diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/console/Kconfig | 25 | ||||
| -rw-r--r-- | src/lib/usbdebug.c | 19 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/enable_usbdebug.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/enable_usbdebug.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/sb800/enable_usbdebug.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/enable_usbdebug.c | 3 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/enable_usbdebug.c | 3 | ||||
| -rw-r--r-- | src/southbridge/sis/sis966/enable_usbdebug.c | 3 |
12 files changed, 24 insertions, 51 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig index c5e5f28449..b753be4023 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -146,9 +146,6 @@ config HAVE_USBDEBUG def_bool n config USBDEBUG - def_bool n - -config USBDEBUG bool "USB 2.0 EHCI debug dongle support" default n depends on HAVE_USBDEBUG @@ -169,25 +166,21 @@ config USBDEBUG If unsure, say N. -# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges -# as those hardcode the physical USB port to be used as Debug Port to 1. -# It cannot be changed by coreboot. config USBDEBUG_DEFAULT_PORT int "Default USB port to use as Debug Port" - default 1 - depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600 + default 0 + depends on USBDEBUG help - This option selects which physical USB port coreboot will try to - use as EHCI Debug Port first (valid values are: 1-15). + Selects which physical USB port usbdebug dongle is connected to. + Setting of 0 means to scan possible ports starting from 1. - If coreboot doesn't detect an EHCI Debug Port dongle on this port, - it will try all the other ports one after the other. This will take - a few seconds of time though, and thus slow down the booting process. + Intel platforms have hardwired the debug port location and this + setting makes no difference there. Hence, if you select the correct port here, you can speed up - your boot time. Which USB port number (1-15) refers to which - actual port on your mainboard (potentially also USB pin headers - on your mainboard) is highly board-specific, and you'll likely + your boot time. Which USB port number refers to which actual + port on your mainboard (potentially also USB pin headers on + your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error. # TODO: Deps? diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 4a1228f158..c9247881f0 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -421,8 +421,13 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; - memset(&info->ep_pipe, 0, sizeof (info->ep_pipe)); + + if (CONFIG_USBDEBUG_DEFAULT_PORT > 0) + set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT); + else + set_debug_port(1); + try_next_time: port_map_tried = 0; @@ -630,6 +635,7 @@ err: //return ret; next_debug_port: +#if CONFIG_USBDEBUG_DEFAULT_PORT==0 port_map_tried |= (1 << (debug_port - 1)); new_debug_port = ((debug_port-1 + 1) % n_ports) + 1; if (port_map_tried != ((1 << n_ports) - 1)) { @@ -637,10 +643,15 @@ next_debug_port: goto try_next_port; } if (--playtimes) { - //set_debug_port(new_debug_port); - set_debug_port(debug_port); + set_debug_port(new_debug_port); goto try_next_time; } +#else + if (0) + goto try_next_port; + if (--playtimes) + goto try_next_time; +#endif return -10; } @@ -774,7 +785,7 @@ int usbdebug_init(void) struct ehci_debug_info *dbg_info = dbgp_ehci_info(); #if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE - enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + enable_usbdebug(0); #endif return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index dda29c1724..6fa17817f9 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -57,5 +57,4 @@ void enable_usbdebug(unsigned int port) EHCI_BAR_INDEX, CONFIG_EHCI_BAR); pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - set_debug_port(port); } diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 4ae4641b86..fe9468d4af 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET hex default 0xe0 -config USBDEBUG_DEFAULT_PORT - int - default 0 - choice prompt "SATA Mode" default SATA_MODE_IDE diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index d20c8c4fe1..40c53aecfa 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -36,9 +36,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ - /* Select the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 3aaf7c82bf..0712d2af2d 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -58,9 +58,4 @@ void enable_usbdebug(unsigned int port) /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - /* - * Select the requested physical USB port (1-15) as the Debug Port. - * Must be called after the EHCI BAR has been set up (see above). - */ - set_debug_port(port); } diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 09f742915d..6422fa2295 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -57,5 +57,4 @@ void enable_usbdebug(unsigned int port) EHCI_BAR_INDEX, CONFIG_EHCI_BAR); pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - set_debug_port(port); } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d4a6baa2ce..62c6b436f2 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 -config USBDEBUG_DEFAULT_PORT - int - default 1 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801gx/bootblock.c" diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index dd07dac7a2..8a4a53ef78 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -37,10 +37,6 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 -config USBDEBUG_DEFAULT_PORT - int - default 1 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801ix/bootblock.c" diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 90890e6802..d65fea212d 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -52,9 +52,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index 069344b522..f629c505c3 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -46,9 +46,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index f38fe90398..04384ba9ac 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -48,9 +48,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); |