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-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 94b54a66d3..8b3794f4e9 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -92,6 +92,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable Cpu Ratio Override temporary. */
m_cfg->CpuRatio = 0;
+ m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)