diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/pmic_wrap_common.h | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/emi.c | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/pmic_wrap.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/mt6391.c | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/spm.c | 2 |
7 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 0b9f2d3860..bf64164948 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -69,7 +69,7 @@ static inline s32 pwrap_write_nochk(u16 addr, u16 wdata) return pwrap_wacs2(1, addr, wdata, 0, 0); } -/* dewrapper defaule value */ +/* dewrapper default value */ enum { DEFAULT_VALUE_READ_TEST = 0x5aa5, WRITE_TEST_VALUE = 0xa55a @@ -81,7 +81,7 @@ enum { TIMEOUT_WAIT_IDLE_US = 255 }; -/* manual commnd */ +/* manual command */ enum { OP_WR = 0x1, OP_CSH = 0x0, diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 58dce72e94..4fafb049d2 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -450,7 +450,7 @@ static void dramc_set_mrs_value(int channel, int rank, mrs_write(channel, rank, sdram_params->mrs_set.mrs_63, 10); /* MR10 -> ZQ Init, tZQINIT>=1us */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_10, 1); - /* MR3 driving stregth set to max */ + /* MR3 driving strength set to max */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_3, 1); /* MR1 */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_1, 1); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 492238a80c..f6c866bfdb 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -971,9 +971,9 @@ void perbit_window_cal(u32 channel, u8 type) dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2; } - /* 1. delay DQ,find the pass widnow (left boundary) + /* 1. delay DQ,find the pass window (left boundary) * 2. delay DQS find the pass window (right boundary) - * 3. find the best DQ / DQS to satify the middle value + * 3. find the best DQ / DQS to satisfy the middle value * of the overall pass window per bit * 4. set DQS delay to the max per byte, delay DQ to de-skew */ diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f3ea7614e4..12f08379ea 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -148,7 +148,7 @@ size_t sdram_size(void) 9; /* check if row address */ - /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ + /* 00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + 13; @@ -159,7 +159,7 @@ size_t sdram_size(void) /* add bank address bit, LPDDR3 is 8 banks =2^3 */ bit_counter += 3; - /*transfor bits to bytes */ + /* transform bits to bytes */ return ((size_t)1 << (bit_counter - 3)); } diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index 3687a2992d..d6c58a5ca0 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -125,7 +125,7 @@ struct mt8173_pwrap_regs { check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148); -/* dewrapper regsister */ +/* dewrapper register */ enum { DEW_EVENT_OUT_EN = DEW_BASE + 0x0, DEW_DIO_EN = DEW_BASE + 0x2, diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2656d7252d..3f77c8accc 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -201,7 +201,7 @@ static void mt6391_init_setting(void) pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); - /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); @@ -359,7 +359,7 @@ static void mt6391_init_setting(void) pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0); - /* 26M clock amplitute adjust */ + /* 26M clock amplitude adjust */ pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11); diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 024fe1c9fc..020da934ab 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -274,7 +274,7 @@ static int spm_load_firmware(enum dyna_load_pcm_index index, offset += copy_size; /* version */ - /* The termintating character should be contained in the spm binary */ + /* The terminating character should be contained in the spm binary */ assert(spm_bin[file_size - 1] == '\0'); assert(offset < file_size); printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset); |