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-rw-r--r--src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb6
-rw-r--r--src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb6
-rw-r--r--src/mainboard/foxconn/g41s-k/devicetree.cb7
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb7
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb7
-rw-r--r--src/mainboard/roda/rv11/variants/rw11/devicetree.cb4
-rw-r--r--src/superio/ite/common/env_ctrl.c16
-rw-r--r--src/superio/ite/common/env_ctrl.h20
-rw-r--r--src/superio/ite/common/env_ctrl_chip.h23
9 files changed, 68 insertions, 28 deletions
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
index e1fbc51572..349a84533d 100644
--- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
@@ -58,9 +58,9 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/ite/it8728f
- register "TMPIN1" = "THERMAL_RESISTOR"
- register "TMPIN2" = "THERMAL_RESISTOR"
- register "TMPIN3" = "THERMAL_RESISTOR"
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
register "FAN1.smart.tmpin" = "1"
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
index 128ff1847d..af0e4cc9db 100644
--- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
@@ -58,9 +58,9 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/ite/it8728f
- register "TMPIN1" = "THERMAL_RESISTOR"
- register "TMPIN2" = "THERMAL_RESISTOR"
- register "TMPIN3" = "THERMAL_RESISTOR"
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
register "FAN1.smart.tmpin" = "1"
diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb
index fae89e65fb..e57436ae7c 100644
--- a/src/mainboard/foxconn/g41s-k/devicetree.cb
+++ b/src/mainboard/foxconn/g41s-k/devicetree.cb
@@ -85,9 +85,10 @@ chip northbridge/intel/x4x # Northbridge
device pci 1f.0 on # ISA bridge
subsystemid 0x105b 0x0dda
chip superio/ite/it8720f # Super I/O
- register "TMPIN1" = "THERMAL_DIODE"
- register "TMPIN2" = "THERMAL_RESISTOR"
- register "TMPIN3" = "THERMAL_MODE_DISABLED"
+ register "TMPIN1.mode" = "THERMAL_DIODE"
+ register "TMPIN1.offset" = "0"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
register "ec.vin_mask" = "VIN_ALL"
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index acf743b18c..6bdc134b9a 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -110,9 +110,10 @@ chip northbridge/intel/i945
device pci 1f.0 on # LPC bridge
ioapic_irq 2 INTA 0x10
chip superio/ite/it8718f # Super I/O
- register "TMPIN1" = "THERMAL_RESISTOR"
- register "TMPIN2" = "THERMAL_RESISTOR"
- register "TMPIN3" = "THERMAL_DIODE"
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_DIODE"
+ register "TMPIN3.offset" = "0"
register "ec.vin_mask" = "VIN_ALL"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index 60004d25ea..39f790890e 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -82,9 +82,10 @@ chip northbridge/intel/x4x # Northbridge
device pci 1f.0 on # ISA bridge
subsystemid 0x1458 0x5001
chip superio/ite/it8718f # Super I/O
- register "TMPIN1" = "THERMAL_RESISTOR"
- register "TMPIN2" = "THERMAL_RESISTOR"
- register "TMPIN3" = "THERMAL_DIODE"
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_DIODE"
+ register "TMPIN3.offset" = "0"
register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
index 845bca8183..d5f744e98f 100644
--- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -113,8 +113,8 @@ chip northbridge/intel/sandybridge
end
end
chip superio/ite/it8783ef
- register "TMPIN1" = "THERMAL_RESISTOR"
- register "TMPIN2" = "THERMAL_RESISTOR"
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
register "ec.vin_mask" = "VIN_ALL"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
register "FAN1.smart.tmpin" = " 1"
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 1e313ce715..c8274db6c8 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -99,13 +99,13 @@ static void enable_peci(const u16 base, const u8 tmpin)
* into TMPINx register
*/
static void enable_tmpin(const u16 base, const u8 tmpin,
- const enum ite_ec_thermal_mode mode)
+ const struct ite_ec_thermal_config *const conf)
{
u8 reg;
reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE);
- switch (mode) {
+ switch (conf->mode) {
case THERMAL_DIODE:
reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin);
break;
@@ -115,12 +115,20 @@ static void enable_tmpin(const u16 base, const u8 tmpin,
default:
printk(BIOS_WARNING,
"Unsupported thermal mode 0x%x on TMPIN%d\n",
- mode, tmpin);
+ conf->mode, tmpin);
return;
}
ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg);
+ /* Set temperature offsets */
+ if (conf->mode != THERMAL_RESISTOR) {
+ reg = ite_ec_read(base, ITE_EC_BEEP_ENABLE);
+ reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE;
+ ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg);
+ ite_ec_write(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset);
+ }
+
/* Enable the startup of monitoring operation */
reg = ite_ec_read(base, ITE_EC_CONFIGURATION);
reg |= ITE_EC_CONFIGURATION_START;
@@ -233,7 +241,7 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf)
/* Enable HWM if configured */
for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
- enable_tmpin(base, i + 1, conf->tmpin_mode[i]);
+ enable_tmpin(base, i + 1, &conf->tmpin[i]);
/* Enable reading of voltage pins */
ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h
index fa131166c0..1be6436310 100644
--- a/src/superio/ite/common/env_ctrl.h
+++ b/src/superio/ite/common/env_ctrl.h
@@ -93,6 +93,26 @@
#define ITE_EC_ADC_TEMP_DIODE_MODE(x) (1 << ((x)-1))
#define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55
+/* Matches length of ITE_EC_TMPIN_CNT */
+static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 };
+
+#define ITE_EC_BEEP_ENABLE 0x5C
+#define ITE_EC_TEMP_ADJUST_WRITE_ENABLE (1 << 7)
+#define ITE_EC_ADC_CLOCK_1MHZ (6 << 4)
+#define ITE_EC_ADC_CLOCK_2MHZ (7 << 4)
+#define ITE_EC_ADC_CLOCK_24MHZ (5 << 4)
+#define ITE_EC_ADC_CLOCK_31KHZ (4 << 4)
+#define ITE_EC_ADC_CLOCK_62KHZ (3 << 4)
+#define ITE_EC_ADC_CLOCK_125KHZ (2 << 4)
+#define ITE_EC_ADC_CLOCK_250KHZ (1 << 4)
+#define ITE_EC_ADC_CLOCK_500KHZ (0 << 4)
+#define ITE_EC_BEEP_ON_TMP_LIMIT (1 << 2)
+#define ITE_EC_BEEP_ON_VIN_LIMIT (1 << 1)
+#define ITE_EC_BEEP_ON_FAN_LIMIT (1 << 0)
+#define ITE_EC_BEEP_FREQ_DIV_OF_FAN 0x5D
+#define ITE_EC_BEEP_FREQ_DIV_OF_VOLT 0x5E
+#define ITE_EC_BEEP_FREQ_DIV_OF_TEMP 0x5F
+
#define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) (0x60 + ((x)-1) * 8)
#define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) (0x61 + ((x)-1) * 8)
#define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) (0x62 + ((x)-1) * 8)
diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h
index f01c574d47..8eb908e77a 100644
--- a/src/superio/ite/common/env_ctrl_chip.h
+++ b/src/superio/ite/common/env_ctrl_chip.h
@@ -28,6 +28,12 @@ enum ite_ec_thermal_mode {
THERMAL_RESISTOR,
};
+struct ite_ec_thermal_config {
+ enum ite_ec_thermal_mode mode;
+ /* Offset is used for diode sensors and PECI */
+ u8 offset;
+};
+
/* Bit mask for voltage pins VINx */
enum ite_ec_voltage_pin {
VIN0 = 0x01,
@@ -74,25 +80,28 @@ struct ite_ec_config {
u8 peci_tmpin;
/*
- * Enable thermal mode on TMPINx.
+ * Enable reading of voltage pins VINx.
*/
- enum ite_ec_thermal_mode tmpin_mode[ITE_EC_TMPIN_CNT];
+ enum ite_ec_voltage_pin vin_mask;
/*
- * Enable reading of voltage pins VINx.
+ * Enable temperature sensors in given mode.
*/
- enum ite_ec_voltage_pin vin_mask;
+ struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT];
/*
* Enable a FAN in given mode.
*/
struct ite_ec_fan_config fan[ITE_EC_FAN_CNT];
+
+ /* FIXME: enable beep when exceeding TMPIN, VIN, FAN limits */
};
/* Some shorthands for device trees */
-#define TMPIN1 ec.tmpin_mode[0]
-#define TMPIN2 ec.tmpin_mode[1]
-#define TMPIN3 ec.tmpin_mode[2]
+#define TMPIN1 ec.tmpin[0]
+#define TMPIN2 ec.tmpin[1]
+#define TMPIN3 ec.tmpin[2]
+
#define FAN1 ec.fan[0]
#define FAN2 ec.fan[1]
#define FAN3 ec.fan[2]
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-08 16:28:45 +0000