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-rw-r--r--src/southbridge/intel/i82801gx/azalia.c3
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.c12
-rw-r--r--src/southbridge/intel/i82801gx/ide.c3
-rw-r--r--src/southbridge/intel/i82801gx/pcie.c4
-rw-r--r--src/southbridge/intel/i82801gx/usb.c4
-rw-r--r--src/southbridge/intel/i82801gx/usb_ehci.c5
6 files changed, 10 insertions, 21 deletions
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 4a2b50e4d4..775326cccf 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -230,8 +230,7 @@ static void azalia_init(struct device *dev)
pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index 1a5366fe87..eae16db3d3 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -54,23 +54,21 @@ static void ich_hide_devfn(unsigned int devfn)
void i82801gx_enable(struct device *dev)
{
- u32 reg32;
+ u16 reg16;
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide this device if possible */
ich_hide_devfn(dev->path.pci.devfn);
} else {
/* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
printk(BIOS_DEBUG, "Set SATA mode early\n");
diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c
index b6b30efea9..cc3e7409d4 100644
--- a/src/southbridge/intel/i82801gx/ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
@@ -30,8 +30,7 @@ static void ide_init(struct device *dev)
enable_secondary = config->ide_enable_secondary;
}
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER);
/* Native Capable, but not enabled. */
pci_write_config8(dev, 0x09, 0x8a);
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 4398ad56b0..4de62e256d 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -47,9 +47,7 @@ static void pci_init(struct device *dev)
printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
/* Enable Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c
index d4b559a37b..d8c55e0981 100644
--- a/src/southbridge/intel/i82801gx/usb.c
+++ b/src/southbridge/intel/i82801gx/usb.c
@@ -10,14 +10,12 @@
static void usb_init(struct device *dev)
{
- u32 reg32;
u8 reg8;
/* USB Specification says the device must be Bus Master */
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
// Erratum
pci_write_config8(dev, 0xca, 0x00);
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index d127496cd6..08211c2f9e 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -18,10 +18,7 @@ static void usb_ehci_init(struct device *dev)
u8 reg8;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
reg32 = pci_read_config32(dev, 0xdc);
reg32 |= (1 << 31) | (1 << 27);