11 files changed, 18 insertions, 9 deletions
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index 87e09d6822..6920c9d941 100755
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY12
 
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 48
 	depends on CPU_AMD_AGESA_FAMILY12
 
 config CPU_SOCKET_TYPE
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
index c1528f63a0..f4c1183f0d 100644
--- a/src/cpu/amd/agesa/family15/Kconfig
+++ b/src/cpu/amd/agesa/family15/Kconfig
@@ -21,6 +21,11 @@ config CPU_AMD_AGESA_FAMILY15
 	bool
 	select PCI_IO_CFG_EXT
 
+config CPU_ADDR_BITS
+	int
+	default 48
+	depends on CPU_AMD_AGESA_FAMILY15
+
 if CPU_AMD_AGESA_FAMILY15
 
 config CPU_AMD_SOCKET_G34
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index 8f3a9ffb44..7459818b77 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY15_TN
 
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 48
 	depends on CPU_AMD_AGESA_FAMILY15_TN
 
 config CPU_SOCKET_TYPE
diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c
index a8ec91710b..e2b6038561 100644
--- a/src/mainboard/amd/dinar/agesawrapper.c
+++ b/src/mainboard/amd/dinar/agesawrapper.c
@@ -270,7 +270,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c
index c180800143..720de4389b 100644
--- a/src/mainboard/amd/parmer/agesawrapper.c
+++ b/src/mainboard/amd/parmer/agesawrapper.c
@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index 67ac8e9e53..7a3616b480 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c
index 2bd172560e..2c7b092d2c 100644
--- a/src/mainboard/amd/torpedo/agesawrapper.c
+++ b/src/mainboard/amd/torpedo/agesawrapper.c
@@ -281,7 +281,7 @@ agesawrapper_amdinitmmio (
   /* Set ROM cache onto WP to decrease post time */
   MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
   LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+  MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
   LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
   /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index d354c370d4..66236edf2e 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig
index e7dae6618d..b93bfadcfc 100644
--- a/src/mainboard/supermicro/h8scm/Kconfig
+++ b/src/mainboard/supermicro/h8scm/Kconfig
@@ -59,6 +59,10 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 16
 
+config CPU_ADDR_BITS
+	int
+	default 36  # TODO: Set it conservatively to match both fam10 & 15
+
 config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c
index aeeab110a3..a84162931c 100644
--- a/src/mainboard/supermicro/h8scm/agesawrapper.c
+++ b/src/mainboard/supermicro/h8scm/agesawrapper.c
@@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c
index 1485354c29..6f18f5c2c4 100644
--- a/src/mainboard/tyan/s8226/agesawrapper.c
+++ b/src/mainboard/tyan/s8226/agesawrapper.c
@@ -204,7 +204,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;