diff options
Diffstat (limited to 'src')
56 files changed, 0 insertions, 296 deletions
diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index 5a0d1a889f..3c77b11e2a 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -24,7 +24,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977f/w83977f_early_serial.c" @@ -40,5 +39,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index a51b64e937..8b7027189b 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -83,9 +83,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index ce4cd1b920..9079044919 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -217,9 +217,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 8d108b3d89..f60313842a 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -84,9 +84,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 86491c0e1b..ade6f62d0f 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -56,7 +56,4 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); msr_init(); - - /* Check all of memory */ - //ram_check(0x00000000, 640*1024); } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index f7f194a7be..5274ef2e4a 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -328,9 +328,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); post_code(0x42); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index e58fa12036..5c7858c19b 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -217,10 +217,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index a8dc6cde59..7b213bf1c7 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -133,8 +133,4 @@ void main(unsigned long bist) msr = rdmsr(MC_CF8F_DATA); print_debug(" \n"); #endif - - /* Check memory. */ - // ram_check(0x00000000, 640 * 1024); - // ram_check(1024 * 1024, 2 * 1024 * 1024); } diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 3b7b199f49..3d3367aa85 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -24,7 +24,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87351/pc87351_early_serial.c" @@ -40,5 +39,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index 118ded48a3..f79c2437b9 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 0x4000); */ } diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index ea93eee412..540ada6432 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -218,10 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index 8074c874e1..f5eeab3c29 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index 8074c874e1..f5eeab3c29 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 802645365a..7d9a5a7d57 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -99,6 +99,4 @@ void main(unsigned long bist) enable_mainboard_devices(); ddr_ram_setup(&ctrl); - - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 04a7cf3f46..3927cd2f33 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/pc8374_early_init.c" @@ -323,17 +322,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 1 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); -// ram_check(0x00100000, 0x01000000); - ram_check(0x00100000, 0x00100100); - /* check the first 1M in the 3rd Gig */ -// ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index a75d60f07a..823e5effa4 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -62,12 +62,5 @@ void main(unsigned long bist) #if 0 dump_pci_devices(); dump_pci_device(PCI_DEV(0, 0, 0)); - - // Check all of memory - ram_check(0x00000000, msr.lo+(msr.hi<<32)); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); - // Check 16MB of memory @ 2GB - ram_check(0x80000000, 0x81000000); #endif } diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 4e6462d1e4..a4994f1f4b 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -6,7 +6,6 @@ #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" void setup_pars(void) @@ -203,16 +202,6 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0, 0)); #endif -#if 0 - print_err("RAM CHECK!\n"); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); -#endif -#if 0 - print_err("RAM CHECK for 32 MB!\n"); - // Check 32MB of memory @ 0 - ram_check(0x00000000, 0x02000000); -#endif #if 1 { volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 14f04941f7..4429914d74 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -66,9 +66,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check all of memory */ - ram_check(0x00000000, 640*1024); - /* Switch from Cache as RAM to real RAM */ /* There are two ways we could think about this. 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code. diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 3d99873bc9..16ea548ff5 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -6,7 +6,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 7b7f239d0e..1f6ebdd1aa 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -214,10 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9a753b9201..21f80c2567 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -216,9 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index 6bde6756c4..a5019ce095 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" #include "cpu/x86/bist.h" @@ -47,5 +46,4 @@ static void main(unsigned long bist) cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 640 * 1024); */ } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 5afa651e05..8ef205aab7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -219,9 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 0900f4ba3e..1d99197293 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" #include "cpu/x86/bist.h" @@ -42,5 +41,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 640 * 1024); */ } diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 4e27f9bbbd..0c06fd2432 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -87,8 +87,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 5d33b10633..e3ab67940e 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" @@ -105,17 +104,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#if 0 - ram_check(0x00000000, 0x02000000); -#endif - -#endif } diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 525f02e7a0..856c69950d 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -118,6 +118,4 @@ void main(unsigned long bist) /* dump_pci_devices(); */ /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */ /* dump_bar14(PCI_DEV(0, 0x00, 0)); */ - - ram_check(0, 1024 * 1024); } diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index c75ce3e732..d6ee7c582f 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -28,7 +28,6 @@ #include <pc80/mc146818rtc.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" @@ -98,9 +97,4 @@ static void main(unsigned long bist) #ifdef TRUXTON_DEBUG dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#ifdef TRUXTON_DEBUG - ram_fill(0x00000000, 0x02000000); - ram_verify(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index f393c301a3..e6fb83f4a6 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -8,7 +8,6 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index daacd1bebd..b0c14968b9 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -104,6 +104,4 @@ void main(unsigned long bist) enable_mainboard_devices(); ddr_ram_setup(&ctrl); - - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 990c878987..a1688dfcb7 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -224,9 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 24008bcfe6..5406b7d05f 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -80,16 +80,4 @@ void main(unsigned long bist) sdram_set_spd_registers(); sdram_enable(); } - -#if 0 - dump_pci_devices(); - dump_pci_device(PCI_DEV(0, 0, 0)); - - // Check all of memory - ram_check(0x00000000, msr.lo+(msr.hi<<32)); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); - // Check 16MB of memory @ 2GB - ram_check(0x80000000, 0x81000000); -#endif } diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 1d63e49243..0abdde4372 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -127,8 +127,4 @@ void main(unsigned long bist) outb( temp, 0x4F); temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! print_debug_hex8(temp);print_debug("\n"); - /* Check all of memory */ -// ram_check(0, 16384); - ram_check(0x20000, 0x24000); -// ram_check(0x00000000, 640*1024); } diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 42f93410ad..35f8fe5c31 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -157,9 +157,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 714411c57d..afe5bd7c09 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -197,9 +197,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 0100caedc3..32f3b3e304 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -122,9 +122,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index ffd9e4ed06..5f940e5661 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -194,9 +194,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 209485ec64..ed9324ea44 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -142,10 +142,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory */ - /* Enable this only if you are having questions. */ - /* ram_check(0, 640 * 1024); */ - /* Switch from Cache as RAM to real RAM. * * There are two ways we could think about this. diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 9fd001ca17..ec77537113 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -166,10 +166,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory */ - /* Enable this only if you are having questions. */ - /* ram_check(0, 640 * 1024); */ - /* Switch from Cache as RAM to real RAM. * * There are two ways we could think about this. diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 65d6bdea69..1fb1440a1b 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -121,8 +121,4 @@ void main(unsigned long bist) /* Initialize memory */ sdram_initialize(); - - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ - /* ram_check(64512 * 1024, 65536 * 1024); */ } diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 2873d8af99..9ae30b0e0a 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" @@ -99,16 +98,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index c5107d9fc1..1865a08dac 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" @@ -103,16 +102,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index af042477d2..fb71fa5f2c 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" @@ -103,16 +102,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); //dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 839be04184..794234ea71 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -48,12 +47,6 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } @@ -110,17 +103,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); -// ram_check(0x00100000, 0x01000000); - ram_check(0x00100000, 0x00100100); - /* check the first 1M in the 3rd Gig */ -// ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 76c94b228f..5e54fa66fa 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -102,17 +101,4 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); -// ram_check(0x00100000, 0x01000000); - ram_check(0x00100000, 0x00100100); - /* check the first 1M in the 3rd Gig */ -// ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 66bfdfc53c..ff296ec23e 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -12,7 +12,6 @@ #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77) @@ -162,12 +161,5 @@ static void main(unsigned long bist) identify_system(); #endif -#if 0 - // Check 32MB of memory @ 0 (very slow!) - print_err("Checking memory:\n"); - ram_check(0x00000000, 0x000a0000); - ram_check(0x000b0000, 0x02000000); -#endif - TS5300_LED_OFF; } diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index 8074c874e1..f5eeab3c29 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index e399dd128f..c9ec8a80b2 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -124,7 +124,4 @@ void main(unsigned long bist) #if CONFIG_LLSHELL llshell(); #endif - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ - /* ram_check(64512 * 1024, 65536 * 1024); */ } diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index f6a4ccfece..3e4ffb5c4c 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -85,9 +85,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 1d37ced6d9..20b4c05675 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -93,5 +93,4 @@ void main(unsigned long bist) report_bist_failure(bist); enable_mainboard_devices(); ddr_ram_setup(&ctrl); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 508d298604..2d887b3f92 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -7,7 +7,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -105,20 +104,6 @@ static void main(unsigned long bist) ddr_ram_setup((const struct mem_controller *)0); - /* Check all of memory */ -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif - if (bist == 0) early_mtrr_init(); diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 90d92383ad..30ea0f2a3a 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -27,7 +27,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -134,6 +133,4 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - - //ram_check(0, 640 * 1024); } diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 2bae6c4c81..870c4e7630 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -6,7 +6,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -95,25 +94,4 @@ static void main(unsigned long bist) sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); sdram_enable(0, (const struct mem_controller *) 0); - - /* Check all of memory */ -#if 0 - ram_check(0x00000000, msr.lo); -#endif -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, -#if TOTAL_CPUS > 1 - /* Check 16MB of memory @ 2GB */ - { 0x80000000, 0x81000000 }, -#endif - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif } diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 657b3cde6b..2b653f79d2 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -67,5 +67,4 @@ void main(unsigned long bist) smbus_fixup(&ctrl); report_bist_failure(bist); ddr_ram_setup(&ctrl); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index becd698c0a..cd615efa4b 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -86,9 +86,6 @@ void main(unsigned long bist) sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index b1ece302fe..f876124336 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -78,7 +78,4 @@ void main(unsigned long bist) print_err("ram setup done\n"); msr_init(); - - /* Check all of memory */ - /*ram_check(0x00000000, 640*1024);*/ } |