4 files changed, 56 insertions, 43 deletions
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 4196144369..3dafc9defd 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -4,15 +4,9 @@
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <device/pci_ops.h>
-#include <reg_script.h>
-#include <spi-generic.h>
 #include <soc/pci_devs.h>
-#include <soc/lpc.h>
-#include <soc/me.h>
-#include <soc/rcba.h>
-#include <soc/spi.h>
+#include <soc/pch.h>
 #include <soc/systemagent.h>
-#include <southbridge/intel/common/spi.h>
 
 /*
  * 16.6 System Agent Configuration Locking
@@ -55,48 +49,13 @@ static void broadwell_systemagent_finalize(void)
 	MCHBAR32(0x6008) = MCHBAR32(0x6008);
 }
 
-const struct reg_script pch_finalize_script[] = {
-#if !CONFIG(EM100PRO_SPI_CONSOLE)
-	/* Lock SPIBAR */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
-		      SPIBAR_HSFS_FLOCKDN),
-#endif
-
-	/* TC Lockdown */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
-
-	/* BIOS Interface Lockdown */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
-
-	/* Function Disable SUS Well Lockdown */
-	REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
-
-	/* Global SMI Lock */
-	REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
-
-	/* GEN_PMCON Lock */
-	REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
-
-	/* PMSYNC */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
-
-	REG_SCRIPT_END
-};
-
 static void broadwell_finalize(void *unused)
 {
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
 
 	broadwell_systemagent_finalize();
 
-	spi_finalize_ops();
-	reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
-
-	/* Lock */
-	RCBA32_OR(0x3a6c, 0x00000001);
-
-	/* Read+Write this R/WO register */
-	RCBA32(LCAP) = RCBA32(LCAP);
+	broadwell_pch_finalize();
 
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h
index 59b5b18f17..cf27499fe5 100644
--- a/src/soc/intel/broadwell/include/soc/pch.h
+++ b/src/soc/intel/broadwell/include/soc/pch.h
@@ -30,4 +30,6 @@ int pch_is_wpt_ulx(void);
 u32 pch_read_soft_strap(int id);
 void pch_disable_devfn(struct device *dev);
 
+void broadwell_pch_finalize(void);
+
 #endif
diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc
index 7e5c65aa76..1c196136c4 100644
--- a/src/soc/intel/broadwell/pch/Makefile.inc
+++ b/src/soc/intel/broadwell/pch/Makefile.inc
@@ -3,6 +3,7 @@ bootblock-y += bootblock.c
 ramstage-y += adsp.c
 romstage-y += early_pch.c
 ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += finalize.c
 ramstage-y += gpio.c
 romstage-y += gpio.c
 smm-y      += gpio.c
diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c
new file mode 100644
index 0000000000..37afded317
--- /dev/null
+++ b/src/soc/intel/broadwell/pch/finalize.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <reg_script.h>
+#include <spi-generic.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
+#include <soc/pch.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
+#include <southbridge/intel/common/spi.h>
+
+const struct reg_script pch_finalize_script[] = {
+#if !CONFIG(EM100PRO_SPI_CONSOLE)
+	/* Lock SPIBAR */
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
+		      SPIBAR_HSFS_FLOCKDN),
+#endif
+
+	/* TC Lockdown */
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
+
+	/* BIOS Interface Lockdown */
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
+
+	/* Function Disable SUS Well Lockdown */
+	REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
+
+	/* Global SMI Lock */
+	REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
+
+	/* GEN_PMCON Lock */
+	REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
+
+	/* PMSYNC */
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
+
+	REG_SCRIPT_END
+};
+
+void broadwell_pch_finalize(void)
+{
+	spi_finalize_ops();
+	reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
+
+	/* Lock */
+	RCBA32_OR(0x3a6c, 0x00000001);
+
+	/* Read+Write this R/WO register */
+	RCBA32(LCAP) = RCBA32(LCAP);
+}