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-rw-r--r--src/soc/intel/cannonlake/fsp_params.c12
-rw-r--r--src/soc/intel/cannonlake/include/soc/pmc.h3
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 6173403395..25ee5e1ebe 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -107,6 +107,17 @@ static void parse_devicetree(FSP_S_CONFIG *params)
parse_devicetree_param(config, params);
}
+/* Ignore LTR value for GBE devices */
+static void ignore_gbe_ltr(void)
+{
+ uint8_t reg8;
+ uint8_t *pmcbase = pmc_mmio_regs();
+
+ reg8 = read8(pmcbase + LTR_IGN);
+ reg8 |= IGN_GBE;
+ write8(pmcbase + LTR_IGN, reg8);
+}
+
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
@@ -168,6 +179,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmSlpS0VmRuntimeControl = 0;
params->PchPmSlpS0Vm070VSupport = 0;
params->PchPmSlpS0Vm075VSupport = 0;
+ ignore_gbe_ltr();
}
}
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 95cca65ab2..67854d4cbd 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -145,6 +145,9 @@
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
#define GBLRST_CAUSE1 0x1928
+#define LTR_IGN 0x1B0C
+#define IGN_GBE (1 << 3)
+
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)