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-rw-r--r--src/cpu/x86/lapic/apic_timer.c6
-rw-r--r--src/include/cpu/intel/speedstep.h1
-rw-r--r--src/mainboard/asus/p5gc-mx/romstage.c2
3 files changed, 6 insertions, 3 deletions
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 254bb07b11..ec2e71c39e 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -48,6 +48,7 @@ static int set_timer_fsb(void)
int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
+ msr_t msr;
get_fms(&c, cpuid_eax(1));
switch (c.x86) {
@@ -74,16 +75,17 @@ static int set_timer_fsb(void)
return 0;
}
case 0xf: /* Netburst */
+ msr = rdmsr(MSR_EBC_FREQUENCY_ID);
switch (c.x86_model) {
case 0x2:
car_set_var(g_timer_fsb,
- f2x_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+ f2x_fsb[(msr.lo >> 16) & 7]);
return 0;
case 0x3:
case 0x4:
case 0x6:
car_set_var(g_timer_fsb,
- core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+ core2_fsb[(msr.lo >> 16) & 7]);
return 0;
} /* default: fallthrough */
default:
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 59336ed0c6..4b556b758b 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -40,6 +40,7 @@
#define IA32_PERF_CTL 0x199
#define MSR_THERM2_CTL 0x19D
#define IA32_MISC_ENABLES 0x1A0
+#define MSR_EBC_FREQUENCY_ID 0x2c
#define MSR_FSB_FREQ 0xcd
#define MSR_FSB_CLOCK_VCC 0xce
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index a29478c7d9..69db496437 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -94,7 +94,7 @@ static u8 msr_get_fsb(void)
/* Netburst */
if (((eax >> 8) & 0xf) == 0xf) {
- msr = rdmsr(0x2c);
+ msr = rdmsr(MSR_EBC_FREQUENCY_ID);
fsbcfg = (msr.lo >> 16) & 0x7;
} else { /* Intel Core 2 */
msr = rdmsr(MSR_FSB_FREQ);