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-rw-r--r--src/soc/intel/cannonlake/chip.h3
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a81a7c1211..7461d78279 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -407,6 +407,9 @@ struct soc_intel_cannonlake_config {
uint8_t DdiPortCDdc;
uint8_t DdiPortDDdc;
uint8_t DdiPortFDdc;
+
+ /* Unlock all GPIO Pads */
+ uint8_t PchUnlockGpioPads;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 25ee5e1ebe..2688557d9b 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -340,6 +340,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
+
+ /* Unlock all GPIO pads */
+ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;
}
/* Mainboard GPIO Configuration */