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-rw-r--r--src/mainboard/google/falco/romstage.c28
-rw-r--r--src/mainboard/google/peppy/romstage.c26
-rw-r--r--src/mainboard/google/slippy/romstage.c26
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c44
-rw-r--r--src/mainboard/intel/wtm2/romstage.c24
-rw-r--r--src/northbridge/intel/haswell/pei_data.h19
6 files changed, 116 insertions, 51 deletions
diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c
index 74ace9b75a..e284491bbd 100644
--- a/src/mainboard/google/falco/romstage.c
+++ b/src/mainboard/google/falco/romstage.c
@@ -129,17 +129,27 @@ void mainboard_romstage_entry(unsigned long bist)
// 3 = disable dimm 0+1 on channel
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
+ // Enable 2x refresh mode
+ ddr_refresh_2x: 1,
max_ddr3_freq: 1600,
usb2_ports: {
- /* Length, Enable, OCn# */
- { 0x0040, 1, 0 }, /* P0: Port A, CN8 */
- { 0x0040, 1, 0 }, /* P1: Port B, CN9 */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
- { 0x0040, 1, 3 }, /* P7: USB2 Port */
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, /* P0: Port A, CN8 */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, /* P1: Port B, CN9 */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
+ USB_PORT_FLEX },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+ USB_PORT_FLEX },
+ { 0x0040, 1, 3, /* P7: USB2 Port */
+ USB_PORT_FRONT_PANEL },
},
usb3_ports: {
/* Enable, OCn# */
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c
index 656f3bc674..bb65f005fe 100644
--- a/src/mainboard/google/peppy/romstage.c
+++ b/src/mainboard/google/peppy/romstage.c
@@ -132,15 +132,23 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb2_ports: {
- /* Length, Enable, OCn# */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */
- { 0x0040, 1, 0 }, /* P1: Port A */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
- { 0x0040, 1, 2 }, /* P4: USB 2.0 Port */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
- { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */
+ /* Length, Enable, OCn#, Location */
+ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 0, /* P1: Port A, CN10 */
+ USB_PORT_BACK_PANEL },
+ { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 2, /* P4: Port B, CN6 */
+ USB_PORT_BACK_PANEL },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
+ USB_PORT_SKIP },
+ { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+ USB_PORT_FLEX },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
+ USB_PORT_SKIP },
},
usb3_ports: {
/* Enable, OCn# */
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index d979203572..a93196a95b 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -159,15 +159,23 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb2_ports: {
- /* Length, Enable, OCn# */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */
- { 0x0040, 1, 0 }, /* P1: Port A, CN10 */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
- { 0x0040, 1, 2 }, /* P4: Port B, CN6 */
- { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
- { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */
+ /* Length, Enable, OCn#, Location */
+ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 0, /* P1: Port A, CN10 */
+ USB_PORT_BACK_PANEL },
+ { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 2, /* P4: Port B, CN6 */
+ USB_PORT_BACK_PANEL },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
+ USB_PORT_SKIP },
+ { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+ USB_PORT_FLEX },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
+ USB_PORT_SKIP },
},
usb3_ports: {
/* Enable, OCn# */
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 1dc49603a9..ee516d9886 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -95,21 +95,35 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel1_disabled: 0,
max_ddr3_freq: 1600,
usb2_ports: {
- /* Length, Enable, OCn# */
- { 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */
- { 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */
- { 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */
- { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */
- { 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */
- { 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */
- { 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */
- { 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */
- { 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */
- { 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */
- { 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */
- { 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */
- { 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
+ USB_PORT_FLEX },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
+ USB_PORT_DOCK },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
+ USB_PORT_FLEX },
+ { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
+ USB_PORT_FRONT_PANEL },
},
usb3_ports: {
/* Enable, OCn# */
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index 0a24e48ba4..c4cce2e2c1 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -101,14 +101,22 @@ void mainboard_romstage_entry(unsigned long bist)
max_ddr3_freq: 1600,
usb2_ports: {
/* Length, Enable, OCn# */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */
- { 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */
- { 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P0: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P1: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P2: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P3: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P4: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P5: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P6: */
+ USB_PORT_FRONT_PANEL },
+ { 0x40, 1, USB_OC_PIN_SKIP, /* P7: */
+ USB_PORT_FRONT_PANEL },
},
usb3_ports: {
/* Enable, OCn# */
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index 73118290bd..b7dc8cf57a 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -31,16 +31,31 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 12
+#define PEI_VERSION 13
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
#define USB_OC_PIN_SKIP 8
+enum usb2_port_location {
+ USB_PORT_BACK_PANEL = 0,
+ USB_PORT_FRONT_PANEL,
+ USB_PORT_DOCK,
+ USB_PORT_MINI_PCIE,
+ USB_PORT_FLEX,
+ USB_PORT_INTERNAL,
+ USB_PORT_SKIP
+};
+
+/* Usb Port Length:
+ * [16:4] = length in inches in octal format
+ * [3:0] = decimal point
+ */
struct usb2_port_setting {
uint16_t length;
uint8_t enable;
uint8_t over_current_pin;
+ uint8_t location;
} __attribute__((packed));
struct usb3_port_setting {
@@ -75,6 +90,8 @@ struct pei_data
// 3 = disable dimm 0+1 on channel
int dimm_channel0_disabled;
int dimm_channel1_disabled;
+ /* Enable 2x Refresh Mode */
+ int ddr_refresh_2x;
/* Data read from flash and passed into MRC */
unsigned char *mrc_input;
unsigned int mrc_input_len;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:32:35 +0000