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-rw-r--r--src/cpu/x86/mtrr/mtrr.c5
-rw-r--r--src/include/boot/coreboot_tables.h8
-rw-r--r--src/include/cpu/x86/mtrr.h3
-rw-r--r--src/lib/coreboot_table.c23
4 files changed, 39 insertions, 0 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index dad10292a9..9c8f8c7647 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -349,6 +349,11 @@ void x86_setup_fixed_mtrrs(void)
#if CONFIG_CACHE_ROM
static long rom_cache_mtrr = -1;
+long x86_mtrr_rom_cache_var_index(void)
+{
+ return rom_cache_mtrr;
+}
+
void x86_mtrr_enable_rom_caching(void)
{
msr_t msr_val;
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index f624ac1e1a..a7e4ab0500 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -250,6 +250,14 @@ struct lb_vboot_handoff {
uint32_t vboot_handoff_size;
};
+#define LB_TAG_X86_ROM_MTRR 0x0021
+struct lb_x86_rom_mtrr {
+ uint32_t tag;
+ uint32_t size;
+ /* The variable range MTRR index covering the ROM. */
+ uint32_t index;
+};
+
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index bff736d296..15a5cad090 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -78,9 +78,12 @@ int x86_mtrr_check(void);
#if CONFIG_CACHE_ROM
void x86_mtrr_enable_rom_caching(void);
void x86_mtrr_disable_rom_caching(void);
+/* Return the variable range MTRR index of the ROM cache. */
+long x86_mtrr_rom_cache_var_index(void);
#else
static inline void x86_mtrr_enable_rom_caching(void) {}
static inline void x86_mtrr_disable_rom_caching(void) {}
+static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
#endif /* CONFIG_CACHE_ROM */
#endif
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index b9a82a831d..765c51001e 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -40,6 +40,9 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
+#if CONFIG_ARCH_X86
+#include <cpu/x86/mtrr.h>
+#endif
static struct lb_header *lb_table_init(unsigned long addr)
{
@@ -237,6 +240,24 @@ static inline void lb_vboot_handoff(struct lb_header *header) {}
#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
#endif /* CONFIG_CHROMEOS */
+static void lb_x86_rom_cache(struct lb_header *header)
+{
+#if CONFIG_ARCH_X86
+ long mtrr_index;
+ struct lb_x86_rom_mtrr *lb_x86_rom_mtrr;
+
+ mtrr_index = x86_mtrr_rom_cache_var_index();
+
+ if (mtrr_index < 0)
+ return;
+
+ lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header);
+ lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR;
+ lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr);
+ lb_x86_rom_mtrr->index = mtrr_index;
+#endif
+}
+
static void add_cbmem_pointers(struct lb_header *header)
{
/*
@@ -539,6 +560,8 @@ unsigned long write_coreboot_table(
lb_strings(head);
/* Record our framebuffer */
lb_framebuffer(head);
+ /* Communicate x86 variable MTRR ROM cache information. */
+ lb_x86_rom_cache(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */