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-rw-r--r--src/arch/mips/bootblock_simple.c2
-rw-r--r--src/soc/imgtec/pistachio/bootblock.c26
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld34
3 files changed, 51 insertions, 11 deletions
diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c
index 747a8bfff6..64bbae23a4 100644
--- a/src/arch/mips/bootblock_simple.c
+++ b/src/arch/mips/bootblock_simple.c
@@ -32,5 +32,7 @@ void main(void)
console_init();
#endif
+ bootblock_mmu_init();
+
run_romstage();
}
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
index 90112646c4..1276a24153 100644
--- a/src/soc/imgtec/pistachio/bootblock.c
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -21,6 +21,9 @@
#include <stdint.h>
#include <arch/cpu.h>
+#include <arch/mmu.h>
+#include <assert.h>
+#include <symbols.h>
static void bootblock_cpu_init(void)
{
@@ -37,3 +40,26 @@ static void bootblock_cpu_init(void)
/* And make sure that it starts from zero. */
write_c0_count(0);
}
+
+static void bootblock_mmu_init(void)
+{
+ uint32_t null_guard_size = 1 * MiB;
+ uint32_t dram_base, dram_size;
+
+ write_c0_wired(0);
+
+ dram_base = (uint32_t)_dram;
+ dram_size = CONFIG_DRAM_SIZE_MB * MiB;
+
+ /*
+ * To be able to catch NULL pointer dereference attempts, lets not map
+ * memory close to zero.
+ */
+ if (dram_base < null_guard_size) {
+ dram_base += null_guard_size;
+ dram_size -= null_guard_size;
+ }
+
+ assert(!identity_map(dram_base, dram_size));
+ assert(!identity_map((uint32_t)_sram, _sram_size));
+}
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 5b50a0a365..802592f4d5 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -23,20 +23,32 @@
SECTIONS
{
- DRAM_START(0x80000000)
- RAMSTAGE(0x80000000, 128K)
+ /*
+ * All of DRAM (other than the DMA coherent area) is accessed through
+ * the identity mapping.
+ */
+ DRAM_START(0x00000000)
+ /* DMA coherent area: accessed via KSEG1. */
+ DMA_COHERENT(0x00100000, 1M)
+ POSTRAM_CBFS_CACHE(0x00200000, 128K)
+ RAMSTAGE(0x00220000, 128K)
- /* GRAM becomes the SRAM. */
- SRAM_START(0x9a000000)
+ /*
+ * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock
+ * and then through the identity mapping in ROM stage.
+ */
+ SRAM_START(0x1a000000)
+ ROMSTAGE(0x1a004800, 36K)
+ PRERAM_CBFS_CACHE(0x1a00d800, 74K)
+ SRAM_END(0x1a020000)
+
+ /* Bootblock executes out of KSEG0 and sets up the identity mapping. */
BOOTBLOCK(0x9a000000, 18K)
- ROMSTAGE(0x9a004800, 36K)
- CBFS_CACHE(0x9a00d800, 74K)
- SRAM_END(0x9a020000)
- /* Let's use SRAM for stack and CBMEM console. */
+ /*
+ * Let's use SRAM for stack and CBMEM console. Always accessed
+ * through KSEG0.
+ */
STACK(0x9b000000, 8K)
PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
-
- /* DMA coherent area: end of available DRAM, uncached */
- DMA_COHERENT(0xAFF00000, 1M)
}