diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/pll_common.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/common/pll.c | 12 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/infracfg.h | 419 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/mcucfg.h | 1038 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/pll.h | 297 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/pll.c | 436 |
6 files changed, 2201 insertions, 3 deletions
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 681b97c5e3..a1bd96d4aa 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -20,6 +20,8 @@ struct mux { void *reg; + void *set_reg; + void *clr_reg; void *upd_reg; u8 mux_shift; u8 mux_width; diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 35b03d845e..539d82cafe 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -12,9 +12,15 @@ void mux_set_sel(const struct mux *mux, u32 sel) u32 mask = GENMASK(mux->mux_width - 1, 0); u32 val = read32(mux->reg); - val &= ~(mask << mux->mux_shift); - val |= (sel & mask) << mux->mux_shift; - write32(mux->reg, val); + if (mux->set_reg && mux->clr_reg) { + write32(mux->clr_reg, mask << mux->mux_shift); + write32(mux->set_reg, sel << mux->mux_shift); + } else { + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + } + if (mux->upd_reg) write32(mux->upd_reg, 1 << mux->upd_shift); } diff --git a/src/soc/mediatek/mt8192/include/soc/infracfg.h b/src/soc/mediatek/mt8192/include/soc/infracfg.h new file mode 100644 index 0000000000..032e6cdd93 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/infracfg.h @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_INFRACFG_H +#define SOC_MEDIATEK_MT8192_INFRACFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_infracfg_regs { + u32 reserved1[20]; + u32 infra_globalcon_dcmctl; /* 0x0050 */ + u32 reserved2[7]; + u32 infra_bus_dcm_ctrl; /* 0x0070 */ + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u32 reserved3[1]; + u32 dramc_wbr; /* 0x00b4 */ + u32 reserved4[2]; + u32 module_sw_cg_3_set; /* 0x00c0 */ + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u32 reserved5[5]; + u32 module_sw_cg_4_set; /* 0x00e0 */ + u32 module_sw_cg_4_clr; + u32 module_sw_cg_4_sta; + u32 reserved6[5]; + u32 i2c_dbtool_misc; /* 0x0100 */ + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u32 reserved7[5]; + u32 infra_globalcon_rst0_set; /* 0x0120 */ + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u32 reserved8[1]; + u32 infra_globalcon_rst1_set; /* 0x0130 */ + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u32 reserved9[1]; + u32 infra_globalcon_rst2_set; /* 0x0140 */ + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u32 reserved10[1]; + u32 infra_globalcon_rst3_set; /* 0x0150 */ + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u32 reserved11[41]; + u32 infra_topaxi_si0_ctl; /* 0x0200 */ + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u32 reserved12[1]; + u32 infra_apb_async_sta; /* 0x0230 */ + u32 infra_topaxi_si2_ctl; + u32 infra_topaxi_fmem_mdhw_ctrl; + u32 infra_conn_gals_ctl; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u32 reserved13[1]; + u32 infra_topaxi_aslice_ctrl; /* 0x0260 */ + u32 infra_topaxi_aslice_ctrl_1; + u32 infra_topaxi_aslice_ctrl_2; + u32 infra_topaxi_aslice_ctrl_3; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 infra_ssusb_dev; + u32 reserved14[1]; + u32 infra_topaxi_emi_gmc_l2c_ctrl; /* 0x0288 */ + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_cbip_slice_ctrl_2; + u32 reserved15[1]; + u32 infra_topaxi_aslice_ctrl_4; /* 0x02b8 */ + u32 reserved16[1]; + u32 infra_topaxi_protecten_mcu; /* 0x02c0 */ + u32 infra_topaxi_protecten_mcu_set; + u32 infra_topaxi_protecten_mcu_clr; + u32 reserved17[1]; + u32 infra_topaxi_protecten_mm; /* 0x02d0 */ + u32 infra_topaxi_protecten_mm_set; + u32 infra_topaxi_protecten_mm_clr; + u32 reserved18[1]; + u32 infra_topaxi_protecten_mcu_sta0; /* 0x02e0 */ + u32 infra_topaxi_protecten_mcu_sta1; + u32 infra_topaxi_protecten_mm_sta0; + u32 infra_topaxi_protecten_mm_sta1; + u32 reserved19[1]; + u32 infra_apu_master_m0_gals_ctl; /* 0x02f4 */ + u32 infra_apu_master_m1_gals_ctl; + u32 infra_topaxi_bus_dbg_con_ao; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u32 reserved20[4]; + u32 md2_bank4_map0; /* 0x0350 */ + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u32 reserved21[1]; + u32 ap2md_dummy; /* 0x0370 */ + u32 reserved22[3]; + u32 conn_map0; /* 0x0380 */ + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 conn_map2; + u32 conn_map3; + u32 conn_map4; + u32 module_clk_sel_set; + u32 module_clk_sel_clr; + u32 pmicw_clock_ctrl_set; + u32 pmicw_clock_ctrl_clr; + u32 dramc_wbr_set; + u32 dramc_wbr_clr; + u32 topaxi_si0_ctl_set; + u32 topaxi_si0_ctl_clr; + u32 topaxi_si1_ctl_set; + u32 topaxi_si1_ctl_clr; + u32 reserved23[14]; + u32 peri_cci_sideband_con; /* 0x0400 */ + u32 mfg_cci_sideband_con; + u32 reserved24[2]; + u32 infra_pwm_cksw_ctrl; /* 0x0410 */ + u32 reserved25[59]; + u32 infra_ao_dbg_con0; /* 0x0500 */ + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 infra_ao_dbg_sta; + u32 reserved26[58]; + u32 mfg_misc_con; /* 0x0600 */ + u32 reserved27[63]; + u32 infra_rsvd0; /* 0x0700 */ + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 infra_topaxi_protecten_2; + u32 infra_topaxi_protecten_set_2; + u32 infra_topaxi_protecten_clr_2; + u32 reserved28[1]; + u32 infra_topaxi_protecten_sta0_2; /* 0x0720 */ + u32 infra_topaxi_protecten_sta1_2; + u32 reserved29[2]; + u32 infra_globalcon_rst4_set; /* 0x0730 */ + u32 infra_globalcon_rst4_clr; + u32 infra_globalcon_rst4_sta; + u32 infra_ao_sec_rst_con4; + u32 reserved30[16]; + u32 mcu2emi_m0_parity; /* 0x0780 */ + u32 mcu2emi_m0_parity_dbg_aw_1; + u32 mcu2emi_m0_parity_dbg_aw_2; + u32 mcu2emi_m0_parity_dbg_ar_1; + u32 mcu2emi_m0_parity_dbg_ar_2; + u32 mcu2emi_m1_parity; + u32 mcu2emi_m1_parity_dbg_aw_1; + u32 mcu2emi_m1_parity_dbg_aw_2; + u32 mcu2emi_m1_parity_dbg_ar_1; + u32 mcu2emi_m1_parity_dbg_ar_2; + u32 mcu2ifr_reg_parity; + u32 mcu2ifr_reg_parity_dbg_aw_1; + u32 mcu2ifr_reg_parity_dbg_aw_2; + u32 mcu2ifr_reg_parity_dbg_ar_1; + u32 mcu2ifr_reg_parity_dbg_ar_2; + u32 ifr_l3c2mcu_parity; + u32 ifr_l3c2mcu_parity_dbg_r_1; + u32 reserved31[47]; + u32 md1_sbc_key0; /* 0x0880 */ + u32 md1_sbc_key1; + u32 md1_sbc_key2; + u32 md1_sbc_key3; + u32 md1_sbc_key4; + u32 md1_sbc_key5; + u32 md1_sbc_key6; + u32 md1_sbc_key7; + u32 md1_sbc_key_lock; + u32 reserved32[1]; + u32 md1_misc_lock; /* 0x08a8 */ + u32 md1_misc; + u32 c2k_sbc_key0; + u32 c2k_sbc_key1; + u32 c2k_sbc_key2; + u32 c2k_sbc_key3; + u32 c2k_sbc_key4; + u32 c2k_sbc_key5; + u32 c2k_sbc_key6; + u32 c2k_sbc_key7; + u32 c2k_sbc_key_lock; + u32 reserved33[11]; + u32 infra_bonding; /* 0x0900 */ + u32 reserved34[63]; + u32 infra_ao_scpsys_apb_async_sta; /* 0x0a00 */ + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 infra_mcu2apu_asl0_ctl; + u32 infra_mcu2reg_asl0_ctl; + u32 infra_mcu_decoder_infra_ctl; + u32 infra_mcu_decoder_sta0; + u32 infra_mcu_decoder_sta1; + u32 infra_idle_async_bit_en_0; + u32 infra_apu_slave_gals_ctrl; + u32 infra_aximem_idle_bit_en_0; + u32 infra_mcu_path_sync_ctl; + u32 infra_conn2ap_int_mask; + u32 infra_mcu_pwr_ctl_mask; + u32 infra_md_rsv; + u32 reserved35[7]; + u32 infra_mem_26m_cksel; /* 0x0a60 */ + u32 reserved36[39]; + u32 pll_ulposc_con0; /* 0x0b00 */ + u32 pll_ulposc_con1; + u32 reserved37[2]; + u32 pll_auxadc_con0; /* 0x0b10 */ + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u32 reserved38[24]; + u32 infra_topaxi_protecten_vdnr; /* 0x0b80 */ + u32 infra_topaxi_protecten_vdnr_set; + u32 infra_topaxi_protecten_vdnr_clr; + u32 infra_topaxi_protecten_vdnr_sta0; + u32 infra_topaxi_protecten_vdnr_sta1; + u32 reserved39[3]; + u32 infra_topaxi_protecten_vdnr_1; /* 0x0ba0 */ + u32 infra_topaxi_protecten_vdnr_set_1; + u32 infra_topaxi_protecten_vdnr_clr_1; + u32 infra_topaxi_protecten_vdnr_sta0_1; + u32 infra_topaxi_protecten_vdnr_sta1_1; + u32 reserved40[19]; + u32 cldma_ctrl; /* 0x0c00 */ + u32 reserved41[63]; + u32 infrabus_dbg0; /* 0x0d00 */ + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 infrabus_dbg17; + u32 infrabus_dbg18; + u32 infrabus_dbg19; + u32 infrabus_dbg20; + u32 infrabus_dbg21; + u32 infrabus_dbg22; + u32 infrabus_dbg23; + u32 infrabus_dbg24; + u32 infrabus_dbg25; + u32 infrabus_dbg26; + u32 infrabus_dbg27; + u32 infrabus_dbg28; + u32 infrabus_dbg29; + u32 infrabus_dbg30; + u32 infrabus_dbg31; + u32 infrabus_dbg32; + u32 infrabus_dbg33; + u32 infrabus_dbg34; + u32 infrabus_dbg35; + u32 infrabus_dbg36; + u32 infrabus_dbg37; + u32 infrabus_dbg38; + u32 infrabus_dbg39; + u32 infrabus_dbg40; + u32 infrabus_dbg41; + u32 infrabus_dbg42; + u32 infrabus_dbg43; + u32 infrabus_dbg44; + u32 infrabus_dbg45; + u32 reserved42[4]; + u32 infra_topaxi_protecten_mm_2; /* 0x0dc8 */ + u32 infra_topaxi_protecten_mm_set_2; + u32 infra_topaxi_protecten_mm_clr_2; + u32 infra_topaxi_protecten_mm_sta0_2; + u32 infra_topaxi_protecten_mm_sta1_2; + u32 reserved43[5]; + u32 infrabus_dbg_mask2; /* 0x0df0 */ + u32 reserved44[19]; + u32 infra_ao_sec_mm0; /* 0x0e40 */ + u32 infra_ao_sec_mm1; + u32 infra_ao_sec_mm2; + u32 infra_ao_sec_mm3; + u32 infra_ao_sec_mm4; + u32 infra_ao_sec_mm5; + u32 infra_ao_sec_mm6; + u32 infra_ao_sec_mm7; + u32 infra_ao_sec_mm8; + u32 infra_ao_sec_mm9; + u32 infra_ao_sec_mm10; + u32 infra_ao_sec_mm11; + u32 infra_ao_sec_mm12; + u32 infra_ao_sec_mm13; + u32 infra_ao_sec_mm14; + u32 infra_ao_sec_mm15; + u32 infra_ao_sec_mm16; + u32 reserved45[5]; + u32 infra_ao_mm_hang_free; /* 0x0e98 */ + u32 infra_ao_module_hang_free; + u32 reserved46[24]; + u32 infra_misc; /* 0x0f00 */ + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u32 reserved47[27]; + u32 infra_ao_sec_con; /* 0x0f80 */ + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u32 reserved48[1]; + u32 infra_ao_sec_cg_con2; /* 0x0f9c */ + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u32 reserved49[2]; + u32 infra_ao_sec_hyp; /* 0x0fb0 */ + u32 infra_ao_sec_mfg_hyp; +}; + +check_member(mt8192_infracfg_regs, infra_globalcon_dcmctl, 0x0050); +check_member(mt8192_infracfg_regs, infra_bus_dcm_ctrl, 0x0070); +check_member(mt8192_infracfg_regs, module_sw_cg_3_set, 0x00c0); +check_member(mt8192_infracfg_regs, module_sw_cg_4_set, 0x00e0); +check_member(mt8192_infracfg_regs, i2c_dbtool_misc, 0x0100); +check_member(mt8192_infracfg_regs, infra_globalcon_rst0_set, 0x0120); +check_member(mt8192_infracfg_regs, infra_topaxi_si0_ctl, 0x0200); +check_member(mt8192_infracfg_regs, md2_bank4_map0, 0x0350); +check_member(mt8192_infracfg_regs, conn_map0, 0x0380); +check_member(mt8192_infracfg_regs, peri_cci_sideband_con, 0x0400); +check_member(mt8192_infracfg_regs, infra_pwm_cksw_ctrl, 0x0410); +check_member(mt8192_infracfg_regs, infra_ao_dbg_con0, 0x0500); +check_member(mt8192_infracfg_regs, mfg_misc_con, 0x0600); +check_member(mt8192_infracfg_regs, infra_rsvd0, 0x0700); +check_member(mt8192_infracfg_regs, infra_globalcon_rst4_set, 0x0730); +check_member(mt8192_infracfg_regs, mcu2emi_m0_parity, 0x0780); +check_member(mt8192_infracfg_regs, md1_sbc_key0, 0x0880); +check_member(mt8192_infracfg_regs, infra_bonding, 0x0900); +check_member(mt8192_infracfg_regs, infra_ao_scpsys_apb_async_sta, 0x0a00); +check_member(mt8192_infracfg_regs, infra_mem_26m_cksel, 0x0a60); +check_member(mt8192_infracfg_regs, pll_ulposc_con0, 0x0b00); +check_member(mt8192_infracfg_regs, pll_auxadc_con0, 0x0b10); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr, 0x0b80); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr_1, 0x0ba0); +check_member(mt8192_infracfg_regs, cldma_ctrl, 0x0c00); +check_member(mt8192_infracfg_regs, infrabus_dbg0, 0x0d00); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_mm_2, 0x0dc8); +check_member(mt8192_infracfg_regs, infrabus_dbg_mask2, 0x0df0); +check_member(mt8192_infracfg_regs, infra_ao_sec_mm0, 0x0e40); +check_member(mt8192_infracfg_regs, infra_ao_mm_hang_free, 0x0e98); +check_member(mt8192_infracfg_regs, infra_misc, 0x0f00); +check_member(mt8192_infracfg_regs, infra_ao_sec_con, 0x0f80); +check_member(mt8192_infracfg_regs, infra_ao_sec_hyp, 0x0fb0); +check_member(mt8192_infracfg_regs, infra_ao_sec_mfg_hyp, 0x0fb4); + +static struct mt8192_infracfg_regs *const mt8192_infracfg = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8192_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/mcucfg.h b/src/soc/mediatek/mt8192/include/soc/mcucfg.h new file mode 100644 index 0000000000..1d270ecd41 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mcucfg.h @@ -0,0 +1,1038 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_MCUCFG_H +#define SOC_MEDIATEK_MT8192_MCUCFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_mcucfg_regs { + u32 reserved1[2]; + u32 mbista_mcsi_sf1_con; /* 0x0008 */ + u32 mbista_mcsi_sf1_result; + u32 mbista_mcsi_sf2_con; + u32 mbista_mcsi_sf2_result; + u32 mbista_etb_con; + u32 mbista_etb_result; + u32 mbista_rstb; + u32 mbista_all_result; + u32 reserved2[2]; + u32 mbist_trigger_mux_ctl; /* 0x0030 */ + u32 reserved3[3]; + u32 dfd_ctrl; /* 0x0040 */ + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 reserved4[5]; + u32 mp_top_dbg_mon_sel; /* 0x0060 */ + u32 mp_top_dbg_mon; + u32 mp0_dbg_mon_sel; + u32 mp0_dbg_mon; + u32 reserved5[28]; + u32 mp0_ptp_sensor_sel; /* 0x00e0 */ + u32 reserved6[5]; + u32 armpll_jit_clk_out_sel; /* 0x00f8 */ + u32 reserved7[1]; + u32 cci_tra_cfg0; /* 0x0100 */ + u32 reserved8[4]; + u32 cci_tra_cfg5; /* 0x0114 */ + u32 cci_tra_cfg6; + u32 cci_tra_cfg7; + u32 cci_tra_cfg8; + u32 cci_tra_cfg9; + u32 cci_tra_cfg10; + u32 cci_tra_cfg11; + u32 cci_tra_cfg12; + u32 reserved9[51]; + u32 cci_m0_tra; /* 0x0200 */ + u32 cci_m1_tra; + u32 cci_m2_tra; + u32 reserved10[5]; + u32 cci_s1_tra; /* 0x0220 */ + u32 cci_s2_tra; + u32 cci_s3_tra; + u32 cci_s4_tra; + u32 reserved11[4]; + u32 cci_m0_tra_latch; /* 0x0240 */ + u32 cci_m1_tra_latch; + u32 cci_m2_tra_latch; + u32 reserved12[5]; + u32 cci_s1_tra_latch; /* 0x0260 */ + u32 cci_s2_tra_latch; + u32 cci_s3_tra_latch; + u32 cci_s4_tra_latch; + u32 reserved13[20]; + u32 cci_m0_if; /* 0x02c0 */ + u32 cci_m1_if; + u32 cci_m2_if; + u32 reserved14[5]; + u32 cci_s1_if; /* 0x02e0 */ + u32 cci_s2_if; + u32 cci_s3_if; + u32 cci_s4_if; + u32 reserved15[12]; + u32 cci_m0_if_latch; /* 0x0320 */ + u32 cci_m1_if_latch; + u32 cci_m2_if_latch; + u32 reserved16[5]; + u32 cci_s1_if_latch; /* 0x0340 */ + u32 cci_s2_if_latch; + u32 cci_s3_if_latch; + u32 cci_s4_if_latch; + u32 reserved17[44]; + u32 l3c_share_status0; /* 0x0400 */ + u32 l3c_share_status1; + u32 l3c_share_status2; + u32 reserved18[1]; + u32 mp0_cpu0_dc_age; /* 0x0410 */ + u32 mp0_cpu1_dc_age; + u32 mp0_cpu2_dc_age; + u32 mp0_cpu3_dc_age; + u32 mp0_cpu4_dc_age; + u32 mp0_cpu5_dc_age; + u32 mp0_cpu6_dc_age; + u32 mp0_cpu7_dc_age; + u32 reserved19[52]; + u32 mp0_cpu0_nonwfx_ctrl; /* 0x0500 */ + u32 mp0_cpu0_nonwfx_cnt; + u32 mp0_cpu1_nonwfx_ctrl; + u32 mp0_cpu1_nonwfx_cnt; + u32 mp0_cpu2_nonwfx_ctrl; + u32 mp0_cpu2_nonwfx_cnt; + u32 mp0_cpu3_nonwfx_ctrl; + u32 mp0_cpu3_nonwfx_cnt; + u32 mp0_cpu4_nonwfx_ctrl; + u32 mp0_cpu4_nonwfx_cnt; + u32 mp0_cpu5_nonwfx_ctrl; + u32 mp0_cpu5_nonwfx_cnt; + u32 mp0_cpu6_nonwfx_ctrl; + u32 mp0_cpu6_nonwfx_cnt; + u32 mp0_cpu7_nonwfx_ctrl; + u32 mp0_cpu7_nonwfx_cnt; + u32 reserved20[48]; + u32 mp0_ses_apb_trig; /* 0x0600 */ + u32 mp0_ses_clk_en; + u32 reserved21[2]; + u32 wfx_ret_met_dbc_sel; /* 0x0610 */ + u32 reserved22[3]; + u32 adb_bist_cfg1; /* 0x0620 */ + u32 adb_bist_cfg2_md; + u32 adb_bist_cfg3_go; + u32 adb_bist_done; + u32 adb_bist_pass; + u32 adb_bist_done1; + u32 reserved23[1]; + u32 adb_bist_pass1; /* 0x063c */ + u32 reserved24[48]; + u32 axi2acp_cfg_ctrl; /* 0x0700 */ + u32 axi2acp_cfg_mask_id; + u32 reserved25[2]; + u32 axi2acp_ar_def_set; /* 0x0710 */ + u32 reserved26[1]; + u32 axi2acp_aw_def_set; /* 0x0718 */ + u32 reserved27[1]; + u32 axi2acp_err_addr0; /* 0x0720 */ + u32 axi2acp_err_addr1; + u32 axi2acp_err_st; + u32 axi2acp_err_id; + u32 axi2acp_err_irq; + u32 axi2acp_err_dbgout; + u32 reserved28[50]; + u32 mst_ccim0_inject_fault; /* 0x0800 */ + u32 mst_ccim0_rec_par; + u32 mst_ccim0_log_rid; + u32 reserved29[1]; + u32 mst_ccim0_log_rd0; /* 0x0810 */ + u32 mst_ccim0_log_rd1; + u32 mst_ccim0_log_rd2; + u32 mst_ccim0_log_rd3; + u32 mst_ccim1_inject_fault; + u32 mst_ccim1_rec_par; + u32 mst_ccim1_log_rid; + u32 reserved30[1]; + u32 mst_ccim1_log_rd0; /* 0x0830 */ + u32 mst_ccim1_log_rd1; + u32 mst_ccim1_log_rd2; + u32 mst_ccim1_log_rd3; + u32 mst_intaxi_inject_fault; + u32 mst_intaxi_rec_par; + u32 mst_intaxi_log_rid; + u32 reserved31[1]; + u32 mst_intaxi_log_rd0; /* 0x0850 */ + u32 mst_intaxi_log_rd1; + u32 reserved32[2]; + u32 slv_1to2_inject_fault; /* 0x0860 */ + u32 slv_1to2_rec_par; + u32 slv_1to2_log_awid; + u32 slv_1to2_log_arid; + u32 slv_1to2_log_awa0; + u32 slv_1to2_log_awa1; + u32 slv_1to2_log_ara0; + u32 slv_1to2_log_ara1; + u32 slv_1to2_log_wid; + u32 reserved33[3]; + u32 slv_1to2_log_wd0; /* 0x0890 */ + u32 slv_1to2_log_wd1; + u32 slv_1to2_log_wd2; + u32 slv_1to2_log_wd3; + u32 slv_l3c_inject_fault; + u32 slv_l3c_rec_par; + u32 slv_l3c_log_awid; + u32 slv_l3c_log_arid; + u32 slv_l3c_log_awa0; + u32 slv_l3c_log_awa1; + u32 slv_l3c_log_ara0; + u32 slv_l3c_log_ara1; + u32 slv_l3c_log_wid; + u32 reserved34[1]; + u32 slv_l3c_log_wd0; /* 0x08c8 */ + u32 slv_l3c_log_wd1; + u32 slv_gic_inject_fault; + u32 slv_gic_rec_par; + u32 slv_gic_log_awid; + u32 slv_gic_log_arid; + u32 slv_gic_log_awa0; + u32 slv_gic_log_awa1; + u32 slv_gic_log_ara0; + u32 slv_gic_log_ara1; + u32 slv_gic_log_wid; + u32 reserved35[1]; + u32 slv_gic_log_wd0; /* 0x08f8 */ + u32 slv_gic_log_wd1; + u32 reserved36[64]; + u32 ildo_vin_big0; /* 0x0a00 */ + u32 ildo_out_big0; + u32 ildo_ovstck_big0; + u32 ildo_vo2hck_big0; + u32 ildo_mhstck_big0; + u32 ildo_mlstck_big0; + u32 ilod_uvwin_big0; + u32 ilod_ovwin_big0; + u32 ildo_pd_cfg_big0; + u32 reserved37[3]; + u32 ildo_vin_big1; /* 0x0a30 */ + u32 ildo_out_big1; + u32 ildo_ovstck_big1; + u32 ildo_vo2hck_big1; + u32 ildo_mhstck_big1; + u32 ildo_mlstck_big1; + u32 ilod_uvwin_big1; + u32 ilod_ovwin_big1; + u32 ildo_pd_cfg_big1; + u32 reserved38[3]; + u32 ildo_vin_big2; /* 0x0a60 */ + u32 ildo_out_big2; + u32 ildo_ovstck_big2; + u32 ildo_vo2hck_big2; + u32 ildo_mhstck_big2; + u32 ildo_mlstck_big2; + u32 ilod_uvwin_big2; + u32 ilod_ovwin_big2; + u32 ildo_pd_cfg_big2; + u32 reserved39[3]; + u32 ildo_vin_big3; /* 0x0a90 */ + u32 ildo_out_big3; + u32 ildo_ovstck_big3; + u32 ildo_vo2hck_big3; + u32 ildo_mhstck_big3; + u32 ildo_mlstck_big3; + u32 ilod_uvwin_big3; + u32 ilod_ovwin_big3; + u32 ildo_pd_cfg_big3; + u32 reserved40[1495]; + u32 l3c_share_cfg0; /* 0x2210 */ + u32 l3c_share_cfg1; + u32 l3c_share_cfg2; + u32 reserved41[1]; + u32 udi_cfg0; /* 0x2220 */ + u32 udi_cfg1; + u32 reserved42[2]; + u32 mcusys_core_status; /* 0x2230 */ + u32 reserved43[1]; + u32 cfg_sys_valid; /* 0x2238 */ + u32 cfg_sysbase_addr_0; + u32 cfg_sysbase_addr_1; + u32 cfg_sysbase_addr_2; + u32 cfg_sysbase_addr_3; + u32 cfg_sysbase_addr_4; + u32 reserved44[4]; + u32 mcusys_base; /* 0x2260 */ + u32 l3c_sram_base; + u32 gic_periph_base; + u32 cci_periph_base; + u32 cci_periph_infra_base; + u32 dfd_sram_base; + u32 l3c_mm_sram_base; + u32 ext_l3c_sram_base; + u32 ext_gic_periph_base; + u32 mcusys_qos_shaper_degree; + u32 mcusys_qos_shaper_others; + u32 mcusys_qos_age_set_enable; + u32 sspm_cpueb_turbo_pll_ctl; + u32 cpu_eb_apb_base; + u32 cpu_eb_tcm_btb_delsel; + u32 cpu_eb_mem_misc; + u32 cpu_plldiv_cfg0; + u32 cpu_plldiv_cfg1; + u32 cpu_plldiv_cfg2; + u32 cpu_plldiv_cfg3; + u32 cpu_plldiv_cfg4; + u32 reserved45[11]; + u32 bus_plldiv_cfg; /* 0x22e0 */ + u32 reserved46[3]; + u32 plldiv_ctl0; /* 0x22f0 */ + u32 reserved47[3]; + u32 mcsi_ram_delsel0; /* 0x2300 */ + u32 mcsi_ram_delsel1; + u32 reserved48[30]; + u32 etb_cfg0; /* 0x2380 */ + u32 reserved49[3]; + u32 bus_parity_gen_en; /* 0x2390 */ + u32 bus_parity_clr; + u32 bus_parity_chk_en; + u32 bus_parity_fail; + u32 dsu2biu_addr_remap_cfg; + u32 dsu2biu_addr_remap_sta; + u32 reserved50[2]; + u32 dsu2biu_addr_remap_0_cfg0; /* 0x23b0 */ + u32 dsu2biu_addr_remap_0_cfg1; + u32 dsu2biu_addr_remap_0_cfg2; + u32 reserved51[1]; + u32 dsu2biu_addr_remap_1_cfg0; /* 0x23c0 */ + u32 dsu2biu_addr_remap_1_cfg1; + u32 dsu2biu_addr_remap_1_cfg2; + u32 reserved52[1]; + u32 dsu2biu_addr_remap_magic; /* 0x23d0 */ + u32 reserved53[11]; + u32 cci_rgu; /* 0x2400 */ + u32 reserved54[3]; + u32 mcsi_cfg0; /* 0x2410 */ + u32 mcsi_cfg1; + u32 mcsi_cfg2; + u32 mcsi_cfg3; + u32 mcsi_cfg4; + u32 reserved55[7]; + u32 mcsic_dcm0; /* 0x2440 */ + u32 mcsic_dcm1; + u32 reserved56[18]; + u32 apmcu2emi_early_cke_ctl01; /* 0x2490 */ + u32 reserved57[1]; + u32 apmcu2emi_early_ebg_ctl0; /* 0x2498 */ + u32 apmcu2emi_early_ebg_ctl1; + u32 apmcu2emi_early_ebg_ctl2; + u32 apmcu2emi_early_ebg_ctl3; + u32 apmcu2emi_early_ebg_ctl4; + u32 apmcu2emi_early_ebg_ctl5; + u32 reserved58[20]; + u32 mp_adb_dcm_cfg0; /* 0x2500 */ + u32 reserved59[1]; + u32 mp_adb_dcm_cfg2; /* 0x2508 */ + u32 reserved60[1]; + u32 mp_adb_dcm_cfg4; /* 0x2510 */ + u32 reserved61[1]; + u32 mp_misc_dcm_cfg0; /* 0x2518 */ + u32 reserved62[9]; + u32 etb_ck_ctl; /* 0x2540 */ + u32 reserved63[15]; + u32 dcc_cpu_con0; /* 0x2580 */ + u32 dcc_cpu_con1; + u32 reserved64[6]; + u32 dcc_bus_con0; /* 0x25a0 */ + u32 reserved65[7]; + u32 mcusys_dcm_cfg0; /* 0x25c0 */ + u32 reserved66[79]; + u32 fcm_spmc_sw_cfg1; /* 0x2700 */ + u32 fcm_spmc_sw_cfg2; + u32 fcm_spmc_wait_cfg; + u32 fcm_spmc_sw_pchannel; + u32 fcm_spmc_pwr_status; + u32 fcm_spmc_off_thres; + u32 fcm_spmc_wdt_latch_info; + u32 reserved67[9]; + u32 mcusys_spmc_sw_cfg; /* 0x2740 */ + u32 mcusys_spmc_wait_cfg; + u32 mcusys_spmc_pwr_status; + u32 reserved68[45]; + u32 cpc_pllbuck_req_ctrl; /* 0x2800 */ + u32 mcusys_pwr_ctrl; + u32 cpusys_pwr_ctrl; + u32 sw_gic_wakeup_req; + u32 cpc_pllbuck_arb_weight; + u32 cpc_flow_ctrl_cfg; + u32 cpc_last_core_req; + u32 cpc_cpusys_last_core_resp; + u32 reserved69[1]; + u32 cpc_mcusys_last_core_resp; /* 0x2824 */ + u32 cpc_pwr_on_mask; + u32 reserved70[5]; + u32 cpc_spmc_pwr_status; /* 0x2840 */ + u32 cpc_core_cur_fsm; + u32 cpc_cpusys_mcusys_cur_fsm; + u32 cpc_wakeup_req; + u32 reserved71[1]; + u32 cpc_gp0_gp1_status; /* 0x2854 */ + u32 reserved72[1]; + u32 cpc_turbo_ctrl; /* 0x285c */ + u32 cpc_turbo_gp0_ctrl; + u32 cpc_turbo_gp1_ctrl; + u32 cpc_turbo_gp2_ctrl; + u32 cpc_turbo_pwr_on_mask; + u32 cpc_turbo_gp0_req; + u32 cpc_turbo_gp1_req; + u32 cpc_turbo_gp2_req; + u32 reserved73[1]; + u32 cpc_turbo_gp0_resp; /* 0x2880 */ + u32 cpc_turbo_gp1_resp; + u32 cpc_turbo_gp2_resp; + u32 cpc_coh_block_thres; + u32 cpc_int_status; + u32 cpc_int_enable; + u32 pllbuck_group_func; + u32 cpc_dcm_enable; + u32 cpc_pllbuck_state; + u32 cpc_cpu_on_sw_hint; + u32 cpc_cpu_on_sw_hint_set; + u32 cpc_cpu_on_sw_hint_clear; + u32 reserved74[20]; + u32 emi_wfifo; /* 0x2900 */ + u32 axi1to4_cfg; + u32 apb_cfg; + u32 emi_adb_edge_sel; + u32 reserved75[4]; + u32 sclk_cfg_slow_down_ck; /* 0x2920 */ + u32 reserved76[3]; + u32 acpwakeup; /* 0x2930 */ + u32 reserved77[1]; + u32 l3gic_idle_bypass; /* 0x2938 */ + u32 reserved78[21]; + u32 mcusys_dbg_mon_sel; /* 0x2990 */ + u32 mcusys_dbg_mon; + u32 reserved79[58]; + u32 gic_acao_ctl0; /* 0x2a80 */ + u32 reserved80[1]; + u32 gic_acao_ctl2; /* 0x2a88 */ + u32 reserved81[29]; + u32 spmc_dbg_setting; /* 0x2b00 */ + u32 kernel_base_l; + u32 kernel_base_h; + u32 systime_base_l; + u32 systime_base_h; + u32 trace_data_selection; + u32 reserved82[2]; + u32 trace_data_entry0_l; /* 0x2b20 */ + u32 trace_data_entry0_h; + u32 trace_data_entry1_l; + u32 trace_data_entry1_h; + u32 trace_data_entry2_l; + u32 trace_data_entry2_h; + u32 trace_data_entry3_l; + u32 trace_data_entry3_h; + u32 cpu0_on_off_latency; + u32 cpu1_on_off_latency; + u32 cpu2_on_off_latency; + u32 cpu3_on_off_latency; + u32 cpu4_on_off_latency; + u32 cpu5_on_off_latency; + u32 cpu6_on_off_latency; + u32 cpu7_on_off_latency; + u32 cluster_off_latency; + u32 cluster_on_latency; + u32 mcusys_on_off_latency; + u32 reserved83[1]; + u32 cluster_off_dormant_counter; /* 0x2b70 */ + u32 cluster_off_dormant_counter_clear; + u32 turbo_gp0_gp1_latency; + u32 turbo_gp2_latency; + u32 cpc_wdt_latch_info1; + u32 cpc_wdt_latch_info2; + u32 cpc_wdt_latch_info3; + u32 cpc_wdt_latch_info4; + u32 cpc_wdt_latch_info5; + u32 cpc_pmu_ctrl; + u32 cpc_pmu_cnt_clr; + u32 cpc_pmu_cnt0; + u32 reserved84[4]; + u32 cpc_wdt_latch_info6; /* 0x2bb0 */ + u32 cpc_wdt_latch_info7; + u32 cpc_ptm_event_en_ctrl; + u32 cpc_ptm_event_en_ctrl1; + u32 cpc_ptm_trace_sel; + u32 cpc_ptm_trace_status_l; + u32 cpc_ptm_trace_status_h; + u32 reserved85[29]; + u32 sesv6_bg_ctrl; /* 0x2c40 */ + u32 reserved86[3]; + u32 dsu_sesv6_ao_reg0; /* 0x2c50 */ + u32 dsu_sesv6_ao_reg1; + u32 dsu_sesv6_ao_reg2; + u32 dsu_sesv6_ao_reg3; + u32 dsu_sesv6_ao_reg4; + u32 reserved87[39]; + u32 ildo_dout_sel; /* 0x2d00 */ + u32 reserved88[31]; + u32 dreq20_little_en; /* 0x2d80 */ + u32 reserved89[2]; + u32 dreq20_big_vproc_iso; /* 0x2d8c */ + u32 reserved90[28]; + u32 pikachu_event; /* 0x2e00 */ + u32 pikachu_status; + u32 reserved91[126]; + u32 cpu0_drcc_ao_config; /* 0x3000 */ + u32 reserved92[3]; + u32 cpu0_sesv6_ao_reg0; /* 0x3010 */ + u32 cpu0_sesv6_ao_reg1; + u32 cpu0_sesv6_ao_reg2; + u32 cpu0_sesv6_ao_reg3; + u32 cpu0_sesv6_ao_reg4; + u32 reserved93[7]; + u32 cpu0_dfs_cfg; /* 0x3040 */ + u32 reserved94[3]; + u32 cpu0_turbo_cfg; /* 0x3050 */ + u32 reserved95[105]; + u32 cpu0_resereved_reg; /* 0x31f8 */ + u32 cpu0_resereved_reg_rd; + u32 cpu1_drcc_ao_config; + u32 reserved96[3]; + u32 cpu1_sesv6_ao_reg0; /* 0x3210 */ + u32 cpu1_sesv6_ao_reg1; + u32 cpu1_sesv6_ao_reg2; + u32 cpu1_sesv6_ao_reg3; + u32 cpu1_sesv6_ao_reg4; + u32 reserved97[7]; + u32 cpu1_dfs_cfg; /* 0x3240 */ + u32 reserved98[3]; + u32 cpu1_turbo_cfg; /* 0x3250 */ + u32 reserved99[105]; + u32 cpu1_resereved_reg; /* 0x33f8 */ + u32 cpu1_resereved_reg_rd; + u32 cpu2_drcc_ao_config; + u32 reserved100[3]; + u32 cpu2_sesv6_ao_reg0; /* 0x3410 */ + u32 cpu2_sesv6_ao_reg1; + u32 cpu2_sesv6_ao_reg2; + u32 cpu2_sesv6_ao_reg3; + u32 cpu2_sesv6_ao_reg4; + u32 reserved101[7]; + u32 cpu2_dfs_cfg; /* 0x3440 */ + u32 reserved102[3]; + u32 cpu2_turbo_cfg; /* 0x3450 */ + u32 reserved103[105]; + u32 cpu2_resereved_reg; /* 0x35f8 */ + u32 cpu2_resereved_reg_rd; + u32 cpu3_drcc_ao_config; + u32 reserved104[3]; + u32 cpu3_sesv6_ao_reg0; /* 0x3610 */ + u32 cpu3_sesv6_ao_reg1; + u32 cpu3_sesv6_ao_reg2; + u32 cpu3_sesv6_ao_reg3; + u32 cpu3_sesv6_ao_reg4; + u32 reserved105[7]; + u32 cpu3_dfs_cfg; /* 0x3640 */ + u32 reserved106[3]; + u32 cpu3_turbo_cfg; /* 0x3650 */ + u32 reserved107[105]; + u32 cpu3_resereved_reg; /* 0x37f8 */ + u32 cpu3_resereved_reg_rd; + u32 cpu4_drcc_ao_config; + u32 reserved108[3]; + u32 cpu4_sesv6_ao_reg0; /* 0x3810 */ + u32 cpu4_sesv6_ao_reg1; + u32 cpu4_sesv6_ao_reg2; + u32 cpu4_sesv6_ao_reg3; + u32 cpu4_sesv6_ao_reg4; + u32 reserved109[3]; + u32 cpu4_didt_reg; /* 0x3830 */ + u32 cpu4_mem_lre_reg; + u32 reserved110[2]; + u32 cpu4_dfs_cfg; /* 0x3840 */ + u32 reserved111[3]; + u32 cpu4_turbo_cfg; /* 0x3850 */ + u32 reserved112[105]; + u32 cpu4_resereved_reg; /* 0x39f8 */ + u32 cpu4_resereved_reg_rd; + u32 cpu5_drcc_ao_config; + u32 reserved113[3]; + u32 cpu5_sesv6_ao_reg0; /* 0x3a10 */ + u32 cpu5_sesv6_ao_reg1; + u32 cpu5_sesv6_ao_reg2; + u32 cpu5_sesv6_ao_reg3; + u32 cpu5_sesv6_ao_reg4; + u32 reserved114[3]; + u32 cpu5_didt_reg; /* 0x3a30 */ + u32 cpu5_mem_lre_reg; + u32 reserved115[2]; + u32 cpu5_dfs_cfg; /* 0x3a40 */ + u32 reserved116[3]; + u32 cpu5_turbo_cfg; /* 0x3a50 */ + u32 reserved117[105]; + u32 cpu5_resereved_reg; /* 0x3bf8 */ + u32 cpu5_resereved_reg_rd; + u32 cpu6_drcc_ao_config; + u32 reserved118[3]; + u32 cpu6_sesv6_ao_reg0; /* 0x3c10 */ + u32 cpu6_sesv6_ao_reg1; + u32 cpu6_sesv6_ao_reg2; + u32 cpu6_sesv6_ao_reg3; + u32 cpu6_sesv6_ao_reg4; + u32 reserved119[3]; + u32 cpu6_didt_reg; /* 0x3c30 */ + u32 cpu6_mem_lre_reg; + u32 reserved120[2]; + u32 cpu6_dfs_cfg; /* 0x3c40 */ + u32 reserved121[3]; + u32 cpu6_turbo_cfg; /* 0x3c50 */ + u32 reserved122[105]; + u32 cpu6_resereved_reg; /* 0x3df8 */ + u32 cpu6_resereved_reg_rd; + u32 cpu7_drcc_ao_config; + u32 reserved123[3]; + u32 cpu7_sesv6_ao_reg0; /* 0x3e10 */ + u32 cpu7_sesv6_ao_reg1; + u32 cpu7_sesv6_ao_reg2; + u32 cpu7_sesv6_ao_reg3; + u32 cpu7_sesv6_ao_reg4; + u32 reserved124[3]; + u32 cpu7_didt_reg; /* 0x3e30 */ + u32 cpu7_mem_lre_reg; + u32 reserved125[2]; + u32 cpu7_dfs_cfg; /* 0x3e40 */ + u32 reserved126[3]; + u32 cpu7_turbo_cfg; /* 0x3e50 */ + u32 reserved127[105]; + u32 cpu7_resereved_reg; /* 0x3ff8 */ + u32 cpu7_resereved_reg_rd; + u32 reserved128[512]; + u32 mp0_mbist_cfg; /* 0x4800 */ + u32 reserved129[15]; + u32 mp0_l3_data_ram_delsel; /* 0x4840 */ + u32 mp0_l3_tag_ram_delsel; + u32 mp0_l3_victim_ram_delsel; + u32 mp0_l3_scu_sf_ram_delsel; + u32 reserved130[12]; + u32 mp0_dcm_cfg0; /* 0x4880 */ + u32 mp0_dcm_cfg1; + u32 mp0_dcm_cfg2; + u32 mp0_dcm_cfg3; + u32 mp0_dcm_cfg4; + u32 mp0_dcm_cfg5; + u32 mp0_dcm_cfg6; + u32 mp0_dcm_cfg7; + u32 mp0_dcm_cfg8; + u32 reserved131[7]; + u32 mp0_l3_cache_parity1; /* 0x48c0 */ + u32 mp0_l3_cache_parity2; + u32 mp0_l3_cache_parity3; + u32 reserved132[1]; + u32 mp0_cluster_cfg0; /* 0x48d0 */ + u32 reserved133[3]; + u32 mp0_cluster_cfg4; /* 0x48e0 */ + u32 mp0_cluster_cfg5; + u32 mp0_cluster_cfg6; + u32 mp0_cluster_cfg7; + u32 reserved134[4]; + u32 mp0_cluster_cfg8; /* 0x4900 */ + u32 mp0_cluster_cfg9; + u32 mp0_cluster_cfg10; + u32 mp0_cluster_cfg11; + u32 mp0_cluster_cfg12; + u32 mp0_cluster_cfg13; + u32 mp0_cluster_cfg14; + u32 mp0_cluster_cfg15; + u32 mp0_cluster_cfg16; + u32 mp0_cluster_cfg17; + u32 mp0_cluster_cfg18; + u32 mp0_cluster_cfg19; + u32 mp0_cluster_cfg20; + u32 mp0_cluster_cfg21; + u32 mp0_cluster_cfg22; + u32 mp0_cluster_cfg23; + u32 mp0_mem_dreq_cfg; + u32 mp0_victim_rd_mask; + u32 reserved135[174]; + u32 cpu_type0_spmc0_cfg; /* 0x4c00 */ + u32 reserved136[7]; + u32 cpu_type0_ram_delsel0_cfg; /* 0x4c20 */ + u32 cpu_type0_ram_delsel1_cfg; + u32 cpu_type0_ram_delsel2_cfg; + u32 reserved137[53]; + u32 cpu_type1_spmc0_cfg; /* 0x4d00 */ + u32 reserved138[3]; + u32 cpu_type1_mpmmen; /* 0x4d10 */ + u32 reserved139[3]; + u32 cpu_type1_ram_delsel0_cfg; /* 0x4d20 */ + u32 cpu_type1_ram_delsel1_cfg; + u32 cpu_type1_ram_delsel2_cfg; + u32 reserved140[5]; + u32 cpu_type1_drss_cfg0; /* 0x4d40 */ + u32 cpu_type1_drss_cfg1; + u32 reserved141[302]; + u32 mcusys_pwr_con; /* 0x5200 */ + u32 mp0_cputop_pwr_con; + u32 mp0_cpu0_pwr_con; + u32 mp0_cpu1_pwr_con; + u32 mp0_cpu2_pwr_con; + u32 mp0_cpu3_pwr_con; + u32 mp0_cpu4_pwr_con; + u32 mp0_cpu5_pwr_con; + u32 mp0_cpu6_pwr_con; + u32 mp0_cpu7_pwr_con; + u32 reserved142[246]; + u32 sec_pol_ctl_en0; /* 0x5600 */ + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 reserved143[7]; + u32 int_pol_ctl0; /* 0x5668 */ + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 reserved144[7]; + u32 int_msk_ctl0; /* 0x56d0 */ + u32 int_msk_ctl1; + u32 int_msk_ctl2; + u32 int_msk_ctl3; + u32 int_msk_ctl4; + u32 int_msk_ctl5; + u32 int_msk_ctl6; + u32 int_msk_ctl7; + u32 int_msk_ctl8; + u32 int_msk_ctl9; + u32 int_msk_ctl10; + u32 int_msk_ctl11; + u32 int_msk_ctl12; + u32 int_msk_ctl13; + u32 int_msk_ctl14; + u32 int_msk_ctl15; + u32 int_msk_ctl16; + u32 int_msk_ctl17; + u32 int_msk_ctl18; + u32 reserved145[10]; + u32 int_msk_ctl_all; /* 0x5744 */ + u32 int_cfg_indirect_access; + u32 int_cfg_direct_access_en; + u32 reserved146[572]; + u32 dfd_internal_ctl; /* 0x6040 */ + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_finish_wait_time; + u32 dfd_internal_chain_group; + u32 dfd_internal_chain_inv_info_ll; + u32 dfd_internal_chain_inv_info_lh; + u32 dfd_internal_chain_inv_info_hl; + u32 dfd_internal_chain_inv_info_hh; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsi; + u32 dfd_internal_mcsi_sel_status; + u32 dfd_v30_ctl; + u32 dfd_v30_base_addr; + u32 dfd_power_ctl; + u32 dfd_reset_on; + u32 dfd_test_si_0; + u32 dfd_test_si_1; + u32 dfd_status_clean; + u32 dfd_status_return; + u32 dfd_v35_enable; + u32 dfd_v35_tap_number; + u32 dfd_v35_tap_en; + u32 dfd_v35_ctl; + u32 dfd_v35_tap_seq0; + u32 dfd_v35_tap_seq1; + u32 dfd_v35_seq0_0; + u32 dfd_v35_seq0_1; + u32 dfd_v35_seq1_0; + u32 dfd_v35_seq1_1; + u32 dfd_v35_seq2_0; + u32 dfd_v35_seq2_1; + u32 reserved147[6]; + u32 dfd_soc_clock_stop_mask; /* 0x60f0 */ + u32 reserved148[2]; + u32 dfd_hw_trigger_mask; /* 0x60fc */ + u32 dfd_v50_enable; + u32 dfd_v50_self_trigger_iteration; + u32 dfd_v50_start_trigger; + u32 dfd_v50_cpuck_halt; + u32 dfd_v50_26m_resume; + u32 dfd_v50_26m_halt_release; + u32 dfd_v50_system_halt_time; + u32 dfd_v50_group_0_1_diff; + u32 dfd_v50_group_0_2_diff; + u32 dfd_v50_group_0_3_diff; + u32 dfd_v50_group_0_4_diff; + u32 dfd_v50_group_0_5_diff; + u32 dfd_v50_group_0_6_diff; + u32 dfd_v50_group_0_7_diff; + u32 dfd_v50_group_0_8_diff; + u32 dfd_v50_group_0_9_diff; + u32 dfd_v50_group_0_10_diff; + u32 dfd_v50_group_0_11_diff; + u32 dfd_v50_group_0_12_diff; + u32 dfd_v50_group_0_13_diff; + u32 dfd_v50_group_0_14_diff; + u32 dfd_v50_group_0_15_diff; + u32 dfd_v50_group_0_16_diff; + u32 dfd_v50_group_0_17_diff; + u32 dfd_v50_group_0_18_diff; + u32 dfd_v50_group_0_19_diff; + u32 dfd_v50_group_0_20_diff; + u32 dfd_v50_group_0_21_diff; + u32 dfd_v50_group_0_22_diff; + u32 dfd_v50_group_0_23_diff; + u32 dfd_v50_group_0_24_diff; + u32 dfd_v50_group_0_25_diff; + u32 dfd_v50_group_0_26_diff; + u32 dfd_v50_group_0_27_diff; + u32 dfd_v50_group_0_28_diff; + u32 dfd_v50_group_0_29_diff; + u32 dfd_v50_group_0_30_diff; + u32 dfd_v50_group_0_31_diff; + u32 dfd_v50_chain_group_3_0_info; + u32 dfd_v50_chain_group_7_4_info; + u32 dfd_v50_chain_group_11_8_info; + u32 dfd_v50_chain_group_15_12_info; + u32 dfd_v50_chain_group_19_16_info; + u32 dfd_v50_chain_group_23_20_info; + u32 dfd_v50_chain_group_27_24_info; + u32 dfd_v50_chain_group_31_28_info; + u32 dfd_v50_chain_group_35_32_info; + u32 dfd_v50_chain_group_39_36_info; + u32 dfd_v50_chain_group_43_40_info; + u32 dfd_v50_chain_group_47_44_info; + u32 dfd_v50_chain_group_51_48_info; + u32 dfd_v50_chain_group_55_52_info; + u32 dfd_v50_chain_group_59_56_info; + u32 dfd_v50_chain_group_63_60_info; + u32 dfd_v50_chain_group_67_64_info; + u32 dfd_v50_chain_group_71_68_info; + u32 dfd_v50_chain_group_75_72_info; + u32 dfd_v50_chain_group_79_76_info; + u32 dfd_v50_chain_group_83_80_info; + u32 dfd_v50_chain_group_87_84_info; + u32 dfd_v50_chain_group_91_88_info; + u32 dfd_v50_chain_group_95_92_info; + u32 dfd_v50_chain_group_99_96_info; + u32 dfd_v50_chain_group_103_100_info; + u32 dfd_v50_chain_group_107_104_info; + u32 dfd_v50_chain_group_111_108_info; + u32 dfd_v50_chain_group_115_112_info; + u32 dfd_v50_chain_group_119_116_info; + u32 dfd_v50_chain_group_123_120_info; + u32 dfd_v50_chain_group_127_124_info; + u32 dfd_test_si_2; + u32 dfd_test_si_3; + u32 dfd_test_so; + u32 dfd_bus_halt_time; + u32 dfd_read_addr; + u32 dfd_v50_clk_stop_time; + u32 dfd_v50_group_0_32_diff; + u32 dfd_v50_group_0_33_diff; + u32 dfd_v50_group_0_34_diff; + u32 dfd_v50_group_0_35_diff; + u32 dfd_v50_group_0_36_diff; + u32 dfd_v50_group_0_37_diff; + u32 dfd_v50_group_0_38_diff; + u32 dfd_v50_group_0_39_diff; + u32 dfd_v50_group_0_40_diff; + u32 dfd_v50_group_0_41_diff; + u32 dfd_v50_group_0_42_diff; + u32 dfd_v50_group_0_43_diff; + u32 dfd_v50_group_0_44_diff; + u32 dfd_v50_group_0_45_diff; + u32 dfd_v50_group_0_46_diff; + u32 dfd_v50_group_0_47_diff; + u32 dfd_v50_group_0_48_diff; + u32 dfd_v50_group_0_49_diff; + u32 dfd_v50_group_0_50_diff; + u32 dfd_v50_group_0_51_diff; + u32 dfd_v50_group_0_52_diff; + u32 dfd_v50_group_0_53_diff; + u32 dfd_v50_group_0_54_diff; + u32 dfd_v50_group_0_55_diff; + u32 dfd_v50_group_0_56_diff; + u32 dfd_v50_group_0_57_diff; + u32 dfd_v50_group_0_58_diff; + u32 dfd_v50_group_0_59_diff; + u32 dfd_v50_group_0_60_diff; + u32 dfd_v50_group_0_61_diff; + u32 dfd_v50_group_0_62_diff; + u32 dfd_v50_group_0_63_diff; + u32 reserved149[20]; + u32 dfd_v50_spare; /* 0x6300 */ + u32 reserved150[1843]; + u32 mcusys_reserved_reg4; /* 0x7fd0 */ + u32 mcusys_reserved_reg4_rd; + u32 reserved151[2]; + u32 mcusys_reserved_reg0; /* 0x7fe0 */ + u32 mcusys_reserved_reg1; + u32 mcusys_reserved_reg2; + u32 mcusys_reserved_reg3; + u32 mcusys_reserved_reg0_rd; + u32 mcusys_reserved_reg1_rd; + u32 mcusys_reserved_reg2_rd; + u32 mcusys_reserved_reg3_rd; +}; + +check_member(mt8192_mcucfg_regs, mbista_mcsi_sf1_con, 0x0008); +check_member(mt8192_mcucfg_regs, mbist_trigger_mux_ctl, 0x0030); +check_member(mt8192_mcucfg_regs, dfd_ctrl, 0x0040); +check_member(mt8192_mcucfg_regs, mp_top_dbg_mon_sel, 0x0060); +check_member(mt8192_mcucfg_regs, mp0_ptp_sensor_sel, 0x00e0); +check_member(mt8192_mcucfg_regs, armpll_jit_clk_out_sel, 0x00f8); +check_member(mt8192_mcucfg_regs, cci_tra_cfg5, 0x0114); +check_member(mt8192_mcucfg_regs, cci_m0_tra, 0x0200); +check_member(mt8192_mcucfg_regs, cci_s1_tra, 0x0220); +check_member(mt8192_mcucfg_regs, cci_m0_tra_latch, 0x0240); +check_member(mt8192_mcucfg_regs, cci_s1_tra_latch, 0x0260); +check_member(mt8192_mcucfg_regs, cci_m0_if, 0x02c0); +check_member(mt8192_mcucfg_regs, cci_s1_if, 0x02e0); +check_member(mt8192_mcucfg_regs, cci_m0_if_latch, 0x0320); +check_member(mt8192_mcucfg_regs, cci_s1_if_latch, 0x0340); +check_member(mt8192_mcucfg_regs, l3c_share_status0, 0x0400); +check_member(mt8192_mcucfg_regs, mp0_cpu0_nonwfx_ctrl, 0x0500); +check_member(mt8192_mcucfg_regs, mp0_ses_apb_trig, 0x0600); +check_member(mt8192_mcucfg_regs, wfx_ret_met_dbc_sel, 0x0610); +check_member(mt8192_mcucfg_regs, adb_bist_cfg1, 0x0620); +check_member(mt8192_mcucfg_regs, axi2acp_cfg_ctrl, 0x0700); +check_member(mt8192_mcucfg_regs, axi2acp_ar_def_set, 0x0710); +check_member(mt8192_mcucfg_regs, mst_ccim0_inject_fault, 0x0800); +check_member(mt8192_mcucfg_regs, slv_1to2_inject_fault, 0x0860); +check_member(mt8192_mcucfg_regs, slv_1to2_log_wd0, 0x0890); +check_member(mt8192_mcucfg_regs, ildo_vin_big0, 0x0a00); +check_member(mt8192_mcucfg_regs, ildo_vin_big1, 0x0a30); +check_member(mt8192_mcucfg_regs, ildo_vin_big2, 0x0a60); +check_member(mt8192_mcucfg_regs, ildo_vin_big3, 0x0a90); +check_member(mt8192_mcucfg_regs, l3c_share_cfg0, 0x2210); +check_member(mt8192_mcucfg_regs, mcusys_core_status, 0x2230); +check_member(mt8192_mcucfg_regs, mcusys_base, 0x2260); +check_member(mt8192_mcucfg_regs, bus_plldiv_cfg, 0x22e0); +check_member(mt8192_mcucfg_regs, plldiv_ctl0, 0x22f0); +check_member(mt8192_mcucfg_regs, mcsi_ram_delsel0, 0x2300); +check_member(mt8192_mcucfg_regs, etb_cfg0, 0x2380); +check_member(mt8192_mcucfg_regs, bus_parity_gen_en, 0x2390); +check_member(mt8192_mcucfg_regs, dsu2biu_addr_remap_0_cfg0, 0x23b0); +check_member(mt8192_mcucfg_regs, cci_rgu, 0x2400); +check_member(mt8192_mcucfg_regs, mcsi_cfg0, 0x2410); +check_member(mt8192_mcucfg_regs, mcsic_dcm0, 0x2440); +check_member(mt8192_mcucfg_regs, apmcu2emi_early_cke_ctl01, 0x2490); +check_member(mt8192_mcucfg_regs, mp_adb_dcm_cfg0, 0x2500); +check_member(mt8192_mcucfg_regs, etb_ck_ctl, 0x2540); +check_member(mt8192_mcucfg_regs, dcc_cpu_con0, 0x2580); +check_member(mt8192_mcucfg_regs, dcc_bus_con0, 0x25a0); +check_member(mt8192_mcucfg_regs, mcusys_dcm_cfg0, 0x25c0); +check_member(mt8192_mcucfg_regs, fcm_spmc_sw_cfg1, 0x2700); +check_member(mt8192_mcucfg_regs, mcusys_spmc_sw_cfg, 0x2740); +check_member(mt8192_mcucfg_regs, cpc_pllbuck_req_ctrl, 0x2800); +check_member(mt8192_mcucfg_regs, cpc_spmc_pwr_status, 0x2840); +check_member(mt8192_mcucfg_regs, emi_wfifo, 0x2900); +check_member(mt8192_mcucfg_regs, sclk_cfg_slow_down_ck, 0x2920); +check_member(mt8192_mcucfg_regs, acpwakeup, 0x2930); +check_member(mt8192_mcucfg_regs, mcusys_dbg_mon_sel, 0x2990); +check_member(mt8192_mcucfg_regs, gic_acao_ctl0, 0x2a80); +check_member(mt8192_mcucfg_regs, spmc_dbg_setting, 0x2b00); +check_member(mt8192_mcucfg_regs, trace_data_entry0_l, 0x2b20); +check_member(mt8192_mcucfg_regs, cpc_wdt_latch_info6, 0x2bb0); +check_member(mt8192_mcucfg_regs, sesv6_bg_ctrl, 0x2c40); +check_member(mt8192_mcucfg_regs, dsu_sesv6_ao_reg0, 0x2c50); +check_member(mt8192_mcucfg_regs, ildo_dout_sel, 0x2d00); +check_member(mt8192_mcucfg_regs, dreq20_little_en, 0x2d80); +check_member(mt8192_mcucfg_regs, dreq20_big_vproc_iso, 0x2d8c); +check_member(mt8192_mcucfg_regs, pikachu_event, 0x2e00); +check_member(mt8192_mcucfg_regs, cpu0_drcc_ao_config, 0x3000); +check_member(mt8192_mcucfg_regs, cpu0_sesv6_ao_reg0, 0x3010); +check_member(mt8192_mcucfg_regs, cpu0_dfs_cfg, 0x3040); +check_member(mt8192_mcucfg_regs, cpu0_turbo_cfg, 0x3050); +check_member(mt8192_mcucfg_regs, cpu0_resereved_reg, 0x31f8); +check_member(mt8192_mcucfg_regs, cpu1_sesv6_ao_reg0, 0x3210); +check_member(mt8192_mcucfg_regs, cpu1_dfs_cfg, 0x3240); +check_member(mt8192_mcucfg_regs, cpu1_turbo_cfg, 0x3250); +check_member(mt8192_mcucfg_regs, cpu1_resereved_reg, 0x33f8); +check_member(mt8192_mcucfg_regs, cpu2_sesv6_ao_reg0, 0x3410); +check_member(mt8192_mcucfg_regs, cpu2_dfs_cfg, 0x3440); +check_member(mt8192_mcucfg_regs, cpu2_turbo_cfg, 0x3450); +check_member(mt8192_mcucfg_regs, cpu2_resereved_reg, 0x35f8); +check_member(mt8192_mcucfg_regs, cpu3_sesv6_ao_reg0, 0x3610); +check_member(mt8192_mcucfg_regs, cpu3_dfs_cfg, 0x3640); +check_member(mt8192_mcucfg_regs, cpu3_turbo_cfg, 0x3650); +check_member(mt8192_mcucfg_regs, cpu3_resereved_reg, 0x37f8); +check_member(mt8192_mcucfg_regs, cpu4_sesv6_ao_reg0, 0x3810); +check_member(mt8192_mcucfg_regs, cpu4_didt_reg, 0x3830); +check_member(mt8192_mcucfg_regs, cpu4_dfs_cfg, 0x3840); +check_member(mt8192_mcucfg_regs, cpu4_turbo_cfg, 0x3850); +check_member(mt8192_mcucfg_regs, cpu4_resereved_reg, 0x39f8); +check_member(mt8192_mcucfg_regs, cpu5_sesv6_ao_reg0, 0x3a10); +check_member(mt8192_mcucfg_regs, cpu5_didt_reg, 0x3a30); +check_member(mt8192_mcucfg_regs, cpu5_dfs_cfg, 0x3a40); +check_member(mt8192_mcucfg_regs, cpu5_turbo_cfg, 0x3a50); +check_member(mt8192_mcucfg_regs, cpu5_resereved_reg, 0x3bf8); +check_member(mt8192_mcucfg_regs, cpu6_sesv6_ao_reg0, 0x3c10); +check_member(mt8192_mcucfg_regs, cpu6_didt_reg, 0x3c30); +check_member(mt8192_mcucfg_regs, cpu6_dfs_cfg, 0x3c40); +check_member(mt8192_mcucfg_regs, cpu6_turbo_cfg, 0x3c50); +check_member(mt8192_mcucfg_regs, cpu6_resereved_reg, 0x3df8); +check_member(mt8192_mcucfg_regs, cpu7_sesv6_ao_reg0, 0x3e10); +check_member(mt8192_mcucfg_regs, cpu7_didt_reg, 0x3e30); +check_member(mt8192_mcucfg_regs, cpu7_dfs_cfg, 0x3e40); +check_member(mt8192_mcucfg_regs, cpu7_turbo_cfg, 0x3e50); +check_member(mt8192_mcucfg_regs, cpu7_resereved_reg, 0x3ff8); +check_member(mt8192_mcucfg_regs, mp0_mbist_cfg, 0x4800); +check_member(mt8192_mcucfg_regs, mp0_l3_data_ram_delsel, 0x4840); +check_member(mt8192_mcucfg_regs, mp0_dcm_cfg0, 0x4880); +check_member(mt8192_mcucfg_regs, mp0_l3_cache_parity1, 0x48c0); +check_member(mt8192_mcucfg_regs, mp0_cluster_cfg4, 0x48e0); +check_member(mt8192_mcucfg_regs, mp0_cluster_cfg8, 0x4900); +check_member(mt8192_mcucfg_regs, cpu_type0_spmc0_cfg, 0x4c00); +check_member(mt8192_mcucfg_regs, cpu_type0_ram_delsel0_cfg, 0x4c20); +check_member(mt8192_mcucfg_regs, cpu_type1_spmc0_cfg, 0x4d00); +check_member(mt8192_mcucfg_regs, cpu_type1_mpmmen, 0x4d10); +check_member(mt8192_mcucfg_regs, cpu_type1_ram_delsel0_cfg, 0x4d20); +check_member(mt8192_mcucfg_regs, cpu_type1_drss_cfg0, 0x4d40); +check_member(mt8192_mcucfg_regs, mcusys_pwr_con, 0x5200); +check_member(mt8192_mcucfg_regs, sec_pol_ctl_en0, 0x5600); +check_member(mt8192_mcucfg_regs, int_pol_ctl0, 0x5668); +check_member(mt8192_mcucfg_regs, int_msk_ctl0, 0x56d0); +check_member(mt8192_mcucfg_regs, int_msk_ctl_all, 0x5744); +check_member(mt8192_mcucfg_regs, dfd_internal_ctl, 0x6040); +check_member(mt8192_mcucfg_regs, dfd_soc_clock_stop_mask, 0x60f0); +check_member(mt8192_mcucfg_regs, dfd_hw_trigger_mask, 0x60fc); +check_member(mt8192_mcucfg_regs, dfd_v50_spare, 0x6300); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg4, 0x7fd0); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); + +static struct mt8192_mcucfg_regs *const mt8192_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8192_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h new file mode 100644 index 0000000000..442aa30877 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PLL_H +#define SOC_MEDIATEK_MT8192_PLL_H + +#include <device/mmio.h> +#include <types.h> +#include <soc/pll_common.h> + +struct mtk_topckgen_regs { + u32 clk_mode; + u32 clk_cfg_update; + u32 clk_cfg_update1; + u32 clk_cfg_update2; + u32 clk_cfg_0; + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 reserved1[1]; + u32 clk_cfg_1; /* 0x0020 */ + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 reserved2[1]; + u32 clk_cfg_2; /* 0x0030 */ + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 reserved3[1]; + u32 clk_cfg_3; /* 0x0040 */ + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 reserved4[1]; + u32 clk_cfg_4; /* 0x0050 */ + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 reserved5[1]; + u32 clk_cfg_5; /* 0x0060 */ + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 reserved6[1]; + u32 clk_cfg_6; /* 0x0070 */ + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 reserved7[1]; + u32 clk_cfg_7; /* 0x0080 */ + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 reserved8[1]; + u32 clk_cfg_8; /* 0x0090 */ + u32 clk_cfg_8_set; + u32 clk_cfg_8_clr; + u32 reserved9[1]; + u32 clk_cfg_9; /* 0x00a0 */ + u32 clk_cfg_9_set; + u32 clk_cfg_9_clr; + u32 reserved10[1]; + u32 clk_cfg_10; /* 0x00b0 */ + u32 clk_cfg_10_set; + u32 clk_cfg_10_clr; + u32 reserved11[1]; + u32 clk_cfg_11; /* 0x00c0 */ + u32 clk_cfg_11_set; + u32 clk_cfg_11_clr; + u32 reserved12[1]; + u32 clk_cfg_12; /* 0x00d0 */ + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 reserved13[1]; + u32 clk_cfg_13; /* 0x00e0 */ + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 reserved14[1]; + u32 clk_cfg_14; /* 0x00f0 */ + u32 clk_cfg_14_set; + u32 clk_cfg_14_clr; + u32 reserved15[1]; + u32 clk_cfg_15; /* 0x0100 */ + u32 clk_cfg_15_set; + u32 clk_cfg_15_clr; + u32 reserved16[1]; + u32 clk_cfg_16; /* 0x0110 */ + u32 clk_cfg_16_set; + u32 clk_cfg_16_clr; + u32 reserved17[9]; + u32 clk_misc_cfg_0; /* 0x0140 */ + u32 reserved18[3]; + u32 clk_misc_cfg_1; /* 0x0150 */ + u32 reserved19[10]; + u32 clk_dbg_cfg; /* 0x017c */ + u32 reserved20[32]; + u32 clk_scp_cfg_0; /* 0x0200 */ + u32 reserved21[3]; + u32 clk_scp_cfg_1; /* 0x0210 */ + u32 reserved22[3]; + u32 clk26cali_0; /* 0x0220 */ + u32 clk26cali_1; + u32 reserved23[2]; + u32 cksta_reg; /* 0x0230 */ + u32 cksta_reg1; + u32 cksta_reg2; + u32 reserved24[49]; + u32 clkmon_clk_sel_reg; /* 0x0300 */ + u32 clkmon_k1_reg; + u32 reserved25[6]; + u32 clk_auddiv_0; /* 0x0320 */ + u32 clk_auddiv_1; + u32 clk_auddiv_2; + u32 aud_top_cfg; + u32 aud_top_mon; + u32 clk_auddiv_3; + u32 clk_auddiv_4; + u32 reserved26[113]; + u32 clk_extck_reg; /* 0x0500 */ +}; + +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140); +check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0150); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017c); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200); +check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x0210); +check_member(mtk_topckgen_regs, clk26cali_0, 0x0220); +check_member(mtk_topckgen_regs, cksta_reg, 0x0230); +check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x0300); +check_member(mtk_topckgen_regs, clk_auddiv_0, 0x0320); +check_member(mtk_topckgen_regs, clk_extck_reg, 0x0500); + +struct mtk_apmixed_regs { + u32 ap_pll_con0; + u32 ap_pll_con1; + u32 ap_pll_con2; + u32 ap_pll_con3; + u32 ap_pll_con4; + u32 ap_pll_con5; + u32 clksq_stb_con0; + u32 pll_pwr_con0; + u32 pll_pwr_con1; + u32 pll_iso_con0; + u32 pll_iso_con1; + u32 pll_stb_con0; + u32 div_stb_con0; + u32 pll_chg_con0; + u32 pll_test_con0; + u32 pll_test_con1; + u32 apll1_tuner_con0; + u32 apll2_tuner_con0; + u32 reserved0[2]; + u32 pllon_con0; + u32 pllon_con1; + u32 pllon_con2; + u32 pllon_con3; + u32 reserved1[104]; + u32 ap_pllgp1_con0; /* 0x0200 */ + u32 ap_pllgp1_con1; + u32 armpll_ll_con0; + u32 armpll_ll_con1; + u32 armpll_ll_con2; + u32 armpll_ll_con3; + u32 armpll_bl0_con0; + u32 armpll_bl_con1; + u32 armpll_bl_con2; + u32 armpll_bl_con3; + u32 armpll_bl1_con0; + u32 armpll_bl1_con1; + u32 armpll_bl1_con2; + u32 armpll_bl1_con3; + u32 armpll_bl2_con0; + u32 armpll_bl2_con1; + u32 armpll_bl2_con2; + u32 armpll_bl2_con3; + u32 armpll_bl3_con0; + u32 armpll_bl3_con1; + u32 armpll_bl3_con2; + u32 armpll_bl3_con3; + u32 ccipll_con0; + u32 ccipll_con1; + u32 ccipll_con2; + u32 ccipll_con3; + u32 mfgpll_con0; + u32 mfgpll_con1; + u32 mfgpll_con2; + u32 mfgpll_con3; + u32 ap_pllgp1_con2; + u32 reserved2[33]; + u32 ap_pllgp2_con0; /* 0x0300 */ + u32 ap_pllgp2_con1; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_con3; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_con4; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_con4; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_con3; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_con3; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_con3; + u32 adsppll_con0; + u32 adsppll_con1; + u32 adsppll_con2; + u32 adsppll_con3; + u32 tvdpll_con0; + u32 tvdpll_con1; + u32 tvdpll_con2; + u32 tvdpll_con3; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_con3; + u32 apupll_con0; + u32 apupll_con1; + u32 apupll_con2; + u32 apupll_con3; + u32 ap_pllgp3_con0; + u32 npupll_con0; + u32 npupll_con1; + u32 npupll_con2; + u32 npupll_con3; + u32 usbpll_con0; + u32 usbpll_con1; + u32 usbpll_con2; +}; + +check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200); +check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); +check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc); + +enum { + USBPLL_EN = 0x1 << 2, + + PLL_DIV_EN = 0xff << 24, +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, +}; + +enum { + PLL_PWR_ON_DELAY = 30, + PLL_ISO_DELAY = 1, + PLL_EN_DELAY = 20, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +/* PLL rate */ +enum { + ARMPLL_LL_HZ = 1075 * MHz, + ARMPLL_BL_HZ = 774 * MHz, + CCIPLL_HZ = 730 * MHz, + MAINPLL_HZ = 2184UL * MHz, + UNIVPLL_HZ = 2496UL * MHz, + USBPLL_HZ = 192UL * 13 * MHz, + MSDCPLL_HZ = 384 * MHz, + MMPLL_HZ = 2750UL * MHz, + ADSPPLL_HZ = 750 * MHz, + MFGPLL_HZ = 358 * MHz, + TVDPLL_HZ = 594 * MHz, + APLL1_HZ = 180633600, + APLL2_HZ = 196608 * KHz, +}; + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, + MAINPLL_D5_D4_HZ = MAINPLL_D5_HZ / 4, +}; + +/* top_mux rate */ +enum { + SPI_HZ = MAINPLL_D5_D4_HZ, + UART_HZ = CLK26M_HZ, +}; + +DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) +DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9) + +#endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c new file mode 100644 index 0000000000..40d92fdc63 --- /dev/null +++ b/src/soc/mediatek/mt8192/pll.c @@ -0,0 +1,436 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <delay.h> +#include <stddef.h> + +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/pll.h> + +enum mux_id { + TOP_AXI_SEL, + TOP_SPM_SEL, + TOP_SCP_SEL, + TOP_BUS_AXIMEM_SEL, + TOP_DISP_SEL, + TOP_MDP_SEL, + TOP_IMG1_SEL, + TOP_IMG2_SEL, + TOP_IPE_SEL, + TOP_DPE_SEL, + TOP_CAM_SEL, + TOP_CCU_SEL, + TOP_DSP_SEL, + TOP_DSP7_SEL, + TOP_MFG_REF_SEL, + TOP_MFG_PLL_SEL, + TOP_CAMTG_SEL, + TOP_CAMTG2_SEL, + TOP_CAMTG3_SEL, + TOP_CAMTG4_SEL, + TOP_CAMTG5_SEL, + TOP_CAMTG6_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_MSDC50_0_HCLK_SEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_MSDC30_2_SEL, + TOP_AUDIO_SEL, + TOP_AUD_INTBUS_SEL, + TOP_PWRAP_ULPOSC_SEL, + TOP_ATB_SEL, + TOP_PWRMCU_SEL, + TOP_DPI_SEL, + TOP_SCAM_SEL, + TOP_DISP_PWM_SEL, + TOP_USB_TOP_SEL, + TOP_SSUSB_XHCI_SEL, + TOP_I2C_SEL, + TOP_SENINF_SEL, + TOP_SENINF1_SEL, + TOP_SENINF2_SEL, + TOP_SENINF3_SEL, + TOP_TL_SEL, + TOP_DXCC_SEL, + TOP_AUD_ENGEN1_SEL, + TOP_AUD_ENGEN2_SEL, + TOP_AES_UFSFDE_SEL, + TOP_UFS_SEL, + TOP_AUD_1_SEL, + TOP_AUD_2_SEL, + TOP_ADSP_SEL, + TOP_DPMAIF_MAIN_SEL, + TOP_VENC_SEL, + TOP_VDEC_SEL, + TOP_CAMTM_SEL, + TOP_PWM_SEL, + TOP_AUDIO_H_SEL, + TOP_SPMI_MST_SEL, + TOP_DVFSRC_SEL, + TOP_AES_MSDCFDE_SEL, + TOP_MCUPM_SEL, + TOP_SFLASH_SEL, + TOP_NR_MUX +}; + +#define MUX(_id, _reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = NULL, \ + .upd_shift = 0, \ + } + +#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &mtk_topckgen->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0), + MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1), + MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2), + MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3), + /* CLK_CFG_1 */ + MUX_UPD(TOP_DISP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4), + MUX_UPD(TOP_MDP_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5), + MUX_UPD(TOP_IMG1_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6), + MUX_UPD(TOP_IMG2_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7), + /* CLK_CFG_2 */ + MUX_UPD(TOP_IPE_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8), + MUX_UPD(TOP_DPE_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9), + MUX_UPD(TOP_CAM_SEL, clk_cfg_2, 16, 4, clk_cfg_update, 10), + MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 24, 4, clk_cfg_update, 11), + /* CLK_CFG_3 */ + MUX_UPD(TOP_DSP_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12), + /* CLK_CFG_4 */ + MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16), + MUX_UPD(TOP_MFG_REF_SEL, clk_cfg_4, 16, 2, clk_cfg_update, 18), + MUX(TOP_MFG_PLL_SEL, clk_cfg_4, 18, 1), + MUX_UPD(TOP_CAMTG_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19), + /* CLK_CFG_5 */ + MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 0, 3, clk_cfg_update, 20), + MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21), + MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22), + MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23), + /* CLK_CFG_6 */ + MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24), + MUX_UPD(TOP_UART_SEL, clk_cfg_6, 8, 1, clk_cfg_update, 25), + MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26), + MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27), + /* CLK_CFG_7 */ + MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28), + MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 8, 3, clk_cfg_update, 29), + MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30), + MUX_UPD(TOP_AUDIO_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0), + /* CLK_CFG_8 */ + MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1), + MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2), + MUX_UPD(TOP_ATB_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3), + MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_8, 24, 3, clk_cfg_update1, 4), + /* CLK_CFG_9 */ + MUX_UPD(TOP_DPI_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5), + MUX_UPD(TOP_SCAM_SEL, clk_cfg_9, 8, 1, clk_cfg_update1, 6), + MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7), + MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8), + /* CLK_CFG_10 */ + MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, 0, 2, clk_cfg_update1, 9), + MUX_UPD(TOP_I2C_SEL, clk_cfg_10, 8, 2, clk_cfg_update1, 10), + MUX_UPD(TOP_SENINF_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 11), + MUX_UPD(TOP_SENINF1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 12), + /* CLK_CFG_11 */ + MUX_UPD(TOP_SENINF2_SEL, clk_cfg_11, 0, 3, clk_cfg_update1, 13), + MUX_UPD(TOP_SENINF3_SEL, clk_cfg_11, 8, 3, clk_cfg_update1, 14), + MUX_UPD(TOP_TL_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15), + MUX_UPD(TOP_DXCC_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 16), + /* CLK_CFG_12 */ + MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 17), + MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18), + MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19), + MUX_UPD(TOP_UFS_SEL, clk_cfg_12, 24, 3, clk_cfg_update1, 20), + /* CLK_CFG_13 */ + MUX_UPD(TOP_AUD_1_SEL, clk_cfg_13, 0, 1, clk_cfg_update1, 21), + MUX_UPD(TOP_AUD_2_SEL, clk_cfg_13, 8, 1, clk_cfg_update1, 22), + MUX_UPD(TOP_ADSP_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 23), + MUX_UPD(TOP_DPMAIF_MAIN_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 24), + /* CLK_CFG_14 */ + MUX_UPD(TOP_VENC_SEL, clk_cfg_14, 0, 4, clk_cfg_update1, 25), + MUX_UPD(TOP_VDEC_SEL, clk_cfg_14, 8, 4, clk_cfg_update1, 26), + MUX_UPD(TOP_CAMTM_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 27), + MUX_UPD(TOP_PWM_SEL, clk_cfg_14, 24, 1, clk_cfg_update1, 28), + /* CLK_CFG_15 */ + MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_15, 0, 2, clk_cfg_update1, 29), + MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 30), + MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_15, 16, 1, clk_cfg_update2, 0), + MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_15, 24, 3, clk_cfg_update2, 1), + /* CLK_CFG_16 */ + MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 0, 2, clk_cfg_update2, 2), + MUX_UPD(TOP_SFLASH_SEL, clk_cfg_16, 8, 2, clk_cfg_update2, 3), +}; + +struct mux_sel { + enum mux_id id; + u32 sel; +}; + +static const struct mux_sel mux_sels[] = { + /* CLK_CFG_0 */ + { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */ + { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ + { .id = TOP_SCP_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + /* CLK_CFG_1 */ + { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mainpll_d4 */ + { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: tvdpll_ck */ + { .id = TOP_IMG1_SEL, .sel = 1 }, /* 1: univpll_d4 */ + { .id = TOP_IMG2_SEL, .sel = 1 }, /* 1: univpll_d4 */ + /* CLK_CFG_2 */ + { .id = TOP_IPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ + { .id = TOP_DPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ + { .id = TOP_CAM_SEL, .sel = 3 }, /* 3: univpll_d4 */ + { .id = TOP_CCU_SEL, .sel = 8 }, /* 8: univpll_d5 */ + /* CLK_CFG_3 */ + { .id = TOP_DSP_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + /* CLK_CFG_4 */ + { .id = TOP_DSP7_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_MFG_REF_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + { .id = TOP_MFG_PLL_SEL, .sel = 1 }, /* 1: mfgpll */ + { .id = TOP_CAMTG_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + /* CLK_CFG_5 */ + { .id = TOP_CAMTG2_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG3_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG4_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG5_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + /* CLK_CFG_6 */ + { .id = TOP_CAMTG6_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_SPI_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + /* CLK_CFG_7 */ + { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ + { .id = TOP_MSDC30_1_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ + { .id = TOP_MSDC30_2_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ + { .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_8 */ + { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ + { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: osc_d10 */ + { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + /* CLK_CFG_9 */ + { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_d2 */ + { .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + { .id = TOP_DISP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + /* CLK_CFG_10 */ + { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */ + { .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */ + /* CLK_CFG_11 */ + { .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_TL_SEL, .sel = 1 }, /* 1: univpll_192m_d2 */ + { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + /* CLK_CFG_12 */ + { .id = TOP_AUD_ENGEN1_SEL, .sel = 2 }, /* 2: apll1_d4 */ + { .id = TOP_AUD_ENGEN2_SEL, .sel = 2 }, /* 2: apll2_d4 */ + { .id = TOP_AES_UFSFDE_SEL, .sel = 6 }, /* 6: univpll_d6 */ + { .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */ + /* CLK_CFG_13 */ + { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ + { .id = TOP_ADSP_SEL, .sel = 7 }, /* 7: adsppll_ck */ + { .id = TOP_DPMAIF_MAIN_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + /* CLK_CFG_14 */ + { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */ + { .id = TOP_VDEC_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */ + { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */ + { .id = TOP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_15 */ + { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */ + { .id = TOP_SPMI_MST_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */ + /* CLK_CFG_16 */ + { .id = TOP_MCUPM_SEL, .sel = 2 }, /* 2: mainpll_d6_d2 */ + { .id = TOP_SFLASH_SEL, .sel = 1 }, /* 1: mainpll_d7_d8 */ +}; + +enum pll_id { + APMIXED_ARMPLL_LL, + APMIXED_ARMPLL_BL, + APMIXED_CCIPLL, + APMIXED_MAINPLL, + APMIXED_UNIVPLL, + APMIXED_USBPLL, + APMIXED_MSDCPLL, + APMIXED_MMPLL, + APMIXED_ADSPPLL, + APMIXED_MFGPLL, + APMIXED_TVDPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_PLL_MAX +}; + +const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +static const struct pll plls[] = { + PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, + NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMPLL_BL, armpll_bl0_con0, armpll_bl_con3, + NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, + pll_div_rate), + PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, + NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, + 23, 22, mainpll_con1, 24, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, + 23, 22, univpll_con1, 24, univpll_con1, 0, + pll_div_rate), + PLL(APMIXED_USBPLL, usbpll_con0, usbpll_con2, + NO_RSTB_SHIFT, 22, usbpll_con0, 24, usbpll_con0, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, + NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, + 23, 22, mmpll_con1, 24, mmpll_con1, 0, + pll_div_rate), + PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, + NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, + pll_div_rate), + PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, + NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3, + NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_con4, + NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_con4, + NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, + pll_div_rate), +}; + +struct rate { + enum pll_id id; + u32 rate; +}; + +static const struct rate rates[] = { + { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, + { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, + { .id = APMIXED_USBPLL, .rate = USBPLL_HZ }, + { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, + { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, + { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, + { .id = APMIXED_APLL1, .rate = APLL1_HZ }, + { .id = APMIXED_APLL2, .rate = APLL2_HZ }, +}; + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + /* enable clock square1 low-pass filter */ + setbits32(&mtk_apmixed->ap_pll_con0, 0x2); + + /* reduce PLL current */ + SET32_BITFIELDS(&mtk_apmixed->ap_pllgp1_con1, PLLGP1_LVRREF, 1); + SET32_BITFIELDS(&mtk_apmixed->ap_pllgp2_con1, PLLGP2_LVRREF, 1); + + /* xPLL PWR ON */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(PLL_PWR_ON_DELAY); + + /* xPLL ISO Disable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + clrbits32(plls[i].pwr_reg, PLL_ISO); + + udelay(PLL_ISO_DELAY); + + /* xPLL Frequency Set */ + for (i = 0; i < ARRAY_SIZE(rates); i++) + pll_set_rate(&plls[rates[i].id], rates[i].rate); + + /* xPLL Frequency Enable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (i == APMIXED_USBPLL) + setbits32(plls[APMIXED_USBPLL].pwr_reg, USBPLL_EN); + else + setbits32(plls[i].reg, PLL_EN); + } + + /* wait for PLL stable */ + udelay(PLL_EN_DELAY); + + /* xPLL DIV Enable & RSTB */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (plls[i].rstb_shift != NO_RSTB_SHIFT) { + setbits32(plls[i].reg, PLL_DIV_EN); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); + } + } + + /* MCUCFG CLKMUX */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* enable infrasys DCM */ + setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + + /* initialize SPM request */ + setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); + clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); + + /* + * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! + */ + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* enable [14] dramc_pll104m_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); +} |