diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 20 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h | 26 |
3 files changed, 57 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a3ce48383d..cddfe4436f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -639,6 +639,21 @@ static void glk_fsp_silicon_init_params_cb( * Options to disable XHCI Link Compliance Mode. */ silconfig->DisableComplianceMode = cfg->DisableComplianceMode; + + /* + * Options to change USB3 ModPhy setting for Integrated Filter value. + */ + silconfig->ModPhyIfValue = cfg->ModPhyIfValue; + + /* + * Options to bump USB3 LDO voltage with 40mv. + */ + silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump; + + /* + * Options to adjust PMIC Vdd2 voltage. + */ + silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; #endif } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9c9dc58ac..6c2404a405 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -168,6 +168,26 @@ struct soc_intel_apollolake_config { * 0:FALSE(Default), 1:True. */ uint8_t DisableComplianceMode; + + /* Options to change USB3 ModPhy setting for the Integrated Filter (IF) + * value. Default is 0 to not changing default IF value (0x12). Set + * value with the range from 0x01 to 0xff to change IF value. + */ + uint8_t ModPhyIfValue; + + /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing + * LDO voltage. Set TRUE to increase LDO voltage with 40mV. + * 0:FALSE (default), 1:True. + */ + uint8_t ModPhyVoltageBump; + + /* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting + * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage + * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16) + * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: + * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). + */ + uint32_t PmicVdd2Voltage; }; typedef struct soc_intel_apollolake_config config_t; diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 18a43e2b8f..97a40b6558 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -1721,7 +1721,25 @@ typedef struct { **/ UINT32 PmicPmcIpcCtrl; -/** Offset 0x03AF +/** Offset 0x03AF - ModPhyIfValue + Upd To modify the Integrated Filter (IF) value as 0x12(Default) for WIN and 0x16 + for Chrome +**/ + UINT8 ModPhyIfValue; + +/** Offset 0x03B0 - ModPhyVoltageBump + ModPhyVoltageBump. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 ModPhyVoltageBump; + +/** Offset 0x03B1 - Vdd2 Voltage configuration + Upd for changing Vdd2 Voltage configuration : I2C_Slave_Address (31:23) + Register_Offset + (23:16) + OR Value (15:8) + AND Value (7:0) +**/ + UINT32 PmicVdd2Voltage; + +/** Offset 0x03B5 **/ UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; @@ -1792,9 +1810,9 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x03B0 +/** Offset 0x03B6 **/ - UINT8 UnusedUpdSpace7[16]; + UINT8 UnusedUpdSpace7[10]; /** Offset 0x03C0 **/ |