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-rw-r--r--src/soc/intel/broadwell/pcie.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 4e5bbfa015..10b623098b 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -558,9 +558,12 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg8(dev, 0xf5, 0x0f, 0);
- /* Set Extended Capability to offset 200h and Advanced Error Report. */
+ /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
+ /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
+ pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e);
+
pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6),
(1 << 20) | (3 << 6));
/* Enable Relaxed Order from Root Port. */