diff options
Diffstat (limited to 'src')
314 files changed, 2964 insertions, 1290 deletions
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 05ada084ab..fc1368990e 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1331,6 +1331,14 @@ unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t return lpi_desc->header.length; } +/* BERT helpers */ +bool __weak acpi_is_boot_error_src_present(void) +{ + return false; +} + +__weak void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length) {} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -1352,6 +1360,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_tpm2_t *tpm2; acpi_madt_t *madt; acpi_lpit_t *lpit; + acpi_bert_t *bert; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -1573,6 +1582,20 @@ unsigned long write_acpi_tables(unsigned long start) current = acpi_align_current(current); + if (acpi_is_boot_error_src_present()) { + void *region; + size_t size; + printk(BIOS_DEBUG, "ACPI: * BERT\n"); + bert = (acpi_bert_t *) current; + acpi_soc_fill_bert(bert, ®ion, &size); + acpi_write_bert(bert, (uintptr_t)region, size); + if (bert->header.length >= sizeof(acpi_bert_t)) { + current += bert->header.length; + acpi_add_table(rsdp, bert); + } + current = acpi_align_current(current); + } + printk(BIOS_DEBUG, "current = %lx\n", current); for (dev = all_devices; dev; dev = dev->next) { diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index 173a0a3a83..45868b573a 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -7,7 +7,7 @@ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ -#include <arch/cache.h> /* for dmb() */ +#include <arch/cache.h> #include <endian.h> #include <stdint.h> diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index de56291ac4..ec31917444 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -106,6 +106,7 @@ static void revise_error_sizes(acpi_generic_error_status_t *status, size_t size) entries = bert_entry_count(status); entry = acpi_hest_generic_data_nth(status, entries); status->data_length += size; + status->raw_data_length += size; if (entry) entry->data_length += size; } @@ -174,6 +175,7 @@ static acpi_hest_generic_data_v300_t *new_generic_error_entry( entry->validation_bits |= ACPI_GENERROR_VALID_TIMESTAMP; status->data_length += sizeof(*entry); + status->raw_data_length += sizeof(*entry); bert_bump_entry_count(status); return entry; @@ -186,12 +188,52 @@ static size_t sizeof_error_section(guid_t *guid) return sizeof(cper_proc_generic_error_section_t); else if (!guidcmp(guid, &CPER_SEC_PROC_IA32X64_GUID)) return sizeof(cper_ia32x64_proc_error_section_t); + else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + return sizeof(cper_fw_err_rec_section_t); /* else if ... sizeof(structures not yet defined) */ printk(BIOS_ERR, "Error: Requested size of unrecognized CPER GUID\n"); return 0; } +void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size) +{ + void *cl_data = bert_allocate_storage(cl_size); + if (!cl_data) { + printk(BIOS_ERR, "Error: Crashlog entry (size %lu) would exceed available region\n", + cl_size); + return NULL; + } + + revise_error_sizes(status, cl_size); + + return cl_data; +} + +/* Helper to append an ACPI Generic Error Data Entry per crashlog data */ +acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status) +{ + acpi_hest_generic_data_v300_t *entry; + cper_fw_err_rec_section_t *fw_err; + + entry = bert_append_error_datasection(status, &CPER_SEC_FW_ERR_REC_REF_GUID); + if (!entry) + return NULL; + + status->block_status |= GENERIC_ERR_STS_UNCORRECTABLE_VALID; + status->error_severity = ACPI_GENERROR_SEV_FATAL; + entry->error_severity = ACPI_GENERROR_SEV_FATAL; + + fw_err = section_of_acpientry(fw_err, entry); + + fw_err->record_type = CRASHLOG_RECORD_TYPE; + fw_err->revision = CRASHLOG_FW_ERR_REV; + fw_err->record_id = 0; + guidcpy(&fw_err->record_guid, &FW_ERR_RECORD_ID_CRASHLOG_GUID); + + return entry; +} + /* Append a new ACPI Generic Error Data Entry plus CPER Error Section to an * existing ACPI Generic Error Status Block. The caller is responsible for * the setting the status and entry severity, as well as populating all fields @@ -486,10 +528,14 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid) if (!status) return NULL; + status->raw_data_length = sizeof(*status); + if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) r = bert_append_genproc(status); else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) r = bert_append_ia32x64(status); + if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + r = bert_append_fw_err(status); /* else if other types not implemented */ else r = NULL; diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d054cfe72c..67a76a1c2c 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -334,7 +334,7 @@ void arch_bootstate_coreboot_exit(void) * function will always getting called from coreboot context * (ESP stack pointer will always refer to coreboot). * - * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * But with MP_SERVICES_PPI implementation in coreboot this * assumption might not be true, where FSP context (stack pointer refers * to FSP) will request to get cpu_index(). * diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 060e1a43f2..0d373e10b4 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -41,6 +41,9 @@ * +--------------------------------------------------------------------+ */ +#define CRASHLOG_RECORD_TYPE 0x2 +#define CRASHLOG_FW_ERR_REV 0x2 + /* Get implementation-specific reserved area for generating BERT info */ void bert_reserved_region(void **start, size_t *size); @@ -120,6 +123,9 @@ acpi_hest_generic_data_v300_t *bert_append_genproc( acpi_hest_generic_data_v300_t *bert_append_ia32x64( acpi_generic_error_status_t *status); +void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size); +acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status); + /* Add a new event to the BERT region. An event consists of an ACPI Error * Status Block, a Generic Error Data Entry, and an associated CPER Error * Section. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b622465a25..c2cc4ef5c0 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -306,7 +306,7 @@ uint32_t cpu_get_feature_flags_edx(void); * function will always getting called from coreboot context * (ESP stack pointer will always refer to coreboot). * - * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * But with MP_SERVICES_PPI implementation in coreboot this * assumption might not be true, where FSP context (stack pointer refers * to FSP) will request to get cpu_index(). * diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8c595ff3d4..c7827ed5e5 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -686,15 +686,16 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_upgrade = get_socket_type(); len = t->length + smbios_string_table_len(t->eos); if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { - t->max_speed = cpuid_ebx(0x16); t->current_speed = cpuid_eax(0x16); /* base frequency */ t->external_clock = cpuid_ecx(0x16); } else { - t->max_speed = smbios_cpu_get_max_speed_mhz(); t->current_speed = smbios_cpu_get_current_speed_mhz(); t->external_clock = smbios_processor_external_clock(); } + /* This field identifies a capability for the system, not the processor itself. */ + t->max_speed = smbios_cpu_get_max_speed_mhz(); + if (cpu_have_cpuid()) { res = cpuid(1); diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index f58d7b11c2..ae644de27c 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -4,6 +4,7 @@ #define _CBMEM_ID_H_ #define CBMEM_ID_ACPI 0x41435049 +#define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_GNVS 0x474e5653 #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 @@ -14,6 +15,7 @@ #define CBMEM_ID_CBTABLE_FWD 0x43425443 #define CBMEM_ID_CB_EARLY_DRAM 0x4544524D #define CBMEM_ID_CONSOLE 0x434f4e53 +#define CBMEM_ID_CPU_CRASHLOG 0x4350555f #define CBMEM_ID_COVERAGE 0x47434f56 #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 #define CBMEM_ID_ELOG 0x454c4f47 @@ -31,6 +33,7 @@ #define CBMEM_ID_MMC_STATUS 0x4d4d4353 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 +#define CBMEM_ID_PMC_CRASHLOG 0x504d435f #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 @@ -76,6 +79,7 @@ #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ + { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ @@ -87,6 +91,7 @@ { CBMEM_ID_CB_EARLY_DRAM, "EARLY DRAM USAGE" }, \ { CBMEM_ID_CONSOLE, "CONSOLE " }, \ { CBMEM_ID_COVERAGE, "COVERAGE " }, \ + { CBMEM_ID_CPU_CRASHLOG, "CPU CRASHLOG"}, \ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ { CBMEM_ID_ELOG, "ELOG " }, \ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ @@ -101,6 +106,7 @@ { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ + { CBMEM_ID_PMC_CRASHLOG, "PMC CRASHLOG"}, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ { CBMEM_ID_MTC, "MTC " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 641cea815c..a22d7f9eab 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -44,8 +44,8 @@ endchoice config MAX_CPUS int - default 4 if SMM_ASEG - default 32 + default 32 if SMM_TSEG + default 4 config CPU_QEMU_X86_64 bool "Experimental 64bit support" diff --git a/src/device/Kconfig b/src/device/Kconfig index 0e5de456ae..421ad66fea 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -117,6 +117,16 @@ config NO_GFX_INIT endchoice +config PRE_GRAPHICS_DELAY + int "Graphics initialization delay in ms" + default 0 + depends on VGA_ROM_RUN + help + On some systems, coreboot boots so fast that connected monitors + (mostly TVs) won't be able to wake up fast enough to talk to the + VBIOS. On those systems we need to wait for a bit before executing + the VBIOS. + config ONBOARD_VGA_IS_PRIMARY bool "Use onboard VGA as primary video device" default n diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index e1899f13c0..e383821d55 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -174,9 +174,9 @@ static int wait_for_valid(u8 *base) reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - while (timeout--) { + while (timeout--) udelay(1); - } + timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); diff --git a/src/device/device.c b/src/device/device.c index ffdfeac22c..18efd5dcd5 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -166,8 +166,8 @@ static void read_resources(struct bus *bus) if (!curdev->ops || !curdev->ops->read_resources) { if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); + printk(BIOS_ERR, "%s missing %s\n", + dev_path(curdev), __func__); continue; } post_log_path(curdev); @@ -178,8 +178,8 @@ static void read_resources(struct bus *bus) read_resources(link); } post_log_clear(); - printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->secondary, bus->link_num); } struct device *vga_pri = NULL; @@ -210,11 +210,10 @@ static void set_vga_bridge_bits(void) "A bridge on the path doesn't support 16-bit VGA decoding!"); } - if (dev->on_mainboard) { + if (dev->on_mainboard) vga_onboard = dev; - } else { + else vga = dev; - } /* It isn't safe to enable all VGA cards. */ dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); @@ -269,8 +268,8 @@ void assign_resources(struct bus *bus) { struct device *curdev; - printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", + dev_path(bus->dev), __func__, bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -285,8 +284,8 @@ void assign_resources(struct bus *bus) curdev->ops->set_resources(curdev); } post_log_clear(); - printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->secondary, bus->link_num); } /** diff --git a/src/device/device_const.c b/src/device/device_const.c index 5288a743b6..2ce76c61e5 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -9,7 +9,7 @@ #include <device/resource.h> /** Linked list of ALL devices */ -DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root; +DEVTREE_CONST struct device *DEVTREE_CONST all_devices = &dev_root; /** * Given a PCI bus and a devfn number, find the device structure. diff --git a/src/device/device_util.c b/src/device/device_util.c index 0337fb2fb2..71c281e33e 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -370,7 +370,8 @@ struct resource *new_resource(struct device *dev, unsigned int index) resource->next = NULL; tail = dev->resource_list; if (tail) { - while (tail->next) tail = tail->next; + while (tail->next) + tail = tail->next; tail->next = resource; } else { dev->resource_list = resource; @@ -555,7 +556,7 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, /* If it is a subtractive resource recurse. */ if (res->flags & IORESOURCE_SUBTRACTIVE) { - struct bus * subbus; + struct bus *subbus; for (subbus = curdev->link_list; subbus; subbus = subbus->next) if (subbus->link_num @@ -604,11 +605,10 @@ void dev_set_enabled(struct device *dev, int enable) return; dev->enabled = enable; - if (dev->ops && dev->ops->enable) { + if (dev->ops && dev->ops->enable) dev->ops->enable(dev); - } else if (dev->chip_ops && dev->chip_ops->enable_dev) { + else if (dev->chip_ops && dev->chip_ops->enable_dev) dev->chip_ops->enable_dev(dev); - } } void disable_children(struct bus *bus) @@ -814,7 +814,7 @@ void show_one_resource(int debug_level, struct device *dev, buf, resource_type(resource), comment); } -void show_all_devs_resources(int debug_level, const char* msg) +void show_all_devs_resources(int debug_level, const char *msg) { struct device *dev; diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index a65cdada89..93ec854cf8 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -48,19 +48,17 @@ int i2c_dev_readb(struct device *const dev) .len = sizeof(val), }; - const int ret = busdev->ops->ops_i2c_bus-> - transfer(busdev, &msg, 1); + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); if (ret) return ret; else return val; } else if (busdev->ops->ops_smbus_bus->recv_byte) { return busdev->ops->ops_smbus_bus->recv_byte(dev); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte", dev_path(busdev)); + return -1; } int i2c_dev_writeb(struct device *const dev, uint8_t val) @@ -79,11 +77,11 @@ int i2c_dev_writeb(struct device *const dev, uint8_t val) return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); } else if (busdev->ops->ops_smbus_bus->send_byte) { return busdev->ops->ops_smbus_bus->send_byte(dev, val); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", + dev_path(busdev)); + return -1; } int i2c_dev_readb_at(struct device *const dev, uint8_t off) @@ -109,23 +107,21 @@ int i2c_dev_readb_at(struct device *const dev, uint8_t off) }, }; - const int ret = busdev->ops->ops_i2c_bus-> - transfer(busdev, msg, ARRAY_SIZE(msg)); + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg, + ARRAY_SIZE(msg)); if (ret) return ret; else return val; } else if (busdev->ops->ops_smbus_bus->read_byte) { return busdev->ops->ops_smbus_bus->read_byte(dev, off); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte", dev_path(busdev)); + return -1; } -int i2c_dev_writeb_at(struct device *const dev, - const uint8_t off, const uint8_t val) +int i2c_dev_writeb_at(struct device *const dev, const uint8_t off, const uint8_t val) { struct device *const busdev = i2c_busdev(dev); if (!busdev) @@ -142,15 +138,15 @@ int i2c_dev_writeb_at(struct device *const dev, return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1); } else if (busdev->ops->ops_smbus_bus->write_byte) { return busdev->ops->ops_smbus_bus->write_byte(dev, off, val); - } else { - printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", - dev_path(busdev)); - return -1; } + + printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", + dev_path(busdev)); + return -1; } -int i2c_dev_read_at16(struct device *const dev, - uint8_t *const buf, const size_t len, uint16_t off) +int i2c_dev_read_at16(struct device *const dev, uint8_t *const buf, const size_t len, + uint16_t off) { struct device *const busdev = i2c_busdev(dev); if (!busdev) @@ -173,8 +169,8 @@ int i2c_dev_read_at16(struct device *const dev, }; write_be16(&off, off); - const int ret = busdev->ops->ops_i2c_bus->transfer( - busdev, msg, ARRAY_SIZE(msg)); + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg, + ARRAY_SIZE(msg)); if (ret) return ret; else diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 66f5447126..cd98f07605 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -732,6 +732,12 @@ static int should_load_oprom(struct device *dev) return 0; } +static void oprom_pre_graphics_stall(void) +{ + if (CONFIG_PRE_GRAPHICS_DELAY) + mdelay(CONFIG_PRE_GRAPHICS_DELAY); +} + /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { @@ -760,6 +766,9 @@ void pci_dev_init(struct device *dev) if (!should_run_oprom(dev, rom)) return; + /* Wait for any configured pre-graphics delay */ + oprom_pre_graphics_stall(); + run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 89194ad0be..30d11313cb 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -393,7 +393,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -407,19 +407,16 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); - if (!res) { + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_2); + if (!res) dev_err(dev->pdev, "BAR2 resource not found.\n"); - ret = -EIO; - goto out_free; - } /* * If we don't have IO space at all, use MMIO now and * assume the chip has MMIO enabled by default (rev 0x20 * and higher). */ - if (!(res->flags & IORESOURCE_IO)) { + if (!res || !(res->flags & IORESOURCE_IO)) { DRM_INFO("platform has no IO space, trying MMIO\n"); ast->ioregs = ast->regs + AST_IO_MM_OFFSET; ast->io_space_uses_mmap = true; @@ -432,8 +429,6 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ret = -EIO; goto out_free; } - /* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */ - ast->ioregs = (void *)AST_IO_MM_OFFSET; } ast_detect_chip(dev, &need_post); diff --git a/src/drivers/generic/bayhub_lv2/Kconfig b/src/drivers/generic/bayhub_lv2/Kconfig new file mode 100644 index 0000000000..e9f66af8ed --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_BAYHUB_LV2 + bool diff --git a/src/drivers/generic/bayhub_lv2/Makefile.inc b/src/drivers/generic/bayhub_lv2/Makefile.inc new file mode 100644 index 0000000000..11249a9262 --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_BAYHUB_LV2) += lv2.c diff --git a/src/drivers/generic/bayhub_lv2/chip.h b/src/drivers/generic/bayhub_lv2/chip.h new file mode 100644 index 0000000000..aa8f3fd879 --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdbool.h> + +/* Bayhub LV2 PCIe to SD bridge */ +struct drivers_generic_bayhub_lv2_config { + bool enable_power_saving; +}; diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c new file mode 100644 index 0000000000..9e9f0746ae --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for BayHub Technology LV2 PCI to SD bridge */ + +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include "chip.h" +#include "lv2.h" + +static void lv2_init(struct device *dev) +{ + struct drivers_generic_bayhub_lv2_config *config = dev->chip_info; + pci_dev_init(dev); + + if (!config || !config->enable_power_saving) + return; + /* + * This procedure for enabling power-saving mode is from the + * BayHub BIOS Implementation Guideline document. + */ + pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF); + pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE); + pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER); + pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER); + pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE); + pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING); + pci_update_config32(dev, LV2_PCR_HEX_248, LV2_L1_SUBSTATE_SETTING_MASK, + LV2_L1_SUBSTATE_SETTING); + pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK, + LV2_L1_SUBSTATE_OPTIMISE); + pci_or_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_CLKREQ); + pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW); + pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK, + LV2_DRIVER_STRENGTH); + pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK, + LV2_RESET_DMA_DISABLE); + pci_update_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_L1_L0_MASK, + LV2_LINK_CTRL_L1_ENABLE); + pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON); + printk(BIOS_INFO, "BayHub LV2: Power-saving enabled (link_ctrl=%#x)\n", + pci_read_config32(dev, LV2_LINK_CTRL)); +} + +static struct device_operations lv2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .init = lv2_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_O2_LV2, + 0 +}; + +static const struct pci_driver bayhub_lv2 __pci_driver = { + .ops = &lv2_ops, + .vendor = PCI_VENDOR_ID_O2, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_bayhub_lv2_ops = { + CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge") +}; diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h new file mode 100644 index 0000000000..464fed8ac0 --- /dev/null +++ b/src/drivers/generic/bayhub_lv2/lv2.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for BayHub Technology LV2 PCIe to SD bridge */ + +#include <types.h> + +enum { + LV2_PROTECT = 0xD0, + LV2_PROTECT_LOCK_OFF = 0, + LV2_PROTECT_LOCK_ON = BIT(0), + LV2_PROTECT_OFF = 0, + LV2_PROTECT_ON = BIT(31), + LV2_PCR_HEX_FC = 0xFC, + LV2_PCIE_PHY_P1_ENABLE = BIT(25), + LV2_ASPM_L1_TIMER = 0x000E0000, + LV2_ASPM_L1_TIMER_MASK = 0xFFF0FFFF, + LV2_PCR_HEX_A8 = 0xA8, + LV2_LTR_ENABLE = BIT(10), + LV2_PCR_HEX_E0 = 0xE0, + LV2_PCI_PM_L1_TIMER = 0x30000000, + LV2_PCI_PM_L1_TIMER_MASK = 0x0FFFFFFF, + LV2_PCR_HEX_234 = 0x234, + LV2_MAX_LATENCY_SETTING = 0x10011001, + LV2_PCR_HEX_248 = 0x248, + LV2_L1_SUBSTATE_SETTING = 0x0000000A, + LV2_L1_SUBSTATE_SETTING_MASK = 0xFFFFFFF0, + LV2_PCR_HEX_3F4 = 0x3F4, + LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A, + LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0, + LV2_PCR_HEX_300 = 0x300, + LV2_TUNING_WINDOW = 0x00006055, + LV2_TUNING_WINDOW_MASK = 0xFFFF0F00, + LV2_PCR_HEX_304 = 0x304, + LV2_DRIVER_STRENGTH = 0x0000224B, + LV2_DRIVER_STRENGTH_MASK = 0xFFFF0000, + LV2_PCR_HEX_308 = 0x308, + LV2_RESET_DMA_DISABLE = 0x00C00000, + LV2_RESET_DMA_DISABLE_MASK = 0xFF3FFFFF, + LV2_LINK_CTRL = 0x90, + LV2_LINK_CTRL_L1_ENABLE = BIT(1), + LV2_LINK_CTRL_L1_L0_MASK = 0xFFFFFFFC, + LV2_LINK_CTRL_CLKREQ = BIT(8), +}; diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index db4c3aedbd..5408d9e0d5 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -4,7 +4,7 @@ #define _DRIVERS_INTEL_DPTF_CHIP_H_ #include <acpi/acpigen_dptf.h> -#include <timer.h> /* for MSECS_PER_SEC */ +#include <timer.h> #define DPTF_PASSIVE(src, tgt, tmp, prd) \ {.source = DPTF_##src, .target = DPTF_##tgt, .temp = (tmp), .period = (prd)} diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index c452f0b00d..23eadfa978 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -9,7 +9,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/mma.h> -#include <soc/pm.h> /* chip_power_state */ +#include <soc/pm.h> struct romstage_params { uint32_t fsp_version; diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dd08d77e1e..4c468e5534 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -8,7 +8,7 @@ #include <cpu/x86/smm.h> #include <fsp/romstage.h> #include <fsp/util.h> -#include <lib.h> /* hexdump */ +#include <lib.h> #include <string.h> #include <timestamp.h> diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 14d97426c2..285bedf8b7 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -31,6 +31,13 @@ config PLATFORM_USES_FSP2_2 if PLATFORM_USES_FSP2_0 +config PLATFORM_USES_FSP2_X86_32 + bool + default y + help + The FSP 2.0 runs in x86_32 protected mode. + Once there's a x86_64 FSP this needs to default to n. + config HAVE_INTEL_FSP_REPO bool help @@ -173,16 +180,6 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory. -config FSP_PEIM_TO_PEIM_INTERFACE - bool - select FSP_USES_MP_SERVICES_PPI - help - This option allows SOC user to create specific PPI for Intel FSP - usage, coreboot will provide required PPI structure definitions - along with all APIs as per EFI specification. So far this feature - is limited till EFI_PEI_MP_SERVICE_PPI and this option might be - useful to add further PPI if required. - config HAVE_FSP_LOGO_SUPPORT bool default n @@ -271,9 +268,4 @@ config SOC_INTEL_COMMON_FSP_RESET Common code block to handle platform reset request raised by FSP. The FSP will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required. - -if FSP_PEIM_TO_PEIM_INTERFACE -source "src/drivers/intel/fsp2_0/ppi/Kconfig" -endif - endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b518bec180..094308022a 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -95,7 +95,6 @@ ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) endif -# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable -subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi +subdirs-y += ppi endif diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index a134fed065..4f9366657d 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -19,24 +19,24 @@ void fsp_print_header_info(const struct fsp_header *hdr) printk(BIOS_SPEW, "Type: %s/%s\n", (hdr->component_attribute & 1) ? "release" : "debug", (hdr->component_attribute & 2) ? "official" : "test"); - printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", - hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n", + hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size); printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", - hdr->cfg_region_offset, hdr->cfg_region_size); + (size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size); if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", - hdr->memory_init_entry_offset); + (size_t)hdr->memory_init_entry_offset); } if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", - hdr->silicon_init_entry_offset); + (size_t)hdr->silicon_init_entry_offset); if (CONFIG(PLATFORM_USES_FSP2_2)) printk(BIOS_SPEW, "\tMultiPhaseSiInit offset 0x%zx\n", - hdr->multi_phase_si_init_entry_offset); + (size_t)hdr->multi_phase_si_init_entry_offset); printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", - hdr->notify_phase_entry_offset); + (size_t)hdr->notify_phase_entry_offset); } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f237a378f1..aa9a435a75 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -4,6 +4,7 @@ #define _FSP2_0_INFO_HEADER_H_ #include <types.h> +#include <commonlib/bsd/compiler.h> #define FSP_HDR_OFFSET 0x94 #if CONFIG(PLATFORM_USES_FSP2_2) @@ -16,24 +17,29 @@ #define FSP_HDR_ATTRIB_FSPM 2 #define FSP_HDR_ATTRIB_FSPS 3 +#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { uint32_t fsp_revision; - size_t image_size; - uintptr_t image_base; + uint32_t image_size; + uint32_t image_base; uint16_t image_attribute; uint8_t spec_version; uint16_t component_attribute; - size_t cfg_region_offset; - size_t cfg_region_size; - size_t temp_ram_init_entry; - size_t temp_ram_exit_entry; - size_t notify_phase_entry_offset; - size_t memory_init_entry_offset; - size_t silicon_init_entry_offset; - size_t multi_phase_si_init_entry_offset; + uint32_t cfg_region_offset; + uint32_t cfg_region_size; + uint32_t temp_ram_init_entry; + uint32_t temp_ram_exit_entry; + uint32_t notify_phase_entry_offset; + uint32_t memory_init_entry_offset; + uint32_t silicon_init_entry_offset; + uint32_t multi_phase_si_init_entry_offset; char image_id[sizeof(uint64_t) + 1]; uint8_t revision; -}; +} __packed; +#else +#error You need to implement this struct for x86_64 FSP +#endif + enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); diff --git a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h index 836e996631..3c30063111 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h +++ b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h @@ -11,10 +11,36 @@ #include <efi/efi_datatype.h> #include <fsp/soc_binding.h> -/* - * SOC must call this function to get required EFI_PEI_MP_SERVICES_PPI - * structure. - */ -efi_pei_mp_services_ppi *mp_fill_ppi_services_data(void); +/* SOC must call this function to get required EFI_PEI_MP_SERVICES_PPI structure */ +void *mp_fill_ppi_services_data(void); + +/* get the number of logical processors in the platform */ +efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors, + efi_uintn_t *number_of_enabled_processors); + +/* get processor info such as id, status */ +efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, + efi_processor_information *processor_info_buffer); + +/* executes a caller provided function on all enabled APs */ +efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure, + efi_uintn_t timeout_usec, void *argument); + +/* executes a caller provided function on all enabled APs + BSP */ +efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, + efi_uintn_t timeout_usec, void *argument); + +/* executes a caller provided function on specific AP */ +efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure, + efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument); + +/* get the processor instance */ +efi_return_status_t mp_identify_processor(efi_uintn_t *processor_number); + +/* for the APIs that are not supported/required */ +static inline efi_return_status_t mp_api_unsupported(void) +{ + return FSP_UNSUPPORTED; +} #endif /* MP_SERVICE_PPI_H */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 979cff3b91..827c95d980 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -21,6 +21,7 @@ struct FSP_UPD_HEADER { uint8_t Reserved[23]; } __packed; +#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct FSPM_ARCH_UPD { /// /// Revision of the structure. For FSP v2.0 value is 1. @@ -31,12 +32,12 @@ struct FSPM_ARCH_UPD { /// Pointer to the non-volatile storage (NVS) data buffer. /// If it is NULL it indicates the NVS data is not available. /// - void *NvsBufferPtr; + uint32_t NvsBufferPtr; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - void *StackBase; + uint32_t StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. @@ -53,7 +54,11 @@ struct FSPM_ARCH_UPD { uint32_t BootMode; uint8_t Reserved1[8]; } __packed; +#else +#error You need to implement this struct for x86_64 FSP +#endif +#endif struct FSPS_ARCH_UPD { /// /// Revision of the structure. For FSP v2.2 value is 1. diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 92f3d9d960..f2fcec4061 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -87,7 +87,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) void *data; size_t mrc_size; - arch_upd->NvsBufferPtr = NULL; + arch_upd->NvsBufferPtr = 0; if (!CONFIG(CACHE_MRC_SETTINGS)) return; @@ -101,7 +101,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) return; /* MRC cache found */ - arch_upd->NvsBufferPtr = data; + arch_upd->NvsBufferPtr = (uintptr_t)data; printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size); } @@ -142,7 +142,7 @@ static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, stack_end) != CB_SUCCESS) return CB_ERR; - arch_upd->StackBase = (void *)stack_begin; + arch_upd->StackBase = stack_begin; return CB_SUCCESS; } @@ -159,7 +159,7 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. */ if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { - arch_upd->StackBase = temp_ram; + arch_upd->StackBase = (uintptr_t)temp_ram; arch_upd->StackSize = sizeof(temp_ram); } else if (setup_fsp_stack_frame(arch_upd, memmap)) { return CB_ERR; @@ -237,7 +237,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) fsp_version = fsp_memory_settings_version(hdr); - upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); fsp_verify_upd_header_signature(upd->FspUpdHeader.Signature, FSPM_UPD_SIGNATURE); @@ -289,12 +289,12 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) post_code(POST_MEM_PREINIT_PREP_END); /* Call FspMemoryInit */ - fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); - if (ENV_X86_64) + if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) status = protected_mode_call_2arg(fsp_raminit, (uintptr_t)&fspm_upd, (uintptr_t)fsp_get_hob_list_ptr()); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 8a51c0bad7..cbccc6eacf 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -16,7 +16,7 @@ static void fsp_notify(enum fsp_notify_phase phase) if (!fsps_hdr.notify_phase_entry_offset) die("Notify_phase_entry_offset is zero!\n"); - fspnotify = (void *) (fsps_hdr.image_base + + fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); fsp_before_debug_notify(fspnotify, ¬ify_params); @@ -31,7 +31,7 @@ static void fsp_notify(enum fsp_notify_phase phase) post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE); } - if (ENV_X86_64) + if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) ret = protected_mode_call_1arg(fspnotify, (uintptr_t)¬ify_params); else ret = fspnotify(¬ify_params); diff --git a/src/drivers/intel/fsp2_0/ppi/Kconfig b/src/drivers/intel/fsp2_0/ppi/Kconfig index 4f77a32cb2..7cbc87f7ab 100644 --- a/src/drivers/intel/fsp2_0/ppi/Kconfig +++ b/src/drivers/intel/fsp2_0/ppi/Kconfig @@ -1,11 +1,28 @@ # SPDX-License-Identifier: GPL-2.0-only -config FSP_USES_MP_SERVICES_PPI +config MP_SERVICES_PPI bool default n depends on SOC_INTEL_COMMON_BLOCK_CPU_MPINIT help - This option allows SoC user to create MP service PPI for Intel - FSP usage, coreboot will provide EFI_PEI_MP_SERVICES_PPI structure - definitions along with all APIs as per EDK2 specification. Intel FSP - will use this PPI to run CPU feature programming on APs. + This option allows to create MP service PPI for Intel FSP usage. + Intel FSP will use this PPI to run CPU feature programming on APs. + +config MP_SERVICES_PPI_V1 + bool + default n + select MP_SERVICES_PPI + help + This option provides EFI_PEI_MP_SERVICES_PPI structure definitions + along with all APIs as per EDK2 specification. + +config MP_SERVICES_PPI_V2 + bool + default n + select MP_SERVICES_PPI + help + This option provides EDKII_PEI_MP_SERVICES2_PPI structure definitions + along with all APIs as per EDK2 specification. MP services2 PPI is slight + modification over MP services1 PPIs. A new API StartupAllCPUs have been + added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES + parameter has been removed from all MP PPI APIs. diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc index 8d8d990abb..8bda899ea9 100644 --- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc +++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c +ramstage-$(CONFIG_MP_SERVICES_PPI) += mp_service_ppi.c +ramstage-$(CONFIG_MP_SERVICES_PPI_V1) += mp_service1.c +ramstage-$(CONFIG_MP_SERVICES_PPI_V2) += mp_service2.c diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service1.c b/src/drivers/intel/fsp2_0/ppi/mp_service1.c new file mode 100644 index 0000000000..7d351e40f4 --- /dev/null +++ b/src/drivers/intel/fsp2_0/ppi/mp_service1.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> +#include <Ppi/MpServices.h> + +typedef EFI_PEI_MP_SERVICES_PPI efi_pei_mp_services_ppi; + +static efi_return_status_t mps1_get_number_of_processors(const + efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, + efi_uintn_t *number_of_processors, efi_uintn_t *number_of_enabled_processors) +{ + return mp_get_number_of_processors(number_of_processors, number_of_enabled_processors); +} + +static efi_return_status_t mps1_get_processor_info(const + efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, + efi_uintn_t processor_number, + efi_processor_information *processor_info_buffer) +{ + return mp_get_processor_info(processor_number, processor_info_buffer); +} + +static efi_return_status_t mps1_startup_all_aps(const + efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, + efi_ap_procedure procedure, efi_boolean_t ignored3, + efi_uintn_t timeout_usec, void *argument) +{ + return mp_startup_all_aps(procedure, timeout_usec, argument); +} + +static efi_return_status_t mps1_startup_this_ap(const + efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, + efi_ap_procedure procedure, efi_uintn_t processor_number, + efi_uintn_t timeout_usec, void *argument) +{ + return mp_startup_this_ap(procedure, processor_number, timeout_usec, argument); +} + +static efi_return_status_t mps1_switch_bsp(const efi_pei_services **ignored1, + efi_pei_mp_services_ppi *ignored2, efi_uintn_t ignored3, + efi_boolean_t ignored4) +{ + return mp_api_unsupported(); +} + +static efi_return_status_t mps1_enable_disable_ap(const + efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, + efi_uintn_t ignored3, efi_boolean_t ignored4, efi_uint32_t *ignored5) +{ + return mp_api_unsupported(); +} + +static efi_return_status_t mps1_identify_processor(const + efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, + efi_uintn_t *processor_number) +{ + return mp_identify_processor(processor_number); +} + +/* EDK2 UEFIPKG Open Source MP Service PPI to be installed */ + +static efi_pei_mp_services_ppi mp_service1_ppi = { + mps1_get_number_of_processors, + mps1_get_processor_info, + mps1_startup_all_aps, + mps1_startup_this_ap, + mps1_switch_bsp, + mps1_enable_disable_ap, + mps1_identify_processor, +}; + +void *mp_fill_ppi_services_data(void) +{ + return (void *)&mp_service1_ppi; +} diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service2.c b/src/drivers/intel/fsp2_0/ppi/mp_service2.c new file mode 100644 index 0000000000..8d27b16e77 --- /dev/null +++ b/src/drivers/intel/fsp2_0/ppi/mp_service2.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> +#include <Ppi/MpServices2.h> + +typedef EDKII_PEI_MP_SERVICES2_PPI efi_pei_mp_services_ppi; + +static efi_return_status_t mps2_get_number_of_processors( + efi_pei_mp_services_ppi *ignored1, + efi_uintn_t *number_of_processors, + efi_uintn_t *number_of_enabled_processors) +{ + return mp_get_number_of_processors(number_of_processors, number_of_enabled_processors); +} + +static efi_return_status_t mps2_get_processor_info( + efi_pei_mp_services_ppi *ignored1, + efi_uintn_t processor_number, + efi_processor_information *processor_info_buffer) +{ + return mp_get_processor_info(processor_number, processor_info_buffer); +} + +static efi_return_status_t mps2_startup_all_aps( + efi_pei_mp_services_ppi *ignored1, + efi_ap_procedure procedure, efi_boolean_t ignored2, + efi_uintn_t timeout_usec, void *argument) +{ + return mp_startup_all_aps(procedure, timeout_usec, argument); +} + +static efi_return_status_t mps2_startup_all_cpus( + efi_pei_mp_services_ppi *ignored1, + efi_ap_procedure procedure, + efi_uintn_t timeout_usec, void *argument) +{ + return mp_startup_all_cpus(procedure, timeout_usec, argument); +} + +static efi_return_status_t mps2_startup_this_ap( + efi_pei_mp_services_ppi *ignored1, + efi_ap_procedure procedure, efi_uintn_t processor_number, + efi_uintn_t timeout_usec, void *argument) +{ + return mp_startup_this_ap(procedure, processor_number, timeout_usec, argument); +} + +static efi_return_status_t mps2_switch_bsp( + efi_pei_mp_services_ppi *ignored1, efi_uintn_t ignored2, + efi_boolean_t ignored3) +{ + return mp_api_unsupported(); +} + +static efi_return_status_t mps2_enable_disable_ap( + efi_pei_mp_services_ppi *ignored1, + efi_uintn_t ignored2, efi_boolean_t ignored3, efi_uint32_t *ignored4) +{ + return mp_api_unsupported(); +} + +static efi_return_status_t mps2_identify_processor( + efi_pei_mp_services_ppi *ignored1, + efi_uintn_t *processor_number) +{ + return mp_identify_processor(processor_number); +} + +/* EDK2 UEFIPKG Open Source MP Services 2 PPI to be installed */ + +static efi_pei_mp_services_ppi mp_service2_ppi = { + mps2_get_number_of_processors, + mps2_get_processor_info, + mps2_startup_all_aps, + mps2_startup_this_ap, + mps2_switch_bsp, + mps2_enable_disable_ap, + mps2_identify_processor, + mps2_startup_all_cpus, +}; + +void *mp_fill_ppi_services_data(void) +{ + return (void *)&mp_service2_ppi; +} diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 03184e16ca..87056a5b7c 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -12,9 +12,7 @@ #define BSP_CPU_SLOT 0 #define SINGLE_CHIP_PACKAGE 0 -static efi_return_status_t mp_get_number_of_processors(const - efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, - efi_uintn_t *number_of_processors, +efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors, efi_uintn_t *number_of_enabled_processors) { if (number_of_processors == NULL || number_of_enabled_processors == @@ -27,9 +25,7 @@ static efi_return_status_t mp_get_number_of_processors(const return FSP_SUCCESS; } -static efi_return_status_t mp_get_processor_info(const - efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, - efi_uintn_t processor_number, +efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { unsigned int num_virt_cores, num_phys_cores; @@ -62,9 +58,7 @@ static efi_return_status_t mp_get_processor_info(const return FSP_SUCCESS; } -static efi_return_status_t mp_startup_all_aps(const - efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, - efi_ap_procedure procedure, efi_boolean_t ignored3, +efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure, efi_uintn_t timeout_usec, void *argument) { if (cpu_index() < 0) @@ -82,14 +76,34 @@ static efi_return_status_t mp_startup_all_aps(const return FSP_SUCCESS; } -static efi_return_status_t mp_startup_this_ap(const - efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, - efi_ap_procedure procedure, efi_uintn_t processor_number, +efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, efi_uintn_t timeout_usec, void *argument) { if (cpu_index() < 0) return FSP_DEVICE_ERROR; + if (procedure == NULL) + return FSP_INVALID_PARAMETER; + + /* Run on BSP */ + procedure(argument); + + /* Run on APs */ + if (mp_run_on_aps((void *)procedure, argument, + MP_RUN_ON_ALL_CPUS, timeout_usec)) { + printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); + return FSP_NOT_STARTED; + } + + return FSP_SUCCESS; +} + +efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure, + efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument) +{ + if (cpu_index() < 0) + return FSP_DEVICE_ERROR; + if (processor_number > get_cpu_count()) return FSP_NOT_FOUND; @@ -108,25 +122,7 @@ static efi_return_status_t mp_startup_this_ap(const return FSP_SUCCESS; } -static efi_return_status_t mp_switch_bsp(const efi_pei_services **ignored1, - efi_pei_mp_services_ppi *ignored2, efi_uintn_t ignored3, - efi_boolean_t ignored4) -{ - /* FSP don't need this API hence return unsupported */ - return FSP_UNSUPPORTED; -} - -static efi_return_status_t mp_enable_disable_ap(const - efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, - efi_uintn_t ignored3, efi_boolean_t ignored4, efi_uint32_t *ignored5) -{ - /* FSP don't need this API hence return unsupported */ - return FSP_UNSUPPORTED; -} - -static efi_return_status_t mp_identify_processor(const - efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, - efi_uintn_t *processor_number) +efi_return_status_t mp_identify_processor(efi_uintn_t *processor_number) { int index; @@ -142,22 +138,3 @@ static efi_return_status_t mp_identify_processor(const return FSP_SUCCESS; } - -/* - * EDK2 UEFIPKG Open Source MP Service PPI to be installed - */ - -static efi_pei_mp_services_ppi mp_service_ppi = { - mp_get_number_of_processors, - mp_get_processor_info, - mp_startup_all_aps, - mp_startup_this_ap, - mp_switch_bsp, - mp_enable_disable_ap, - mp_identify_processor, -}; - -efi_pei_mp_services_ppi *mp_fill_ppi_services_data(void) -{ - return &mp_service_ppi; -} diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 26ff59dbf2..8572b24901 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -86,7 +86,7 @@ static void do_silicon_init(struct fsp_header *hdr) struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; - supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); + supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base); fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE); @@ -110,14 +110,14 @@ static void do_silicon_init(struct fsp_header *hdr) logo_entry = soc_load_logo(upd); /* Call SiliconInit */ - silicon_init = (void *) (hdr->image_base + + silicon_init = (void *) (uintptr_t)(hdr->image_base + hdr->silicon_init_entry_offset); fsp_debug_before_silicon_init(silicon_init, supd, upd); timestamp_add_now(TS_FSP_SILICON_INIT_START); post_code(POST_FSP_SILICON_INIT); - if (ENV_X86_64) + if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); else status = silicon_init(upd); @@ -145,7 +145,7 @@ static void do_silicon_init(struct fsp_header *hdr) return; /* Call MultiPhaseSiInit */ - multi_phase_si_init = (void *) (hdr->image_base + + multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + hdr->multi_phase_si_init_entry_offset); /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 5c11fed423..8035b94070 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -24,7 +24,7 @@ static int send_kbd_command(u8 command) { int timeout; - timeout = 0x7ff; + timeout = 100000; /* 1 second */ while ((inb(ec_cmd_port) & KBD_IBF) && --timeout) { udelay(10); if ((timeout & 0xff) == 0) @@ -44,7 +44,7 @@ static int send_kbd_data(u8 data) { int timeout; - timeout = 0x7ff; + timeout = 100000; /* 1 second */ while ((inb(ec_cmd_port) & KBD_IBF) && --timeout) { /* wait for IBF = 0 */ udelay(10); if ((timeout & 0xff) == 0) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index fa24902331..058c0d0217 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1075,6 +1075,10 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, void acpi_create_lpit(acpi_lpit_t *lpit); unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); +/* For crashlog. */ +bool acpi_is_boot_error_src_present(void); +void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length); + /* For ACPI S3 support. */ void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 7fd9ac169b..e77c60aad3 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -41,4 +41,7 @@ void lb_table_add_serialno_from_vpd(struct lb_header *header); struct lb_record *lb_new_record(struct lb_header *header); +/* Add VBOOT VBNV offsets. */ +void lb_table_add_vbnv_cmos(struct lb_header *header); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/cper.h b/src/include/cper.h index b6d182e8ea..020ac41c77 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -370,6 +370,19 @@ typedef struct cper_ia32x64_ctx_x64state { u16 tr; } cper_ia32x64_ctx_x64state_t; +#define FW_ERR_RECORD_ID_CRASHLOG_GUID \ + GUID_INIT(0x8f87f311, 0xc998, 0x4d9e, \ + 0xa0, 0xc4, 0x60, 0x65, 0x51, 0x8c, 0x4f, 0x6d) + +/* Firmware Error Record Reference, UEFI v2.8 sec N.2.10 */ +typedef struct cper_fw_err_rec_section { + u8 record_type; + u8 revision; + u8 reserved[6]; + u64 record_id; + guid_t record_guid; +} cper_fw_err_rec_section_t; + static inline cper_timestamp_t cper_timestamp(int precise) { cper_timestamp_t ts; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 62524a3e20..d6e0ee7a05 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1753,6 +1753,7 @@ #define PCI_DEVICE_ID_O2_6832 0x6832 #define PCI_DEVICE_ID_O2_6836 0x6836 #define PCI_DEVICE_ID_O2_BH720 0x8620 +#define PCI_DEVICE_ID_O2_LV2 0x8621 #define PCI_VENDOR_ID_3DFX 0x121a #define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 @@ -3713,11 +3714,13 @@ #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b #define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_1 0x3e90 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_2 0x3e93 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_4 0x3e91 -#define PCI_DEVICE_ID_INTEL_CFL_U_GT2 0x3e96 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_5 0x3e96 #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index f6a20a7056..8766183d7a 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -3,66 +3,44 @@ /* Create EFI equivalent datatype in coreboot based on UEFI specification */ #ifndef __EFI_DATATYPE_H__ #define __EFI_DATATYPE_H__ - #include <Base.h> #include <PiPei.h> -#include <Ppi/MpServices.h> /* Basic Data types */ - /* 8-byte unsigned value. */ typedef UINT64 efi_uint64_t; - /* 8-byte signed value. */ typedef INT64 efi_int64_t; - /* 4-byte unsigned value. */ typedef UINT32 efi_uint32_t; - /* 4-byte signed value. */ typedef INT32 efi_int32_t; - /* 2-byte unsigned value. */ typedef UINT16 efi_uint16_t; - /* 2-byte Character. */ typedef CHAR16 efi_char16_t; - /* 2-byte signed value. */ typedef INT16 efi_int16_t; - /* Logical Boolean. */ typedef BOOLEAN efi_boolean_t; - /* 1-byte unsigned value. */ typedef UINT8 efi_uint8_t; - /* 1-byte Character */ typedef CHAR8 efi_char8_t; - /* 1-byte signed value */ typedef INT8 efi_int8_t; - /* Unsigned value of native width. */ typedef UINTN efi_uintn_t; - /* Signed value of native width. */ typedef INTN efi_intn_t; - /* Status codes common to all execution phases */ typedef EFI_STATUS efi_return_status_t; - /* Data structure */ - /* Data structure for EFI_PEI_SERVICE. */ typedef EFI_PEI_SERVICES efi_pei_services; -/* Data structure for UEFI PI Multi-processor PPI */ -typedef EFI_PEI_MP_SERVICES_PPI efi_pei_mp_services_ppi; - /* Structure that describes information about a logical CPU. */ typedef EFI_PROCESSOR_INFORMATION efi_processor_information; - /* * The function prototype for invoking a function on an * Application Processor. diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e00c2a4a52..5f8c69bf2a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -20,8 +20,6 @@ #include <bootmem.h> #include <bootsplash.h> #include <spi_flash.h> -#include <security/vboot/misc.h> -#include <security/vboot/vbnv_layout.h> #include <smmstore.h> #if CONFIG(USE_OPTION_TABLE) @@ -190,21 +188,6 @@ static void lb_gpios(struct lb_header *header) } } -#if CONFIG(CHROMEOS) -static void lb_vbnv(struct lb_header *header) -{ -#if CONFIG(PC80_SYSTEM) - struct lb_range *vbnv; - - vbnv = (struct lb_range *)lb_new_record(header); - vbnv->tag = LB_TAG_VBNV; - vbnv->size = sizeof(*vbnv); - vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; - vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; -#endif -} -#endif /* CONFIG_CHROMEOS */ - __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } @@ -491,10 +474,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) if (CONFIG(CHROMEOS)) lb_gpios(head); -#if CONFIG(CHROMEOS) /* pass along VBNV offsets in CMOS */ - lb_vbnv(head); -#endif + if (CONFIG(VBOOT_VBNV_CMOS)) + lb_table_add_vbnv_cmos(head); /* Pass mmc early init status */ lb_mmc_info(head); diff --git a/src/lib/metadata_hash.c b/src/lib/metadata_hash.c index f296cf58a5..a823c5f26f 100644 --- a/src/lib/metadata_hash.c +++ b/src/lib/metadata_hash.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include <assert.h> -#include <cbmem.h> #include <metadata_hash.h> #include <symbols.h> diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 224393f6f0..45178a7e23 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -1,5 +1,5 @@ #include <stdint.h> -#include <lib.h> /* Prototypes */ +#include <lib.h> #include <console/console.h> #include <device/mmio.h> diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index ce8a498263..ef0aa2048b 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS config FMDFILE string + default "src/mainboard/amd/majolica/chromeos.fmd" if CHROMEOS default "src/mainboard/amd/majolica/board.fmd" config MAINBOARD_DIR diff --git a/src/mainboard/amd/majolica/chromeos.fmd b/src/mainboard/amd/majolica/chromeos.fmd new file mode 100644 index 0000000000..90cf2eb879 --- /dev/null +++ b/src/mainboard/amd/majolica/chromeos.fmd @@ -0,0 +1,14 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + RW_LEGACY(CBFS) 4K + FW_MAIN_A(CBFS) 1M + VBLOCK_A 8K + FW_MAIN_B(CBFS) 1M + VBLOCK_B 8K + SHARED_DATA 8K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/parmer/bootblock.c b/src/mainboard/amd/parmer/bootblock.c index 29f7abb721..ccd8ec1b40 100644 --- a/src/mainboard/amd/parmer/bootblock.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <device/pci_ops.h> void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 468c938330..e01131d18e 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -2,7 +2,6 @@ #include <amdblocks/acpimmio.h> #include <bootblock_common.h> -#include <device/pci_ops.h> #include <console/console.h> #include <superio/smsc/lpc47n217/lpc47n217.h> diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 88ba11125c..4b6f9a1180 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -3,7 +3,7 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/apple/macbookair4_2/acpi/ec.asl b/src/mainboard/apple/macbookair4_2/acpi/ec.asl index 7ee0e29439..75f766bdb9 100644 --- a/src/mainboard/apple/macbookair4_2/acpi/ec.asl +++ b/src/mainboard/apple/macbookair4_2/acpi/ec.asl @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - Name (_GPE, 23) -/* FIXME: EC support */ -} +#define LIDS_OFFSET 0x60 +#define HPAC_OFFSET 0x60 +#define WKLD_OFFSET 0x68 + +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac.asl> +#include <ec/apple/acpi/lid.asl> diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c index b1a99e0ee8..9d537e6428 100644 --- a/src/mainboard/biostar/th61-itx/early_init.c +++ b/src/mainboard/biostar/th61-itx/early_init.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootblock_common.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <stdbool.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c index 0b5965a905..b351fbd8ef 100644 --- a/src/mainboard/clevo/cml-u/bootblock.c +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <gpio.h> #include <variant/gpio.h> void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f49d47dac9..80fba1de07 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -271,6 +271,12 @@ static void cpu_bus_scan(struct device *bus) if (max_cpus < 0) return; + /* + * Do not install more CPUs than supported by coreboot. + * This will cause a buffer overflow where fixed arrays of CONFIG_MAX_CPUS + * are used and might result in a boot failure. + */ + max_cpus = MIN(max_cpus, CONFIG_MAX_CPUS); /* * TODO: This only handles the simple "qemu -smp $nr" case diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index cdca27ab14..e17c8eea50 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -36,7 +36,7 @@ static void bootblock_southbridge_init(void) /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + CONFIG_FIXED_RCBA_MMIO_BASE | 1); } void bootblock_soc_init(void) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 540db040c9..e53404d55c 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -4,6 +4,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <pc80/keyboard.h> +#include <cpu/x86/smm.h> #include "q35.h" @@ -39,6 +40,9 @@ static void qemu_nb_init(struct device *dev) static void qemu_nb_read_resources(struct device *dev) { + size_t tseg_size; + uintptr_t tseg_base; + pci_dev_read_resources(dev); mmconf_resource(dev, 2); @@ -48,6 +52,9 @@ static void qemu_nb_read_resources(struct device *dev) reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, (6 * 0x1000) / KiB); } + + smm_region(&tseg_base, &tseg_size); + reserved_ram_resource(dev, ESMRAMC, tseg_base / 1024, tseg_size / 1024); } diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl deleted file mode 100644 index 2544617d30..0000000000 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/thermal.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Thermal Zone - -External (\PPKG, MethodObj) - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x03) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 10 seconds - Name (_TSP, 100) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) - { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - } -} diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index 5903648001..c510081c6d 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -15,7 +15,6 @@ DefinitionBlock( #include "acpi/mainboard.asl" #include "acpi/platform.asl" #include "acpi/superio.asl" - #include "acpi/thermal.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 88487d5a5a..59e949a388 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 88487d5a5a..59e949a388 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 9c323144e4..093a88c3ea 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 8d43464648..67f71d6e0b 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 06270b8ebb..8ba76ac5f1 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <endian.h> #include <string.h> diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b691cd16e3..ca760780ed 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -22,8 +22,6 @@ config BASEBOARD_BRYA_LAPTOP select SYSTEM_TYPE_LAPTOP config CHROMEOS - bool - default y select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 51a39c0f7a..647ea42ffe 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -14,42 +14,13 @@ chip soc/intel/alderlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - # Enable WLAN PCIE 5 using clk 2 - register "PchPcieRpEnable[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieClkSrcUsage[2]" = "5" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieRpAdvancedErrorReporting[5]" = "1" - - # Enable WWAN PCIE 6 using clk 5 - register "PchPcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - register "PcieClkSrcUsage[5]" = "6" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieRpAdvancedErrorReporting[6]" = "1" - - # Enable SD Card PCIE 8 using clk 3 - register "PchPcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieRpHotPlug[7]" = "1" - register "PcieClkSrcUsage[3]" = "7" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpAdvancedErrorReporting[7]" = "1" - - # Enable NVMe PCIE 9 using clk 1 - register "PchPcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, }" register "SerialIoGSpiMode" = "{ @@ -121,10 +92,38 @@ chip soc/intel/alderlake end device ref heci1 on end device ref sata on end - device ref pcie_rp5 on end #PCIE5 WLAN - device ref pcie_rp6 on end #PCIE6 WWAN - device ref pcie_rp8 on end #PCIE8 SD card - device ref pcie_rp9 on end #PCIE9-12 SSD + device ref pcie_rp5 on + # Enable WLAN PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE5 WLAN + device ref pcie_rp6 on + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE6 WWAN + device ref pcie_rp8 on + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE8 SD card + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9-12 SSD device ref uart0 on end device ref gspi1 on end device ref pch_espi on diff --git a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc index 03a38b2fc0..b8229c49e9 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt index 93934ae8bd..45b69ae908 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt @@ -1,2 +1,3 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:F 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) diff --git a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt index fb014a3bd3..5f837329ae 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt @@ -1 +1,2 @@ MT53E512M32D2NP-046 WT:F +H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 69280025ee..0fbacfc53b 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -38,8 +38,6 @@ config BASEBOARD_DEDEDE_LAPTOP select SYSTEM_TYPE_LAPTOP config CHROMEOS - bool - default y select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES @@ -101,6 +99,7 @@ config MAINBOARD_PART_NUMBER default "Sasuke" if BOARD_GOOGLE_SASUKE default "Storo" if BOARD_GOOGLE_STORO default "Sasukette" if BOARD_GOOGLE_SASUKETTE + default "Kracko" if BOARD_GOOGLE_KRACKO config MAX_CPUS int @@ -136,5 +135,6 @@ config VARIANT_DIR default "sasuke" if BOARD_GOOGLE_SASUKE default "storo" if BOARD_GOOGLE_STORO default "sasukette" if BOARD_GOOGLE_SASUKETTE + default "kracko" if BOARD_GOOGLE_KRACKO endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 97b90c2e5b..a1d129ec6a 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -104,3 +104,9 @@ config BOARD_GOOGLE_SASUKETTE bool "-> Sasukette" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_KRACKO + bool "-> Kracko" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 23b15969c8..fabdc5e7cc 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> -#include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index e981541122..9ed1dd0472 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -19,12 +19,30 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h b/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc b/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc new file mode 100644 index 0000000000..f6282bf04c --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt new file mode 100644 index 0000000000..856d016914 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt new file mode 100644 index 0000000000..26c06b6f40 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt @@ -0,0 +1,3 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb new file mode 100644 index 0000000000..86208829a5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #| I2C5 | P-Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.3 off end #I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 8d958493bd..d351d85b96 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -22,8 +22,6 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR if BOARD_GOOGLE_BASEBOARD_DELTAUR config CHROMEOS - bool - default y select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 47758d4df1..7a74843493 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -30,9 +30,6 @@ DefinitionBlock( } } - /* VPD support */ - #include <vendorcode/google/chromeos/acpi/vpd.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 747010702c..311f3f6c0b 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -28,8 +28,6 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION if BOARD_GOOGLE_BASEBOARD_DRALLION config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2de104e543..5556c989bb 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -31,11 +31,6 @@ DefinitionBlock( #include <variant/acpi/mainboard.asl> } -#if CONFIG(CHROMEOS) - /* VPD support */ - #include <vendorcode/google/chromeos/acpi/vpd.asl> -#endif - #include <southbridge/intel/common/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 384e44bb57..ceba219ecf 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index b9f2830541..5ea04856bf 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index ab7bc8cf48..7d29df87f4 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -4,7 +4,6 @@ #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> -#include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) { diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index cd55c93a40..bc4fc933be 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <gpio.h> @@ -31,10 +30,9 @@ static void mainboard_init(struct device *dev) setup_mmu(DRAM_INITIALIZED); setup_usb(); - if (CONFIG(CHROMEOS)) { - /* Copy WIFI calibration data into CBMEM. */ + /* Copy WIFI calibration data into CBMEM. */ + if (CONFIG(CHROMEOS)) cbmem_add_vpd_calibration_data(); - } /* * Make sure bootloader can issue sounds The frequency is calculated diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index dd4c1516b1..d7a30b0d11 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -5,5 +5,9 @@ void bootblock_mainboard_early_init(void) { - /* TODO: Perform mainboard initialization */ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_bootblock_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 3dc2c41d69..f4466d1bde 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -1,10 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/variants.h> #include <device/device.h> +static void mainboard_configure_gpios(void) +{ + size_t base_num_gpios, override_num_gpios; + const struct soc_amd_gpio *base_gpios, *override_gpios; + + base_gpios = variant_base_gpio_table(&base_num_gpios); + override_gpios = variant_override_gpio_table(&override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, + override_num_gpios); +} + static void mainboard_init(void *chip_info) { - /* TODO: Perform mainboard initialization */ + mainboard_configure_gpios(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..9fb63f5f43 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c new file mode 100644 index 0000000000..b7d66a37cf --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* GPIO configuration in ramstage*/ +static const struct soc_amd_gpio base_gpio_table[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WAKE_L */ + PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* AGPIO3 */ + PAD_NC(GPIO_3), + /* AGPIO4 */ + PAD_NC(GPIO_4), + /* AGPIO5 */ + PAD_NC(GPIO_5), + /* AGPIO6 */ + PAD_NC(GPIO_6), + /* AGPIO7 */ + PAD_NC(GPIO_7), + /* AGPIO8 */ + PAD_NC(GPIO_8), + /* AGPIO9 */ + PAD_NC(GPIO_9), + /* S0A3 */ + PAD_NF(GPIO_10, S0A3, PULL_NONE), + /* AGPIO11 */ + PAD_NC(GPIO_11), + /* AGPIO12 */ + PAD_NC(GPIO_12), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* AGPIO17 */ + PAD_NC(GPIO_17), + /* AGPIO18 */ + PAD_NC(GPIO_18), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* AGPIO21 */ + PAD_NC(GPIO_21), + /* AGPIO22 */ + PAD_NC(GPIO_22), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* AGPIO24 */ + PAD_NC(GPIO_24), + /* GPIO_25: Not available */ + /* PCIE_RST0_L */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* GPIO_28: Not available */ + /* AGPIO29 */ + PAD_NC(GPIO_29), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* SPI_CS3_L */ + PAD_NF(GPIO_31, SPI_CS3_L, PULL_NONE), + /* AGPIO32 */ + PAD_NC(GPIO_32), + /* GPIO_33 - GPIO_39: Not available */ + /* AGPIO40 */ + PAD_NC(GPIO_40), + /* GPIO_41: Not available */ + /* EGPIO42 */ + PAD_NC(GPIO_42), + /* GPIO_43 - GPIO_66: Not available */ + /* EGPIO67 */ + PAD_NC(GPIO_67), + /* AGPIO68 */ + PAD_NC(GPIO_68), + /* AGPIO69 */ + PAD_NC(GPIO_69), + /* EGPIO70 */ + PAD_NC(GPIO_70), + /* GPIO_71 - GPIO_73: Not available */ + /* EGPIO74 */ + PAD_NC(GPIO_74), + /* EGPIO75 */ + PAD_NC(GPIO_75), + /* EGPIO76 */ + PAD_NC(GPIO_76), + /* GPIO_77 - GPIO_83: Not available */ + /* AGPIO84 */ + PAD_NC(GPIO_84), + /* AGPIO85 */ + PAD_NC(GPIO_85), + /* SPI_CLK2 */ + PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), + /* AGPIO87 */ + PAD_NC(GPIO_87), + /* AGPIO88 */ + PAD_NC(GPIO_88), + /* AGPIO89 */ + PAD_NC(GPIO_89), + /* AGPIO90 */ + PAD_NC(GPIO_90), + /* AGPIO91 */ + PAD_NC(GPIO_91), + /* CLK_REQ0_L */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), + /* EGPIO109 */ + PAD_NC(GPIO_109), + /* GPIO_110 - GPIO_112: Not available */ + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_119: Not available */ + /* EGPIO120 */ + PAD_NC(GPIO_120), + /* EGPIO121 */ + PAD_NC(GPIO_121), + /* GPIO_122 - GPIO_128: Not available */ + /* AGPIO129 */ + PAD_NC(GPIO_129), + /* AGPIO130 */ + PAD_NC(GPIO_130), + /* CLK_REQ3_L */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), + /* EGPIO132 */ + PAD_NC(GPIO_132), + /* UART1_TXD */ + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART1_RXD */ + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* AGPIO144 */ + PAD_NC(GPIO_144), + /* I2C0_SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0_SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1_SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1_SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), +}; + +/* Early GPIO configuration in bootblock */ +static const struct soc_amd_gpio bootblock_gpio_table[] = { + /* TODO: Fill bootblock gpio configuration */ +}; + +const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(base_gpio_table); + return base_gpio_table; +} +const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size) +{ + *size = 0; + return NULL; +} + +const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(bootblock_gpio_table); + return bootblock_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 927af2f913..2946463f4b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -3,4 +3,22 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ +#include <amdblocks/gpio_banks.h> + +/* + * This function provides base GPIO configuration table. It is typically provided by + * baseboard using a weak implementation. If GPIO configuration for a variant differs + * significantly from the baseboard, then the variant can also provide a strong implementation + * of this function. + */ +const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); +/* + * This function allows variant to override any GPIOs that are different than the base GPIO + * configuration provided by variant_base_gpio_table(). + */ +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); + +/* This function provides GPIO init in bootblock. */ +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d088341324..1c10522455 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -45,8 +45,6 @@ config BOARD_GOOGLE_HATCH_COMMON if BOARD_GOOGLE_HATCH_COMMON config CHROMEOS - bool - default y select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index e697379965..3d84e52448 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -28,10 +28,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) printk(BIOS_WARNING, "Invalid SPD cache\n"); } else { dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { + if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != 0) { /* Set mrc_cache as invalid */ printk(BIOS_INFO, "Set mrc_cache as invalid\n"); - memupd->FspmArchUpd.NvsBufferPtr = NULL; + memupd->FspmArchUpd.NvsBufferPtr = 0; } } need_update_cache = true; diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 7cc920d7ee..b4f3609ba0 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -213,15 +213,14 @@ chip soc/intel/cannonlake ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1, - .thresholds={TEMP_PCT(70, 100), - TEMP_PCT(66, 90), - TEMP_PCT(62, 80), - TEMP_PCT(58, 70), - TEMP_PCT(53, 60), - TEMP_PCT(48, 50), - TEMP_PCT(43, 40), - TEMP_PCT(38, 30),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(72, 90), + TEMP_PCT(68, 80), + TEMP_PCT(64, 70), + TEMP_PCT(58, 60), + TEMP_PCT(51, 50), + TEMP_PCT(42, 40), + TEMP_PCT(35, 30),}}" ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index 5b802033b6..f2a3a78aa7 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -2,7 +2,6 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> -#include <boardid.h> #include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index ec9ae3af86..349fe34068 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -2,7 +2,6 @@ #include <chip.h> #include <amdblocks/agesawrapper.h> -#include <boardid.h> #include <gpio.h> #include <console/console.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 4b50d4909d..79fd4784af 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,6 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> -#include <boardid.h> #include <chip.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 8628074837..22d8bb8448 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <boardid.h> #include <variant/gpio.h> /* diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 866456071f..d3d81fde36 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -2,7 +2,7 @@ #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> /* src/include/gpio.h */ +#include <gpio.h> #include <spd_bin.h> #include <variant/gpio.h> #include <amdblocks/dimm_spd.h> diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c index ab13735344..3c551a2d34 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -20,7 +20,8 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { }, .orientation = LB_FB_ORIENTATION_LEFT_UP, .init = { - INIT_DELAY_CMD(24), + INIT_DCS_CMD(0x10), + INIT_DELAY_CMD(34), INIT_DCS_CMD(0xB0, 0x05), INIT_DCS_CMD(0xB1, 0xE5), INIT_DCS_CMD(0xB3, 0x52), @@ -33,9 +34,9 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xBA, 0x87), INIT_DCS_CMD(0xBF, 0x1F), INIT_DCS_CMD(0xC0, 0x0F), - INIT_DCS_CMD(0xC2, 0x0C), + INIT_DCS_CMD(0xC2, 0x0E), INIT_DCS_CMD(0xC3, 0x02), - INIT_DCS_CMD(0xC4, 0x0C), + INIT_DCS_CMD(0xC4, 0x0A), INIT_DCS_CMD(0xC5, 0x02), INIT_DCS_CMD(0xB0, 0x01), INIT_DCS_CMD(0xE0, 0x26), @@ -305,11 +306,16 @@ struct panel_serializable_data BOE_TV105WUM_NW0 = { INIT_DCS_CMD(0xCC, 0xAF), INIT_DCS_CMD(0xCD, 0xFF), INIT_DCS_CMD(0xCE, 0xFF), + INIT_DELAY_CMD(100), INIT_DCS_CMD(0xB0, 0x00), INIT_DCS_CMD(0xB3, 0x08), INIT_DCS_CMD(0xB0, 0x04), INIT_DCS_CMD(0xB8, 0x68), - INIT_DELAY_CMD(150), + INIT_DELAY_CMD(10), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(100), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(50), INIT_END_CMD, }, }; diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index f00bec82c8..d0b52458f8 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -30,7 +30,9 @@ static const char *const sdram_configs[] = { [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x15] = "sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB", [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + [0x17] = "sdram-lpddr4x-MT53E1G32D2NP-046-4GB", /* Table shared by Kakadu and its variants, offset = 0x20 */ [0x20] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e0cd75d8c3..4079182497 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -19,10 +19,9 @@ static void setup_usb(void) static void mainboard_init(struct device *dev) { - if (CONFIG(CHROMEOS)) { - /* Copy WIFI calibration data into CBMEM. */ + /* Copy WIFI calibration data into CBMEM. */ + if (CONFIG(CHROMEOS)) cbmem_add_vpd_calibration_data(); - } setup_usb(); } diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index d01c51373e..599907e1da 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index d01c51373e..599907e1da 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 7e8e277e17..ba01fe3d5f 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -43,8 +43,6 @@ config BASEBOARD_OCTOPUS_LAPTOP select SYSTEM_TYPE_LAPTOP config CHROMEOS - bool - default y select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 9c8e2a6abb..ea488ad90d 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 1a8a37164a..635d721110 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <sar.h> #include <baseboard/variants.h> #include <delay.h> diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 8148dcef2d..6dbc74a303 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c index e813fb122e..089b28a4cd 100644 --- a/src/mainboard/google/octopus/variants/lick/gpio.c +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 444234af45..9893acfb78 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -31,8 +31,6 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN if BOARD_GOOGLE_BASEBOARD_SARIEN config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 12e08be4c0..6bc69efbc9 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -12,7 +12,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 027fa08f8a..fd91f64859 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -31,11 +31,6 @@ DefinitionBlock( #include <variant/acpi/mainboard.asl> } -#if CONFIG(CHROMEOS) - /* VPD support */ - #include <vendorcode/google/chromeos/acpi/vpd.asl> -#endif - #include <southbridge/intel/common/acpi/sleepstates.asl> #if CONFIG(EC_GOOGLE_WILCO) diff --git a/src/mainboard/google/sarien/hda_verb.c b/src/mainboard/google/sarien/hda_verb.c deleted file mode 100644 index c26029774e..0000000000 --- a/src/mainboard/google/sarien/hda_verb.c +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "variant/hda_verb.h" diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/arcada/hda_verb.c index 83acbc2857..b447e9f25b 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/arcada/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - #include <device/azalia_device.h> const u32 cim_verb_data[] = { @@ -192,5 +189,3 @@ const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/hda_verb.c index 5ec53ed112..316b110137 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - #include <device/azalia_device.h> const u32 cim_verb_data[] = { @@ -135,5 +132,3 @@ const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 66440227e2..26a7e90d5e 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 6a89be04df..4faf8329bc 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -76,10 +76,9 @@ static void mainboard_init(struct device *dev) /* Functionally a 0-cost no-op if NAND is not present */ board_nand_init(); -#if CONFIG(CHROMEOS) /* Copy WIFI calibration data into CBMEM. */ - cbmem_add_vpd_calibration_data(); -#endif + if (CONFIG(CHROMEOS)) + cbmem_add_vpd_calibration_data(); /* * Make sure bootloader can issue sounds The frequency is calculated diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 3217d07f71..f4d121ed3d 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -38,8 +38,6 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER if BOARD_GOOGLE_BASEBOARD_VOLTEER config CHROMEOS - bool - default y select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index d74476af16..ccde132176 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -58,6 +58,10 @@ fw_config option BOOT_SATA_DISABLED 0 option BOOT_SATA_ENABLED 1 end + field TOUCHPAD 25 + option REGULAR_TOUCHPAD 0 + option NUMPAD_TOUCHPAD 1 + end end chip soc/intel/tigerlake diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index d4e07460a2..1192129238 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -97,14 +97,26 @@ chip soc/intel/tigerlake end end device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on + probe TOUCHPAD REGULAR_TOUCHPAD + end + end chip drivers/i2c/hid - register "generic.hid" = ""ELAN0000"" + register "generic.hid" = ""ELAN2701"" register "generic.desc" = ""ELAN Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" register "generic.wake" = "GPE0_DW2_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end + device i2c 15 on + probe TOUCHPAD NUMPAD_TOUCHPAD + end end end device ref pch_espi on diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 96c109fbb5..608535e834 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -21,6 +21,9 @@ chip soc/intel/tigerlake .tdp_pl4 = 105, }" + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # Type-C port 0 + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -56,10 +59,24 @@ chip soc/intel/tigerlake }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 155, + .scl_hcnt = 80, + .sda_hold = 36, + }, }, }" device domain 0 on + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN3 + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -164,7 +181,7 @@ chip soc/intel/tigerlake device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref tcss_usb3_port2 on @@ -178,13 +195,13 @@ chip soc/intel/tigerlake chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port4 on @@ -209,7 +226,7 @@ chip soc/intel/tigerlake device ref usb2_port10 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb3_port1 on end diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 37e0ab9efc..6760361355 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -3,10 +3,12 @@ chip soc/intel/tigerlake register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 51, + .tdp_pl4 = 71, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 51, + .tdp_pl4 = 105, }" register "tcc_offset" = "5" # TCC of 95 @@ -98,27 +100,27 @@ chip soc/intel/tigerlake register "policies.active" = "{[0] = {.target=DPTF_NONE}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,87,5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60.8,6000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,75,SHUTDOWN)" ## Power Limits Control - # 3-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is fixed at 51W, avg over 28-32s interval + # 3-15W PL1 in 200mW increments, avg over 26-34s interval + # PL2 is fixed at 51W, avg over 26-34s interval register "controls.power_limits" = "{ .pl1 = {.min_power = 3000, .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}, + .time_window_min = 26 * MSECS_PER_SEC, + .time_window_max = 34 * MSECS_PER_SEC, + .granularity = 250,}, .pl2 = {.min_power = 51000, .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}}" + .time_window_min = 26 * MSECS_PER_SEC, + .time_window_max = 34 * MSECS_PER_SEC, + .granularity = 250,}}" device generic 0 on end end diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl index 53f5d03783..4ef83fd33d 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -271,4 +271,70 @@ Scope (\_SB.PCI0.I2C2) } }) } + Device (NVM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_DDN, "AT24 EEPROM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0050, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM1 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x06) + { + Package (0x02) + { + "size", + 0x2000 + }, + Package (0x02) + { + "pagesize", + One + }, + Package (0x02) + { + "read-only", + One + }, + Package (0x02) + { + "address-width", + 0x10 + }, + Package (0x02) + { + "compatible", + "atmel,24c64" + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } + } + }) + } } diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 4fce3b8616..fe22650925 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -46,6 +46,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select DRIVERS_USB_ACPI select DRIVERS_UART_ACPI + select DRIVERS_GENERIC_BAYHUB_LV2 config ELOG_BOOT_COUNT_CMOS_OFFSET int diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 1de593ed49..1558245773 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -2,7 +2,6 @@ #include <string.h> #include <console/console.h> -#include <cbfs.h> #include <device/device.h> #include <device/mmio.h> #include <acpi/acpi.h> @@ -26,7 +25,6 @@ #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> #include <commonlib/helpers.h> -#include <bootstate.h> #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index e014ce302c..9b0dd9a855 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -134,6 +134,47 @@ chip soc/amd/picasso .tx_res_tune = 0x01, }" + # Start RV2 USB3 PHY Parameters + register "usb3_phy_override" = "0" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port1 Default + register "usb3_phy_tune_params[1]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port2 Default + register "usb3_phy_tune_params[2]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port3 Default + register "usb3_phy_tune_params[3]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x00" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x00" + + # End RV2 USB3 phy setting + # USB OC pin mapping register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 5ec9010680..a3c4573ce5 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -134,6 +134,47 @@ chip soc/amd/picasso .tx_res_tune = 0x01, }" + # Start RV2 USB3 PHY Parameters + register "usb3_phy_override" = "0" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port1 Default + register "usb3_phy_tune_params[1]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port2 Default + register "usb3_phy_tune_params[2]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port3 Default + register "usb3_phy_tune_params[3]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x00" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x00" + + # End RV2 USB3 phy setting + # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_33M, /* MHz */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 0b658a4129..948ce8f9d4 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio early_gpio_table[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 12d2890ce2..473ffb10cb 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a2ad51755f..341357e8cd 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -8,7 +8,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index ae2d02a48d..2452a1defe 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 2b46938e9b..a71aa78f02 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 7f9582c9b6..aeebd0707b 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 554cdeac94..0e50d2f70c 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -70,8 +70,8 @@ chip soc/amd/picasso # I2C3 for H1 register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 42, /* 1.26v to 0 */ + .rise_time_ns = 98, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 17, /* 1.26v to 0 */ .early_init = true, }" diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index f86d926e2e..295fb21de2 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/gumboz/gpio.c b/src/mainboard/google/zork/variants/gumboz/gpio.c index aac25bb353..501c14402e 100644 --- a/src/mainboard/google/zork/variants/gumboz/gpio.c +++ b/src/mainboard/google/zork/variants/gumboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 9b36e3747e..778c6e4407 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c index 0fd867e8d4..db20e44699 100644 --- a/src/mainboard/google/zork/variants/shuboz/gpio.c +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 4d73ea0122..0546df4ae2 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index c6ef161647..5c918fddde 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index c3afe1372a..56b7972421 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -24,7 +24,17 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "168" # eDP phy tuning settings - register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + register "edp_phy_override" = "ENABLE_EDP_TUNINGSET" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .margin_deemph = 0x004b, + .deemph_6db4 = 0x0, + .boostadj = 0x80, + }" # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, # and "0" as default value @@ -38,13 +48,6 @@ chip soc/amd/picasso register "pwrdown_bloff_to_varybloff" = "5" register "min_allowed_bl_level" = "0" - register "edp_tuningset" = "{ - .dp_vs_pemph_level = 0x0, - .deemph_6db4 = 0x004b, - .boostadj = 0x0, - .margin_deemph = 0x80, - }" - # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 @@ -72,6 +75,12 @@ chip soc/amd/picasso # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + device pci 1.3 on + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end # GPP Bridge 2 - SD device pci 8.1 on device pci 0.5 on chip drivers/amd/i2s_machine_dev diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 15d6ee8476..95c7823cec 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -16,9 +16,9 @@ chip soc/amd/picasso register "stapm_time_constant_s" = "200" register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope_mA" = "101070" + register "telemetry_vddcr_vdd_slope_mA" = "102586" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope_mA" = "24560" + register "telemetry_vddcr_soc_slope_mA" = "24674" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 35224a14ce..80d52548fb 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -18,8 +18,6 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_HOTPLUG config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 0dd1456d42..eb7be69ca1 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,49 +40,58 @@ chip soc/intel/alderlake register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 2 - register "PchPcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcUsage[2]" = "0x4" - register "PcieRpClkReqDetect[4]" = "1" + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" # Enable PCH PCIE RP 6 using CLK 5 - register "PchPcieRpEnable[5]" = "1" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcUsage[5]" = "0x5" - register "PcieRpClkReqDetect[5]" = "1" + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" - # Enable PCH PCIE RP 8 using CLK 6 - register "PchPcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK + # Enable PCH PCIE RP 8 using free running CLK (0x80) + # Clock source is shared with LAN and hence marked as free running. + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" # Enable PCH PCIE RP 9 using CLK 1 - register "PchPcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcUsage[1]" = "0x8" - register "PcieRpClkReqDetect[8]" = "1" + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" # Enable PCH PCIE RP 11 for optane - register "PchPcieRpEnable[10]" = "1" + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + # Hybrid storage mode register "HybridStorageMode" = "1" # Enable CPU PCIE RP 1 using CLK 0 - register "CpuPcieRpEnable[0]" = "1" - register "PcieClkSrcUsage[0]" = "0x40" + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" # Enable CPU PCIE RP 2 using CLK 3 - register "CpuPcieRpEnable[1]" = "1" - register "PcieClkSrcUsage[3]" = "0x41" + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_req = 3, + .clk_src = 3, + }" # Enable CPU PCIE RP 3 using CLK 4 - register "CpuPcieRpEnable[2]" = "1" - register "PcieClkSrcUsage[4]" = "0x42" - - # W/A to FSP issue where FSP is using PCH PCIE port - # enable UPD to download FW on CPU PCIE - register "PchPcieRpEnable[0]" = "1" - register "PchPcieRpEnable[2]" = "1" - register "PchPcieRpEnable[3]" = "1" + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_req = 4, + .clk_src = 4, + }" register "SataSalpSupport" = "1" diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 50ba1b3c05..5b02e78cf8 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include <assert.h> #include <console/console.h> #include <fsp/api.h> @@ -7,7 +8,6 @@ #include <string.h> #include <soc/meminit.h> #include <baseboard/variants.h> -#include <cbfs.h> #include "board_id.h" #define SPD_ID_MASK 0x7 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 0f8075bf4f..e4c2d90a95 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -44,9 +44,6 @@ config MAINBOARD_FAMILY default "Intel_cflrvp" config CHROMEOS - bool - default n if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 - default y select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAX_CPUS diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 172dfa2e97..7fda90d98a 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -38,8 +38,6 @@ config GLK_INTEL_EC endchoice config CHROMEOS - bool - default y select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH if GLK_CHROME_EC diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index f1e544cfa8..868a4c6757 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> #include <baseboard/variants.h> -#include <boardid.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 7bfd15878c..8dec42a2a8 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -51,8 +51,6 @@ config DIMM_SPD_SIZE default 512 config CHROMEOS - bool - default y select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index a822bcc350..66ae63672e 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -3,9 +3,39 @@ if BOARD_INTEL_SHADOWMOUNTAIN config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_PMC + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_ALDERLAKE +config CHROMEOS + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + +config DIMM_SPD_SIZE + int + default 512 + config DEVICETREE string default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/intel/shadowmountain/Makefile.inc b/src/mainboard/intel/shadowmountain/Makefile.inc new file mode 100644 index 0000000000..bc2be438d0 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Makefile.inc @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/shadowmountain/bootblock.c b/src/mainboard/intel/shadowmountain/bootblock.c new file mode 100644 index 0000000000..98f58bc6a1 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpio_pads(); +} diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c new file mode 100644 index 0000000000..35a54a8aca --- /dev/null +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..a084537cb9 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += early_gpio.c diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index fbd7d72f9f..1b3e37537b 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -1,5 +1,101 @@ chip soc/intel/alderlake + device cpu_cluster 0 on device lapic 0 on end end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_C" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end + device pci 0d.3 on end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + device pci 14.3 on end # CNVi: WiFi + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 off end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 off end # UART2 + device pci 1c.0 off end # RP1 + device pci 1c.1 off end # RP2 + device pci 1c.2 off end # RP3 + device pci 1c.3 off end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 off end # RP6 + device pci 1c.6 off end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 off end # RP10 + device pci 1d.2 off end # RP11 + device pci 1d.3 off end # RP12 + device pci 1e.0 on end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + end end diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c new file mode 100644 index 0000000000..29e6184447 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* A7 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A17 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A19 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_A19, NONE, DEEP), + /* A20 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_A20, NONE, DEEP), + /* B11 : PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* C0 : EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT), + + /* D10 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + + /* E10 : PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), + /* E11 : PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), + /* E12 : PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), + /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), + + /* F14 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F20 : WWAN_RST_ODL + To meet timing constraints - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), +}; + +void variant_configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..470a5d9e47 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_A8 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_B11 + +/* EC wake is LAN_WAKE# */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_C6_IRQ + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..dbd0e67887 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stddef.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +void variant_configure_early_gpio_pads(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a600d0a15b..9f8187fcf2 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -8,7 +8,6 @@ #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/device_nvs.h> -#include <boardid.h> #include "onboard.h" void mainboard_fill_gnvs(struct global_nvs *gnvs) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index d3d6168d15..0e7f88c2ef 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -2,7 +2,6 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <boardid.h> #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index eac843d903..e7ed500497 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include <boardid.h> #include "onboard.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0bb4476075..331db041f3 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -2,7 +2,6 @@ #include <soc/romstage.h> #include "onboard.h" -#include <boardid.h> void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 9df542dfa6..233706d949 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -26,8 +26,6 @@ config BOARD_SPECIFIC_OPTIONS select SPI_TPM config CHROMEOS - bool - default y select EC_GOOGLE_CHROMEEC_SWITCHES if TGL_CHROME_EC select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index fb8e6ef877..e80cc1221f 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <delay.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ +#include <OEM.h> #include <Porting.h> #include <AGESA.h> diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 40810b6364..dc70eb23b2 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -2,7 +2,6 @@ #include <assert.h> #include <console/console.h> -#include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index d7ecdeca48..bff834036a 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -2,12 +2,17 @@ #include <device/pci_ops.h> #include <console/console.h> +#include <crc_byte.h> #include <device/smbus_host.h> #include <soc/intel/common/block/smbus/smbuslib.h> +#include <types.h> + #include "variants/baseboard/include/eeprom.h" #define I2C_ADDR_EEPROM 0x57 +#define EEPROM_OFFSET_BOARD_SETTINGS 0x1f00 + /* * Check Signature in EEPROM (M24C32-FMN6TP) * If signature is there we assume that that the content is valid @@ -28,6 +33,41 @@ int check_signature(const size_t offset, const uint64_t signature) return 0; } +/* + * Read board settings from the EEPROM and verify their checksum. + * If checksum is valid, we assume the settings are sane as well. + */ +static bool get_board_settings_from_eeprom(struct eeprom_board_settings *board_cfg) +{ + if (read_write_config(board_cfg, EEPROM_OFFSET_BOARD_SETTINGS, 0, sizeof(*board_cfg))) { + printk(BIOS_ERR, "CFG EEPROM: Failed to read board settings\n"); + return false; + } + + const uint32_t crc = + CRC(&board_cfg->raw_settings, sizeof(board_cfg->raw_settings), crc32_byte); + + if (crc != board_cfg->signature) { + printk(BIOS_ERR, "CFG EEPROM: Board settings have invalid checksum\n"); + return false; + } + return true; +} + +struct eeprom_board_settings *get_board_settings(void) +{ + static struct eeprom_board_settings board_cfg = {0}; + + /* Tri-state: -1: settings are invalid, 0: uninitialized, 1: settings are valid */ + static int checked_valid = 0; + + if (checked_valid == 0) { + const bool success = get_board_settings_from_eeprom(&board_cfg); + checked_valid = success ? 1 : -1; + } + return checked_valid > 0 ? &board_cfg : NULL; +} + /* Read data from offset and write it to offset in UPD */ bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size) { diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b24dd566f9..f2bbbba46c 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,6 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen.h> #include <device/device.h> +#include <intelblocks/pmclib.h> +#include <string.h> +#include <types.h> +#include "variants/baseboard/include/eeprom.h" #include "gpio.h" /* FIXME: Example code below */ @@ -65,6 +70,66 @@ static void mb_usb2_fp2_pwr_enable(bool enable) gpio_output(GPP_G4, enable); } +static void mainboard_init(void *chip_info) +{ + const struct eeprom_board_settings *const board_cfg = get_board_settings(); + + if (!board_cfg) + return; + + config_t *config = config_of_soc(); + config->deep_s5_enable_ac = board_cfg->deep_sx_enabled; + config->deep_s5_enable_dc = board_cfg->deep_sx_enabled; +} + +static void mainboard_final(struct device *dev) +{ + const struct eeprom_board_settings *const board_cfg = get_board_settings(); + + if (!board_cfg) + return; + + /* Encoding: 0 -> S0, 1 -> S5 */ + const bool on = !board_cfg->power_state_after_g3; + + pmc_soc_set_afterg3_en(on); +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void mainboard_acpi_fill_ssdt(const struct device *dev) +{ + const struct eeprom_board_settings *const board_cfg = get_board_settings(); + + if (!board_cfg) + return; + + const unsigned int usb_power_gpios[] = { GPP_G0, GPP_G1, GPP_G2, GPP_G3, GPP_G4 }; + + /* Function pointer to write STXS or CTXS according to EEPROM board setting */ + int (*acpigen_write_soc_gpio_op)(unsigned int gpio_num); + + if (board_cfg->usb_powered_in_s5) + acpigen_write_soc_gpio_op = acpigen_soc_set_tx_gpio; + else + acpigen_write_soc_gpio_op = acpigen_soc_clear_tx_gpio; + + acpigen_write_scope("\\_SB"); + { + acpigen_write_method("MPTS", 1); + { + acpigen_write_if_lequal_op_int(ARG0_OP, 5); + { + for (size_t i = 0; i < ARRAY_SIZE(usb_power_gpios); i++) + acpigen_write_soc_gpio_op(usb_power_gpios[i]); + } + acpigen_pop_len(); + } + acpigen_pop_len(); + } + acpigen_pop_len(); +} +#endif + static void mainboard_enable(struct device *dev) { /* FIXME: Do runtime configuration once the board is production ready */ @@ -82,8 +147,15 @@ static void mainboard_enable(struct device *dev) mb_usb31_fp_pwr_enable(1); mb_usb2_fp1_pwr_enable(1); mb_usb2_fp2_pwr_enable(1); + + dev->ops->final = mainboard_final; + +#if CONFIG(HAVE_ACPI_TABLES) + dev->ops->acpi_fill_ssdt = mainboard_acpi_fill_ssdt; +#endif } struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index 95024b6ccd..d5a79cd9f9 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -18,6 +18,24 @@ .size = member_size(FSP_S_CONFIG, x)} #endif /* ENV_ROMSTAGE */ +__packed struct eeprom_board_settings { + uint32_t signature; + union { + struct { + uint8_t secureboot; + uint8_t primary_video; + uint8_t deep_sx_enabled; + uint8_t wake_on_usb; + uint8_t usb_powered_in_s5; + uint8_t power_state_after_g3; + uint8_t blue_rear_vref; + uint8_t internal_audio_connection; + uint8_t pxe_boot_capability; + }; + uint8_t raw_settings[9]; + }; +}; + typedef struct { size_t offset; size_t size; @@ -25,3 +43,4 @@ typedef struct { bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size); int check_signature(const size_t offset, const uint64_t signature); +struct eeprom_board_settings *get_board_settings(void); diff --git a/src/mainboard/purism/librem_cnl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c index fd3154f431..5d92316d21 100644 --- a/src/mainboard/purism/librem_cnl/romstage.c +++ b/src/mainboard/purism/librem_cnl/romstage.c @@ -59,10 +59,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) printk(BIOS_WARNING, "Invalid SPD cache\n"); } else { dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { + if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != 0) { /* Set mrc_cache as invalid */ printk(BIOS_INFO, "Set mrc_cache as invalid\n"); - memupd->FspmArchUpd.NvsBufferPtr = NULL; + memupd->FspmArchUpd.NvsBufferPtr = 0; } } need_update_cache = true; diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 3ce84a46f6..d43e6a1e2f 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -2,7 +2,7 @@ #include <device/pci_def.h> #include <device/device.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ +#include <OEM.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 7f642194ba..fc73f24e4f 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -3,7 +3,6 @@ #include "hostbridge.asl" #include "../memmap.h" #include <southbridge/intel/i82801ix/i82801ix.h> -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -14,7 +13,7 @@ Device (PDRC) // This does not seem to work correctly yet - set values statically for // now. Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index e2cabdb166..a9a1e8eb2d 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "gm45.h" diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index fd7ce527a1..f2c0090ed5 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -264,7 +264,7 @@ static void setup_rcrb(const int peg_enabled) /* Link1: target port 0, component id 2 (ICH), link valid. */ DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 28b7551e81..dcc9162fd0 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -90,15 +90,6 @@ config HASWELL_HIDE_PEG_FROM_MRC However, it prevents MRC from programming PEG AFE registers, which can make PEG devices unstable. When unsure, choose N. -config PRE_GRAPHICS_DELAY - int "Graphics initialization delay in ms" - default 0 - help - On some systems, coreboot boots so fast that connected monitors - (mostly TVs) won't be able to wake up fast enough to talk to the - VBIOS. On those systems we need to wait for a bit before executing - the VBIOS. - # The UEFI System Agent binary needs to be at a fixed offset in the flash # and can therefore only reside in the COREBOOT fmap region config RO_REGION_ONLY diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9a39647c06..1ff2826ca4 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "../haswell.h" -#include <southbridge/intel/common/rcba.h> Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -175,7 +174,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 0bb8ae2aad..1336582889 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 3746fe35cc..e69cfec6de 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -444,7 +444,6 @@ static void gma_func0_init(struct device *dev) if (!lightup_ok) { printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); - mdelay(CONFIG_PRE_GRAPHICS_DELAY); pci_dev_init(dev); } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8af6eb27f0..c2c8143be7 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -511,7 +511,7 @@ static void northbridge_topology_init(void) reg32 &= ~(0xffff << 16); reg32 |= 1 | (2 << 16); DMIBAR32(DMILE1D) = reg32; - DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; reg32 = DMIBAR32(DMILE2D); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 3227c02287..f5d500b2fb 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -56,7 +56,7 @@ void mainboard_romstage_entry(void) .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, + .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 11d3b505ee..349234b1fa 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../i945.h" -#include <southbridge/intel/common/rcba.h> /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -38,7 +37,7 @@ Device (PDRC) //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index edb9a8d4d0..448d5e411a 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b72b..4564ff4bbb 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -730,7 +730,7 @@ static void i945_setup_root_complex_topology(void) reg32 |= (1 << 0); DMIBAR32(DMILE1D) = reg32; - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 73242e4503..31af469345 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -2,7 +2,6 @@ #include "../ironlake.h" #include "hostbridge.asl" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 02b63a64b3..6610a3e38c 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "ironlake.h" diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4620c4f541..7db1d372ac 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -13,7 +12,7 @@ Device (PDRC) /* This does not seem to work correctly yet - set values statically for now. */ Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 1e47c1f21b..5d7a777803 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "peg.asl" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) // Filled by _CRS Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 92f9aeee49..1eba74438c 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 33cb7ad641..9eed44ecff 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index aedcdd9089..f15d181354 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -2,8 +2,8 @@ #include <arch/bootblock.h> #include <arch/mmio.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "x4x.h" diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index a719bb1774..35e4c410da 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <types.h> #include <pc80/mc146818rtc.h> @@ -86,6 +87,17 @@ void vbnv_init_cmos(uint8_t *vbnv_copy) } } +void lb_table_add_vbnv_cmos(struct lb_header *header) +{ + struct lb_range *vbnv; + + vbnv = (struct lb_range *)lb_new_record(header); + vbnv->tag = LB_TAG_VBNV; + vbnv->size = sizeof(*vbnv); + vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; + vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; +} + #if CONFIG(VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) static void back_up_vbnv_cmos(void *unused) { diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 56a0664328..234ae8f4ad 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -2,7 +2,6 @@ #include <boot_device.h> #include <cbfs.h> -#include <cbmem.h> #include <commonlib/bsd/cbfs_private.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index f853ecee93..5fb4f0ab98 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -1,9 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> +#include <assert.h> +#include <soc/iomap.h> #include <soc/southbridge.h> +static void fch_init_acpi_ports(void) +{ + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* TODO: add code for SMI handler case */ + dead_code(); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + void fch_init(void *chip_info) { + fch_init_acpi_ports(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 189bc9d0d6..277707de1c 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -29,6 +29,7 @@ KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 20f70371f0..b91ff2785b 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,7 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +/* MMIO Ranges */ /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 @@ -11,11 +12,20 @@ #define APU_UART0_BASE 0xfedc9000 #define APU_UART1_BASE 0xfedca000 -/* MMIO Ranges */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) /* I/O Ranges */ #define NCP_ERR 0x00f0 +#define ACPI_IO_BASE 0x0400 +#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) +#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) +#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) #define SMB_BASE_ADDR 0x0b00 #endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 6949fa57b3..8623063140 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -8,7 +8,37 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ @@ -22,9 +52,7 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 /* IO 0xf0 NCP Error */ diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index f790def747..c7e7e5cba4 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -3,11 +3,22 @@ #include <acpi/acpi.h> #include <arch/cpu.h> #include <console/console.h> +#include <console/uart.h> #include <fsp/api.h> #include <program_loading.h> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + + mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; + mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); + mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; + mcfg->serial_port_baudrate = get_uart_baudrate(); + mcfg->serial_port_refclk = uart_platform_refclk(); } asmlinkage void car_stage_entry(void) diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c index a0097185dc..ea22ec564a 100644 --- a/src/soc/amd/common/block/acpi/pm_state.c +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -2,6 +2,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> +#include <amdblocks/acpi.h> #include <bootstate.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -13,7 +14,7 @@ static int get_index_bit(uint32_t value, uint16_t limit) uint16_t i; uint32_t t; - if (limit >= TOTAL_BITS(uint32_t)) + if (limit > TOTAL_BITS(uint32_t)) return -1; /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 5b0111b28f..af948ce357 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -181,16 +181,55 @@ uint16_t gpio_acpi_pin(gpio_t gpio) __weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} -void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +static void set_single_gpio(const struct soc_amd_gpio *g, + struct sci_trigger_regs *sci_trigger_cfg) { - uint32_t control, control_flags; - uint8_t mux, index, gpio; + static const struct soc_amd_event *gev_tbl; + static size_t gev_items; int gevent_num; - const struct soc_amd_event *gev_tbl; + const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && + ENV_SEPARATE_VERSTAGE); + + iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK); + iomux_read8(g->gpio); /* Flush posted write */ + + soc_gpio_hook(g->gpio, g->function); + + gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control); + /* Clear interrupt and wake status (write 1-to-clear bits) */ + gpio_or32(g->gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); + if (g->flags == 0) + return; + + /* Can't set SMI flags from PSP */ + if (!can_set_smi_flags) + return; + + if (gev_tbl == NULL) + soc_get_gpio_event_table(&gev_tbl, &gev_items); + + gevent_num = get_gpio_gevent(g->gpio, gev_tbl, gev_items); + if (gevent_num < 0) { + printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n", + g->gpio); + return; + } + + if (g->flags & GPIO_FLAG_SMI) { + program_smi(g->flags, gevent_num); + } else if (g->flags & GPIO_FLAG_SCI) { + fill_sci_trigger(g->flags, gevent_num, sci_trigger_cfg); + soc_route_sci(gevent_num); + } +} + +void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +{ struct sci_trigger_regs sci_trigger_cfg = { 0 }; - size_t gev_items; const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE); + size_t i; + if (!gpio_list_ptr || !size) return; @@ -206,44 +245,8 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) */ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); - if (can_set_smi_flags) - soc_get_gpio_event_table(&gev_tbl, &gev_items); - - for (index = 0; index < size; index++) { - gpio = gpio_list_ptr[index].gpio; - mux = gpio_list_ptr[index].function; - control = gpio_list_ptr[index].control; - control_flags = gpio_list_ptr[index].flags; - - iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); - iomux_read8(gpio); /* Flush posted write */ - - soc_gpio_hook(gpio, mux); - - gpio_setbits32(gpio, PAD_CFG_MASK, control); - /* Clear interrupt and wake status (write 1-to-clear bits) */ - gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); - if (control_flags == 0) - continue; - - /* Can't set SMI flags from PSP */ - if (!can_set_smi_flags) - continue; - - gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); - if (gevent_num < 0) { - printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n", - gpio); - continue; - } - - if (control_flags & GPIO_FLAG_SMI) { - program_smi(control_flags, gevent_num); - } else if (control_flags & GPIO_FLAG_SCI) { - fill_sci_trigger(control_flags, gevent_num, &sci_trigger_cfg); - soc_route_sci(gevent_num); - } - } + for (i = 0; i < size; i++) + set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg); /* * Re-enable interrupt status generation. diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index e0c0e42190..7f3bea0da7 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 274291de56..9fc73d4e59 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <cbfs.h> -#include <cbmem.h> #include <console/console.h> #include <rmodule.h> #include <stage_cache.h> diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 92b0cc6de3..7c156169a8 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cbfs.h> #include <region_file.h> #include <rules.h> #include <console/console.h> diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4989ee2412..4868d84d3c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -263,12 +263,6 @@ config SERIRQ_CONTINUOUS_MODE Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode. -config PICASSO_ACPI_IO_BASE - hex - default 0x400 - help - Base address for the ACPI registers. - config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index ebb2bcd195..eba9dfee3d 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -94,7 +94,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { const struct soc_amd_picasso_config *cfg = config_of_soc(); - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 244d7831ec..313b6c3abf 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -66,6 +66,13 @@ struct usb_pd_control { }; #define USB_PORT_COUNT 6 + +struct __packed usb3_phy_tune { + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_eq_delta_iq_ovrd_en; +}; +/* the RV2 USB3 port count */ +#define RV2_USB3_PORT_COUNT 4 #define USB_PD_PORT_COUNT 2 enum sd_emmc_driver_strength { @@ -247,13 +254,39 @@ struct soc_amd_picasso_config { USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; + /* RV2 SOC Usb 3.1 PHY Parameters */ + uint8_t usb3_phy_override; + /* + * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF + * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 + */ + struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT]; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F */ + uint8_t usb3_rx_vref_ctrl; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */ + uint8_t usb3_rx_vref_ctrl_en; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */ + uint8_t usb_3_tx_vboost_lvl_en; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/ + uint8_t usb_3_rx_vref_ctrl_x; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */ + uint8_t usb_3_rx_vref_ctrl_en_x; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl_x; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */ + uint8_t usb_3_tx_vboost_lvl_en_x; + /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ bool acp_i2s_use_external_48mhz_osc; /* eDP phy tuning settings */ - uint8_t dp_phy_override; + uint16_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; struct { uint8_t dp_vs_pemph_level; diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index fa99db8334..5d62e8eae9 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -17,6 +17,7 @@ #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> @@ -115,7 +116,7 @@ static void sb_rfmux_config_override(void) } } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -220,7 +221,7 @@ static void gpp_clk_setup(void) void fch_init(void *chip_info) { i2c_soc_init(); - sb_init_acpi_ports(); + fch_init_acpi_ports(); acpi_pm_gpe_add_events_print_events(); gpio_add_events(); diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 731a564416..e77cbde419 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -5,6 +5,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/platform_descriptors.h> +#include <soc/soc_util.h> #include <fsp/api.h> #include "chip.h" @@ -126,6 +127,23 @@ static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, scfg->xhci_oc_pin_select |= (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); } + + if ((get_silicon_type() == SILICON_RV2) && cfg->usb3_phy_override) { + scfg->usb_3_phy_enable = cfg->usb3_phy_override; + for (i = 0; i < FSPS_UPD_RV2_USB3_PORT_COUNT; i++) { + memcpy(scfg->usb_3_port_phy_tune[i], + &cfg->usb3_phy_tune_params[i], + sizeof(scfg->usb_3_port_phy_tune[0])); + } + scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl; + scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en; + scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl; + scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en; + scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x; + scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x; + scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x; + scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x; + } } static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) @@ -145,12 +163,13 @@ static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) { - if (cfg->dp_phy_override & ENABLE_EDP_TUNINGSET) { - scfg->DpPhyOverride = cfg->dp_phy_override; - scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level; - scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph; - scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; - scfg->BoostAdj = cfg->edp_tuningset.boostadj; + if (cfg->edp_phy_override & ENABLE_EDP_TUNINGSET) { + scfg->edp_phy_override = cfg->edp_phy_override; + scfg->edp_physel = cfg->edp_physel; + scfg->edp_dp_vs_pemph_level = cfg->edp_tuningset.dp_vs_pemph_level; + scfg->edp_margin_deemph = cfg->edp_tuningset.margin_deemph; + scfg->edp_deemph_6db_4 = cfg->edp_tuningset.deemph_6db4; + scfg->edp_boost_adj = cfg->edp_tuningset.boostadj; } if (cfg->edp_pwr_adjust_enable) { scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 4ee1dd9056..4dae6b4fa2 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -65,11 +65,11 @@ #define DF_IND_CFG_ACC_REG_SHIFT 2 #define DF_IND_CFG_ACC_REG_MASK (0x1ff << DF_IND_CFG_ACC_REG_SHIFT) #define DF_IND_CFG_ACC_FUN_SHIFT 11 -#define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_FUN_SHIFT) #define DF_IND_CFG_64B_EN_SHIFT 14 -#define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_64B_EN_SHIFT) #define DF_IND_CFG_INST_ID_SHIFT 16 -#define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_INST_ID_SHIFT) void data_fabric_set_mmio_np(void); uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id); diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 0296c87dd8..3d0432b303 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -72,15 +72,15 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_IO_BASE 0x400 +#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ -#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x13) +#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x13) /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ -#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ +#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ #define NCP_ERR 0xf0 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index d45c3b04a7..60fd6f9686 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -75,6 +75,10 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK0_REQ_SHIFT 0 @@ -135,10 +139,6 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ -#define PM1_LIMIT 16 -#define GPE0_LIMIT 28 -#define TOTAL_BITS(a) (8 * sizeof(a)) - /* SATA Controller D11F0 */ #define SATA_MISC_CONTROL_REG 0x40 #define SATA_MISC_SUBCLASS_WREN BIT(0) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index bc514561ac..1391536464 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -92,7 +92,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *mcfg = &mupd->FspmConfig; const struct soc_amd_picasso_config *config = config_of_soc(); - mupd->FspmArchUpd.NvsBufferPtr = soc_fill_mrc_cache(); + mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_mrc_cache(); mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 3db7c42e7f..e316d2166a 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpi.h> #include <amdblocks/biosram.h> #include <device/pci_ops.h> #include <arch/cpu.h> @@ -204,3 +205,15 @@ void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; } } + +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *state; + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + if (state) { + acpi_fill_pm_gpe_state(&state->gpe_state); + acpi_pm_gpe_add_events_print_events(); + } + acpi_clear_pm_gpe_status(); +} +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2a915965bb..c53bcf05a5 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -356,7 +356,7 @@ void sb_enable(struct device *dev) printk(BIOS_DEBUG, "%s\n", __func__); } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -404,17 +404,7 @@ static void sb_init_acpi_ports(void) void fch_init(void *chip_info) { - struct chipset_power_state *state; - - sb_init_acpi_ports(); - - state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); - if (state) { - acpi_fill_pm_gpe_state(&state->gpe_state); - acpi_pm_gpe_add_events_print_events(); - } - - acpi_clear_pm_gpe_status(); + fch_init_acpi_ports(); } static void set_sb_aoac(struct aoac_devs *aoac) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 806c91b334..ec79855074 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -34,12 +34,12 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select INTEL_TME + select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 55ecc006ba..9800563d81 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 0f932ce132..13e77cf534 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -19,10 +19,6 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 -#define PCIE_CLK_NOTUSED 0xFF -#define PCIE_CLK_LAN 0x70 -#define PCIE_CLK_FREE 0x80 - struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -122,31 +118,9 @@ struct soc_intel_alderlake_config { uint8_t PchHdaIDispLinkFrequency; uint8_t PchHdaIDispCodecDisconnect; - /* CPU PCIe Root Ports */ - uint8_t CpuPcieRpEnable[CONFIG_MAX_CPU_ROOT_PORTS]; - - /* PCH PCIe Root Ports */ - uint8_t PchPcieRpEnable[CONFIG_MAX_PCH_ROOT_PORTS]; - uint8_t PcieRpHotPlug[CONFIG_MAX_PCH_ROOT_PORTS]; - /* PCIe output clocks type to PCIe devices. - * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, - * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; - /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to - * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ]; - - /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; - - /* PCIe RP L1 substate */ - enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; - - /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; - - /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ - uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_PCH_ROOT_PORTS]; + struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; + struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; + uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; /* Gfx related */ enum { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 35f7a3c2e2..6e6f1af94f 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -15,6 +15,7 @@ #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> @@ -93,6 +94,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) const struct microcode *microcode_file; size_t microcode_len; FSP_S_CONFIG *params = &supd->FspsConfig; + uint32_t enable_mask; struct device *dev; struct soc_intel_alderlake_config *config; @@ -270,19 +272,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Hybrid storage auto detection */ params->HybridStorageMode = config->HybridStorageMode; + enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { + if (!(enable_mask & BIT(i))) + continue; + const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; params->PcieRpL1Substates[i] = - get_l1_substate_control(config->PcieRpL1Substates[i]); - params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; - params->PcieRpAdvancedErrorReporting[i] = - config->PcieRpAdvancedErrorReporting[i]; - params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + get_l1_substate_control(rp_cfg->PcieRpL1Substates); + params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); + params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); + params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); } - /* Enable ClkReqDetect for enabled port */ - memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, - sizeof(config->PcieRpClkReqDetect)); - params->PmSupport = 1; params->Hwp = 1; params->Cx = 1; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 0154cb4848..385246734e 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -7,20 +7,58 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> +#include <intelblocks/pcie_rp.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> +#define FSP_CLK_NOTUSED 0xFF +#define FSP_CLK_LAN 0x70 +#define FSP_CLK_FREE_RUNNING 0x80 + +#define CPU_PCIE_BASE 0x40 + +enum pcie_rp_type { + PCH_PCIE_RP, + CPU_PCIE_RP, +}; + +static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) +{ + assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP); + + if (type == PCH_PCIE_RP) + return rp_number; + else // type == CPU_PCIE_RP + return CPU_PCIE_BASE + rp_number; +} + +static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type, + const struct pcie_rp_config *cfg, size_t cfg_count) +{ + size_t i; + + for (i = 0; i < cfg_count; i++) { + if (!(en_mask & BIT(i))) + continue; + if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) + continue; + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) + m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - unsigned int i; - uint32_t mask = 0; const struct device *dev; + unsigned int i; dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) @@ -42,18 +80,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set CpuRatio to match existing MSR value */ m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; - for (i = 0; i < ARRAY_SIZE(config->PchPcieRpEnable); i++) { - if (config->PchPcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - - memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, - sizeof(config->PcieClkSrcUsage)); - - memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, - sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ @@ -116,6 +142,27 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { + if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; + else + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; + m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; + } + + /* PCIE ports */ + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, + CONFIG_MAX_PCH_ROOT_PORTS); + + /* CPU PCIE ports */ + m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); + pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, + CONFIG_MAX_CPU_ROOT_PORTS); + /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); m_cfg->PchIshEnable = is_dev_enabled(dev); @@ -156,13 +203,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; - mask = 0; - for (i = 0; i < ARRAY_SIZE(config->CpuPcieRpEnable); i++) { - if (config->CpuPcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->CpuPcieRpEnableMask = mask; - m_cfg->TmeEnable = CONFIG(INTEL_TME); /* Skip GPIO configuration from FSP */ diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 773f56eff2..2c271d26ec 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -9,7 +9,6 @@ #include <arch/smp/mpspec.h> #include <assert.h> #include <device/pci_ops.h> -#include <cbmem.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 5433fdc4c5..153ef04073 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -6,7 +6,6 @@ #include <arch/ioapic.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index cffb2241f0..c73b7a7b3f 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -25,6 +25,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLVL, 8, /* 0x13 - Throttle Level */ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ + GPEI, 32, /* 0x19 - GPE Wake Source */ /* Device Config */ Offset (0x20), diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 9fb0822b9b..a068d1edd4 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -25,7 +25,8 @@ struct __packed global_nvs { u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ - u8 rsvd1[7]; + u32 gpei; /* 0x19 - GPE Wake Source */ + u8 rsvd1[3]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 8cd7336a62..d8623ae06e 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/tsc.h> diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 20254d5564..4b9af49a5c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -141,15 +141,6 @@ config RO_REGION_ONLY endif # HAVE_MRC -config PRE_GRAPHICS_DELAY - int "Graphics initialization delay in ms" - default 0 - help - On some systems, coreboot boots so fast that connected monitors - (mostly TVs) won't be able to wake up fast enough to talk to the - VBIOS. On those systems we need to wait for a bit before executing - the VBIOS. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index b9b3424597..f60ebd8462 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <cpu/intel/haswell/haswell.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 45d18331af..59379b576b 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -513,16 +513,6 @@ static void igd_init(struct device *dev) if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - /* Wait for any configured pre-graphics delay */ - if (!acpi_is_wakeup_s3()) { -#if CONFIG(CHROMEOS) - if (display_init_required()) - mdelay(CONFIG_PRE_GRAPHICS_DELAY); -#else - mdelay(CONFIG_PRE_GRAPHICS_DELAY); -#endif - } - /* Early init steps */ if (is_broadwell) { reg_script_run_on_dev(dev, broadwell_early_init_script); diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 38f057e129..48a83df7b2 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <device/pci_ops.h> #include <console/console.h> #include <types.h> diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 4cb16201ad..84b8d00938 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -156,6 +156,15 @@ static void pch_power_options(struct device *dev) default: state = "undefined"; } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); @@ -174,21 +183,8 @@ static void pch_power_options(struct device *dev) static void pch_misc_init(struct device *dev) { u8 reg8; - u16 reg16; u32 reg32; - reg16 = pci_read_config16(dev, GEN_PMCON_3); - - reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ - - reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ - - pci_write_config16(dev, GEN_PMCON_3, reg16); - /* Prepare sleep mode */ reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); reg32 &= ~SLP_TYP; diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 31d6ad8482..5d3ccce7d9 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -2,7 +2,6 @@ #include <string.h> #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <program_loading.h> diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 943c15e70b..37fe21672d 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 87b4be7844..9c393e5cec 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -122,11 +122,13 @@ static struct { { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, "Coffeelake-S GT1" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, "Coffeelake-S GT1" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_U_GT2, "Coffeelake-U GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f96a2d7853..e7f3f0d72b 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -5,7 +5,6 @@ #include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <bootstate.h> #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/turbo.h> diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 2b630d0cdf..b1c5aa2ab6 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -75,8 +75,7 @@ config USE_INTEL_FSP_MP_INIT config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" - depends on FSP_USES_MP_SERVICES_PPI - default y if FSP_PEIM_TO_PEIM_INTERFACE + default y if MP_SERVICES_PPI default n help This option allows FSP to make use of MP services PPI published by diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 036a50a4bf..62c274be57 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> + #include <console/console.h> #include <boot_device.h> #include <cbfs.h> diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7150babc83..ca96f35d20 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -221,11 +221,13 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, - PCI_DEVICE_ID_INTEL_CFL_U_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index cf5613853e..d70706256e 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -18,10 +18,10 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ /* MCHBAR */ -#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR64(x) (*(volatile u64 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR32(x) (*(volatile u32 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR64(x) (*(volatile u64 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) /* Perform System Agent Initialization during Bootblock phase */ void bootblock_systemagent_early_init(void); diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 86ca4e1b84..ce842e850f 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -7,6 +7,7 @@ #include <cpu/x86/smm.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> +#include <arch/bert_storage.h> #include <types.h> /* @@ -49,12 +50,22 @@ * +---------------------------+ 0 */ +#define BERT_REGION_MAX_SIZE 0x10000 + void smm_region(uintptr_t *start, size_t *size) { *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } +void bert_reserved_region(void **start, size_t *size) +{ + *start = cbmem_add(CBMEM_ID_ACPI_BERT, BERT_REGION_MAX_SIZE); + *size = BERT_REGION_MAX_SIZE; + + printk(BIOS_DEBUG, "Reserving BERT start %lx, size %lx\n", (uintptr_t)*start, *size); +} + void fill_postcar_frame(struct postcar_frame *pcf) { /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7ad103db0d..25804d7d02 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -26,12 +26,12 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index ff7457c166..ba64c0436c 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a14be36737..501e6c3339 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -26,12 +26,12 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 6a8e329035..67b7ca513f 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 5324d84142..08bd4be651 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -27,12 +27,12 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 7702bf03e4..a3c2b259d6 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> #include <intelblocks/cpulib.h> diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h index fee0e42a7d..64378cce3d 100644 --- a/src/soc/intel/quark/include/soc/nvs.h +++ b/src/soc/intel/quark/include/soc/nvs.h @@ -8,6 +8,10 @@ struct __packed global_nvs { uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ uint8_t pwrs; /* 0x4 - Power state (AC = 1) */ + + /* Required for future unified acpi_save_wake_source. */ + uint32_t pm1i; + uint32_t gpei; }; #endif /* SOC_INTEL_QUARK_NVS_H */ diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index efe3c10d00..11f70596da 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -84,7 +84,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) /* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; aupd->BootLoaderTolumSize = cbmem_overhead_size(); - aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); + aupd->StackBase = (uintptr_t)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; /* Display the ESRAM layout */ @@ -97,8 +97,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", CONFIG_FSP_ESRAM_LOC); printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+ %p\n", - aupd->StackBase); + printk(BIOS_SPEW, "+-------------------+ 0x%zx\n", + (size_t)aupd->StackBase); printk(BIOS_SPEW, "| |\n"); printk(BIOS_SPEW, "+-------------------+ %p\n", _car_unallocated_start); diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index da8252367c..483be59d87 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -5,7 +5,7 @@ * * Due to what appears to be an ACPI interpreter bug we do not use * the PCRB() method here as it may not be defined yet because the method - * definiton depends on the order of the include files in pch.asl. + * definition depends on the order of the include files in pch.asl. * * https://bugs.acpica.org/show_bug.cgi?id=1201 */ diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cd84bdf453..3e080cce60 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -30,12 +30,12 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index cb1731f38c..f3e821f439 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 08d890087c..39180f7393 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -196,8 +196,6 @@ Method (_PS0, 0, Serialized) If (PMEX == 1) { PMEX = 0 /* Disable Power Management SCI */ } - - Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ } Method (_PS3, 0, Serialized) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d3062cc720..edc716064f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -105,6 +105,9 @@ struct soc_intel_tigerlake_config { /* Common struct containing power limits configuration information */ struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX]; + /* Configuration for boot TDP selection; */ + uint8_t ConfigTdpLevel; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 7f7135e308..49af38454f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -57,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_BLOCK_ACPI select TSC_MONOTONIC_TIMER + select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c index deb9030c20..1e0ba008c2 100644 --- a/src/soc/intel/xeon_sp/cpx/ramstage.c +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -1,8 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <fsp/api.h> +#include <smbios.h> int soc_fsp_multi_phase_init_is_enable(void) { return 0; } + +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + return 3900; +} diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 99326ee6a4..5e1b412fd3 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> -#include <cbmem.h> #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 2d286231a6..79768d48c9 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> -#include <cbmem.h> #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index aa8079ef6b..b3a9693ea4 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <boardid.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/dramc_common.h> diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 9d22ef2b64..9109e61566 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -78,7 +78,7 @@ mcu-firmware-files := \ $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8192_BLOB_DIR)/$(fw)) \ $(eval $(fw)-type := raw) \ - $(eval $(fw)-compression := $(CBFS_COMPRESS_FLAG)) \ + $(eval $(fw)-compression := LZ4) \ $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ ) diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index f080a11776..13eebc8a81 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <cbfs.h> #include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/mcu_common.h> #include <soc/spm.h> #include <soc/symbols.h> +#include <string.h> #include <timer.h> #define SPM_SYSTEM_BASE_OFFSET 0x40000000 diff --git a/src/soc/nvidia/tegra124/include/soc/gpio.h b/src/soc/nvidia/tegra124/include/soc/gpio.h index 6b66a98319..48601dd8a5 100644 --- a/src/soc/nvidia/tegra124/include/soc/gpio.h +++ b/src/soc/nvidia/tegra124/include/soc/gpio.h @@ -4,7 +4,7 @@ #define __SOC_NVIDIA_TEGRA124_GPIO_H__ #include <soc/nvidia/tegra/gpio.h> -#include <soc/pinmux.h> /* for pinmux constants in GPIO macro */ +#include <soc/pinmux.h> /* GPIO index constants. */ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 93588904b5..daea209082 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -2,7 +2,6 @@ #include <console/cbmem_console.h> #include <cbmem.h> -#include <boardid.h> #include <bootmode.h> #include <string.h> #include <fmap.h> diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index eb90f86383..86ee993e76 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> +#include <program_loading.h> #include <soc/mmu.h> #include <soc/aop.h> #include <soc/clock.h> diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index c0a7589abd..66d7c2003e 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <commonlib/bsd/helpers.h> #include <stdint.h> #include <symbols.h> diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 99c7323033..760088632e 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -44,8 +44,8 @@ typedef union _PCI_ADDR { #include <SBDEF.h> #include <AMDSBLIB.h> #include <SBSUBFUN.h> -#include "platform_cfg.h" /* mainboard specific configuration */ -#include <OEM.h> /* platform default configuration */ +#include "platform_cfg.h" +#include <OEM.h> #include <AMD.h> //------------------------------------------------------------------------------------------------------------------------// diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 21816e5136..e3ad885cb4 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -56,4 +56,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index e873f55375..25dcfe0ffe 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb2), XHCI, 8, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value CBMC, 32, diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4a033abfb1..5a80ab0b3e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -181,7 +181,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 767d3ad936..6ed3dce8b9 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -218,7 +218,7 @@ void early_pch_init_native(void) static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index 969d59209b..1c33b0cd73 100644 --- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -97,7 +97,11 @@ struct __packed global_nvs { u8 rsvd11[6]; /* XHCI */ u8 xhci; - u8 rsvd12[65]; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; + u8 rsvd12[57]; u8 tpiq; /* 0xf5 - trackpad IRQ value */ u32 cbmc; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 2adfbd5c98..fe2a37c849 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -254,6 +254,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -279,9 +283,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b0226a6e9a..f5a39ecfa6 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -242,6 +242,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -268,9 +272,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index bef98fae10..28337f6913 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -186,7 +186,7 @@ void southbridge_smm_xhci_sleep(u8 slp_type) return; /* Verify that RCBA is still valid */ - if (pci_read_config32(PCH_LPC_DEV, RCBA) != ((u32)DEFAULT_RCBA | RCBA_ENABLE)) + if (pci_read_config32(PCH_LPC_DEV, RCBA) != (CONFIG_FIXED_RCBA_MMIO_BASE | RCBA_ENABLE)) return; if (RCBA32(FD) & PCH_DISABLE_XHCI) diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index a14513dead..1bdefd4b93 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -104,6 +104,14 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE +config FIXED_RCBA_MMIO_BASE + hex + default 0xfed1c000 + +config RCBA_LENGTH + hex + default 0x4000 + config FIXED_SMBUS_IO_BASE hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 712a477cc1..4a9847a32a 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -3,9 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H -#ifndef __ACPI__ - -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE) /* Root Complex Register Block */ #define RCBA 0xf0 @@ -23,10 +21,4 @@ #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) -#else - -#define DEFAULT_RCBA 0xfed1c000 - -#endif /* __ACPI__ */ - #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 1e3889b4f5..a3b15b68d7 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -101,4 +101,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 4d077205a3..6c9c9694f9 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -110,7 +110,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { // Backbone diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 72281ea5f3..c8a6117de5 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -48,7 +48,7 @@ void i82801gx_lpc_setup(void) void i82801gx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index b2a6baa7e8..933921c3f4 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -98,6 +98,10 @@ struct __packed global_nvs { u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index d2af885b0e..f408a8c53a 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -103,4 +103,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index f720505c08..1a07ec211c 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -110,7 +110,7 @@ Scope(\) // ICH9 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 3c0f3aeff4..f781098f33 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -51,7 +51,7 @@ void i82801ix_early_init(void) enable_smbus(); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 2d4980bec3..3c9aac90a2 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -98,6 +98,10 @@ struct __packed global_nvs { u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index d2af885b0e..264b52a3b0 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -103,4 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index d6136af14f..0e4c03b07a 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -112,7 +112,7 @@ Scope(\) // ICH10 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 771460955c..327c8fc0a5 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -50,7 +50,7 @@ void i82801jx_setup_bars(void) const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 4325a8c1ee..54c4a2c7c4 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -97,6 +97,10 @@ struct __packed global_nvs { u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f172bf1eb3..34ae2f112a 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -53,4 +53,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 949da74d8c..46c6f4f958 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb2), XHCI, 8, CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378eca4..99fa5306ff 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -80,7 +80,7 @@ void bootblock_early_southbridge_init(void) /* Enable RCBA */ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index f5285c1355..2fa4b52d23 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -30,7 +30,7 @@ static void pch_default_disable(void) void ibexpeak_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index 5ce88a68b1..03897cd4b7 100644 --- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -100,6 +100,10 @@ struct __packed global_nvs { u8 xhci; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6a45fb42eb..20b8aac94a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -476,6 +476,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -494,9 +498,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 979e084161..1b06beb7b6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -93,6 +93,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer + + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc274d..50f73cdf9c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,7 +19,7 @@ Scope (\) } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58ef88..c063bfb10a 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,7 +7,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a8760c..ace8b54552 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -36,7 +36,7 @@ enum pch_platform_type get_pch_platform_type(void) static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h index 17ded13589..7db206e6e9 100644 --- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h @@ -73,6 +73,10 @@ struct __packed global_nvs { u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 24a5a7ef9a..b0ff5450cf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -557,10 +557,10 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { + if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { res = new_resource(dev, RCBA); - res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; - res->size = 16 * 1024; + res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; + res->size = CONFIG_RCBA_LENGTH; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; } diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 338133c33c..960d0b4eb3 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -12,7 +12,61 @@ /** Fsp M Configuration **/ typedef struct __packed { - uint16_t UpdTerminator; + /** Offset 0x0040**/ uint32_t pci_express_base_addr; + /** Offset 0x0044**/ uint32_t serial_port_base; + /** Offset 0x0048**/ uint32_t serial_port_use_mmio; + /** Offset 0x004C**/ uint32_t serial_port_stride; + /** Offset 0x0050**/ uint32_t serial_port_baudrate; + /** Offset 0x0054**/ uint32_t serial_port_refclk; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; + /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; + /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; + /** Offset 0x0078**/ uint8_t aa_mode_en; + /** Offset 0x0079**/ uint8_t unused2; + /** Offset 0x007A**/ uint8_t unused3; + /** Offset 0x007B**/ uint8_t unused4; + /** Offset 0x007C**/ uint32_t fast_ppt_limit_mW; + /** Offset 0x0080**/ uint32_t slow_ppt_limit_mW; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s; + /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; + /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; + /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; + /** Offset 0x00A0**/ uint32_t stapm_time_constant_s; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms; + /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; + /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; + /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; + /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; + /** Offset 0x00C1**/ uint8_t system_config; + /** Offset 0x00C2**/ uint8_t core_dldo_bypass; + /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; + /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; + /** Offset 0x00C5**/ uint8_t unused5; + /** Offset 0x00C6**/ uint8_t unused6; + /** Offset 0x00C7**/ uint8_t sata_enable; + /** Offset 0x00C8**/ uint32_t tseg_size; + /** Offset 0x00CC**/ uint8_t pspp_policy; + /** Offset 0x00CD**/ uint8_t audio_soundwire; + /** Offset 0x00CE**/ uint8_t hd_audio_enable; + /** Offset 0x00CF**/ uint8_t unused9; + /** Offset 0x00D0**/ uint32_t bert_size; + /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0; + /** Offset 0x00D5**/ uint8_t ccx_down_core_mode; + /** Offset 0x00D6**/ uint8_t ccx_disable_smt; + /** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41]; + /** Offset 0x0100**/ uint16_t Reserved100; + /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index 2b7f19c602..d4f8aeaa82 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -10,7 +10,50 @@ #include <FspUpd.h> typedef struct __packed { - uint16_t UpdTerminator; + /** Offset 0x0020**/ uint32_t emmc0_mode; + /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x0029**/ uint8_t unused0[7]; + /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; + /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; + /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; + /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; + /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; + /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; + /** Offset 0x0090**/ uint8_t dxio_descriptor6[16]; + /** Offset 0x00A0**/ uint8_t dxio_descriptor7[16]; + /** Offset 0x00B0**/ uint8_t unused1[16]; + /** Offset 0x00C0**/ uint32_t ddi_descriptor0; + /** Offset 0x00C4**/ uint32_t ddi_descriptor1; + /** Offset 0x00C8**/ uint32_t ddi_descriptor2; + /** Offset 0x00CC**/ uint32_t ddi_descriptor3; + /** Offset 0x00D0**/ uint8_t unused2[16]; + /** Offset 0x00E0**/ uint8_t fch_usb_version_major; + /** Offset 0x00E1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00E2**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x00EB**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x00F4**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x00FD**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x0106**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x010F**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x0118**/ uint8_t fch_usb_device_removable; + /** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x011D**/ uint8_t unused3; + /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; + /** Offset 0x0122**/ uint8_t xhci0_force_gen1; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; + /** Offset 0x0130**/ uint8_t unused4[16]; + /** Offset 0x0140**/ uint8_t UnusedUpdSpace1[16]; + /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; /** Fsp S UPD Configuration diff --git a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h index c477a4ff1f..1a295f591a 100644 --- a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h +++ b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h @@ -35,11 +35,15 @@ typedef struct __packed { _Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); + +#if CONFIG(PLATFORM_USES_FSP2_X86_32) typedef struct __packed { uint8_t Revision; uint8_t Reserved[3]; - void *NvsBufferPtr; - void *StackBase; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t NvsBufferPtr; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t StackBase; uint32_t StackSize; uint32_t BootLoaderTolumSize; uint32_t BootMode; @@ -47,5 +51,8 @@ typedef struct __packed { } FSPM_ARCH_UPD; _Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); +#else +#error You need to implement this struct for x86_64 FSP +#endif #endif /* FSP_H_C99_H */ diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8482..f931bf06e6 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -12,6 +12,7 @@ #define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8 #define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4 #define FSPS_UPD_USB2_PORT_COUNT 6 +#define FSPS_UPD_RV2_USB3_PORT_COUNT 4 typedef struct __packed { /** Offset 0x0020**/ uint32_t emmc0_mode; @@ -39,26 +40,32 @@ typedef struct __packed { /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t usb_3_phy_enable; + /** Offset 0x013D**/ uint8_t usb_3_port_phy_tune[FSPS_UPD_RV2_USB3_PORT_COUNT][2]; + /** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl; + /** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en; + /** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl; + /** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en; + /** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x; + /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x; + /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x; + /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x; + /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; diff --git a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h index c477a4ff1f..79ef9253f8 100644 --- a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h +++ b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h @@ -35,11 +35,14 @@ typedef struct __packed { _Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); +#if CONFIG(PLATFORM_USES_FSP2_X86_32) typedef struct __packed { uint8_t Revision; uint8_t Reserved[3]; - void *NvsBufferPtr; - void *StackBase; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t NvsBufferPtr; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t StackBase; uint32_t StackSize; uint32_t BootLoaderTolumSize; uint32_t BootMode; @@ -47,5 +50,8 @@ typedef struct __packed { } FSPM_ARCH_UPD; _Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); +#else +#error You need to implement this struct for x86_64 FSP +#endif #endif /* FSP_H_C99_H */ diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 7642676a74..3f20662467 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -2,8 +2,6 @@ #include <security/vboot/vbnv_layout.h> -#if CONFIG(CHROMEOS) - /* GPIO package generated at run time. */ External (OIPG) @@ -100,4 +98,3 @@ Device (CRHW) } #include "ramoops.asl" -#endif diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl deleted file mode 100644 index a1ea3386ba..0000000000 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This device provides an ACPI interface to read VPD keys from either - * the RO_VPD or RW_VPD region. For example: - * - * VPD.VPDF ("RO", "ro_key_name") - * VPD.VPDF ("RW", "rw_key_name") - */ - -Device (VPD) -{ - Name (_HID, "GOOG000F") - Name (_UID, 1) - Name (_STA, 0xf) - - Name (VOFS, 0x600) /* Start of VPD header in VPD region */ - Name (VIHL, 0x10) /* Length of VPD info header */ - Name (VPET, 0x00) /* VPD Entry Type: Terminator */ - Name (VPES, 0x01) /* VPD Entry Type: String */ - Name (VPEI, 0xfe) /* VPD Entry Type: Info (header) */ - Name (MORE, 0x80) /* Bit to indicate more length bytes */ - - Name (VPTR, Zero) /* Pointer to current byte in VPD for parser */ - Name (VEND, Zero) /* End of VPD region */ - - /* - * VLOC() - Return location and length of VPD region in memory. - * These values must be initialized in GNVS by coreboot. - * - * Returns: Package indicating start and length of region: - * [0] = Address of the start of VPD region. - * [1] = Length of the VPD region. - */ - Method (VLOC, 1, Serialized) - { - Switch (ToString (Arg0)) - { - Case ("RO") { - Return (Package () { \ROVP, \ROVL }) - } - Case ("RW") { - Return (Package () { \RWVP, \RWVL }) - } - Default { - Return (Package () { Zero, Zero }) - } - } - } - - /* - * VVPD() - Verify VPD info header. - * Arg0: VPD partition base address. - * Returns: VPD length or Zero if VPD header is not valid. - */ - Method (VVPD, 1, Serialized) - { - Local0 = Arg0 + ^VOFS - - OperationRegion (VPDH, SystemMemory, Local0, ^VIHL) - Field (VPDH, DWordAcc, NoLock, Preserve) - { - TYPE, 8, /* VPD Header Tag (=0xfe) */ - KLEN, 8, /* Key length (=9) */ - IVER, 8, /* Info version (=1) */ - SIGN, 64, /* Signature (="gVpdInfo") */ - VLEN, 8, /* Value length (=4) */ - SIZE, 32, /* VPD length */ - } - - If (TYPE != ^VPEI) { - Return (Zero) - } - If (KLEN != 9) { - Return (Zero) - } - If (IVER != 1) { - Return (Zero) - } - If (ToString (SIGN) != "gVpdInfo") { - Return (Zero) - } - If (VLEN != 4) { - Return (Zero) - } - - Return (SIZE) - } - - /* Return next byte from VPD at pointer VPTR, and increment VPTR. */ - Method (VPRB, 0, Serialized) - { - If (^VPTR > ^VEND) { - Printf ("Access beyond end of VPD region") - Return (Zero) - } - - Local0 = ^VPTR - OperationRegion (VPDR, SystemMemory, Local0, One) - Field (VPDR, DWordAcc, NoLock, Preserve) - { - BYTE, 8, - } - - /* Increment address pointer */ - ^VPTR++ - Return (BYTE) - } - - /* Extract and return next string from VPD. */ - Method (VPDE, 0, Serialized) - { - Local0 = One /* Indicates if there are more bytes */ - Local1 = Zero /* Length */ - - /* Decode the string length */ - While (Local0) { - /* Read the next byte at indicated address */ - Local2 = ^VPRB () - - /* Update the more bit from the byte in Local2 */ - Local0 = Local2 >> 7 - - /* Save the length bits from Local2 */ - Local1 <<= 7 - Local1 |= Local2 & 0x7f - } - If (Local1 == Zero) { - Return (Zero) - } - - /* Extract the string */ - Local3 = Zero - Local4 = "" - While (Local3 < Local1) { - Concatenate (Local4, ToString (^VPRB ()), Local4) - Local3++ - } - - Return (Local4) - } - - /* - * VPDS() - Find next VPD key and value. - * Returns: Package containing key and value: - * [0] = VPD key string - * [1] = VPD value string - */ - Method (VPDS, 0, Serialized) - { - Name (VPKV, Package () { "", "" }) - - /* Read the VPD type and ensure it is a string */ - If (^VPRB () != ^VPES) { - Printf ("VPDS: Type is not a string") - Return (VPKV) - } - - /* Extract the key string and value */ - VPKV[0] = VPDE () - VPKV[1] = VPDE () - - Return (VPKV) - } - - /* - * VPDF() - Find VPD key with matching name. - * Arg0: VPD Partition, either "RO" or "RW". - * Arg1: VPD key name to search for. - * Returns: VPD string corresponding to VPD key, or Zero if not found. - */ - Method (VPDF, 2, Serialized) - { - Local0 = VLOC (Arg0) - - /* Start of VPD region */ - ^VPTR = DerefOf (Local0[0]) - - /* End address of VPD region */ - ^VEND = ^VPTR + DerefOf (Local0[1]) - - If (^VPTR == Zero || ^VEND == Zero) { - Printf ("Unable to find VPD region") - Return (Zero) - } - - /* Verify VPD info header and save size */ - Local0 = VVPD (^VPTR) - If (Local0 == Zero) { - Printf ("VPD region %o did not verify", Arg0) - Return (Zero) - } - - /* Set VPD pointer to start of VPD entries */ - ^VPTR += ^VOFS + ^VIHL - - /* Search through VPD entries until key is found */ - Local1 = "" - While (Local1 != ToString (Arg1)) { - Local2 = VPDS () - Local1 = DerefOf (Local2[0]) - If (Local1 == "") { - Printf ("VPD KEY %o not found", Arg1) - Return (Zero) - } - } - Local3 = DerefOf (Local2[1]) - - Printf ("Found VPD KEY %o = %o", Local1, Local3) - Return (Local3) - } -} diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 23ae587fb8..b49dc64240 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -6,18 +6,22 @@ ifeq ($(CONFIG_UEFI_2_4_BINDING),y) # ProcessorBind.h isn't just about types. There's compiler definitions as well # as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for # a fixed width type. -CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include else ifeq ($(CONFIG_UDK_2015_BINDING),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32 +CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Ia32 +CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include else ifeq ($(CONFIG_UDK_2017_BINDING),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32 +CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32 +CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include else ifeq ($(CONFIG_UDK_202005_BINDING),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32 +CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32 +CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include endif diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h index c58b169f99..df2b7dcd73 100644 --- a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -50,6 +50,7 @@ typedef struct { UINT8 Reserved[23]; } FSP_UPD_HEADER; +#if CONFIG(PLATFORM_USES_FSP2_X86_32) /// /// FSPM_ARCH_UPD Configuration. /// @@ -63,12 +64,16 @@ typedef struct { /// Pointer to the non-volatile storage (NVS) data buffer. /// If it is NULL it indicates the NVS data is not available. /// - VOID *NvsBufferPtr; + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT32 NvsBufferPtr; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - VOID *StackBase; + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT32 StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. @@ -85,6 +90,9 @@ typedef struct { UINT32 BootMode; UINT8 Reserved1[8]; } FSPM_ARCH_UPD; +#else +#error You need to implement this struct for x86_64 FSP +#endif /// /// FSPT_UPD_COMMON Configuration. diff --git a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h index 29c98ee163..c22b701ede 100644 --- a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -50,6 +50,7 @@ typedef struct { UINT8 Reserved[23]; } FSP_UPD_HEADER; +#if CONFIG(PLATFORM_USES_FSP2_X86_32) /// /// FSPM_ARCH_UPD Configuration. /// @@ -63,12 +64,16 @@ typedef struct { /// Pointer to the non-volatile storage (NVS) data buffer. /// If it is NULL it indicates the NVS data is not available. /// - VOID *NvsBufferPtr; + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT32 NvsBufferPtr; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - VOID *StackBase; + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT32 StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. @@ -85,6 +90,9 @@ typedef struct { UINT32 BootMode; UINT8 Reserved1[8]; } FSPM_ARCH_UPD; +#else +#error You need to implement this struct for x86_64 FSP +#endif /// /// FSPT_UPD_COMMON Configuration. diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h index eb9ce86124..8314f0b979 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -128,6 +128,7 @@ typedef struct { UINT8 Reserved1[20]; } FSPT_ARCH_UPD; +#if CONFIG(PLATFORM_USES_FSP2_X86_32) /// /// FSPM_ARCH_UPD Configuration. /// @@ -141,12 +142,16 @@ typedef struct { /// Pointer to the non-volatile storage (NVS) data buffer. /// If it is NULL it indicates the NVS data is not available. /// - VOID *NvsBufferPtr; + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT32 NvsBufferPtr; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - VOID *StackBase; + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT32 StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. @@ -165,9 +170,14 @@ typedef struct { /// Optional event handler for the bootloader to be informed of events occurring during FSP execution. /// This value is only valid if Revision is >= 2. /// - FSP_EVENT_HANDLER *FspEventHandler; + /// Note: This ought to be FSP_EVENT_HANDLER*, but that won't allow calling this binary on x86_64. + /// + UINT32 FspEventHandler; UINT8 Reserved1[4]; } FSPM_ARCH_UPD; +#else +#error You need to implement this struct for x86_64 FSP +#endif typedef struct { /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices2.h b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices2.h new file mode 100644 index 0000000000..8efa6fed87 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices2.h @@ -0,0 +1,279 @@ +/** @file + This file declares EDKII Multi-processor service PPI. + + Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EDKII_PEI_MP_SERVICES2_PPI_H__ +#define __EDKII_PEI_MP_SERVICES2_PPI_H__ + +#include <Ppi/MpServices.h> + +#define EDKII_PEI_MP_SERVICES2_PPI_GUID \ + { \ + 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba} \ + } + +typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI; + +/** + Get the number of CPU's. + + @param[in] This Pointer to this instance of the PPI. + @param[out] NumberOfProcessors Pointer to the total number of logical processors in + the system, including the BSP and disabled APs. + @param[out] NumberOfEnabledProcessors + Number of processors in the system that are enabled. + + @retval EFI_SUCCESS The number of logical processors and enabled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL. + NumberOfEnabledProcessors is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors + ); + +/** + Get information on a specific CPU. + + @param[in] This Pointer to this instance of the PPI. + @param[in] ProcessorNumber Pointer to the total number of logical processors in + the system, including the BSP and disabled APs. + @param[out] ProcessorInfoBuffer Number of processors in the system that are enabled. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist in the platform. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + ); + +/** + Activate all of the application proessors. + + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] Procedure A pointer to the function to be run on enabled APs of + the system. + @param[in] SingleThread If TRUE, then all the enabled APs execute the function + specified by Procedure one by one, in ascending order + of processor handle number. If FALSE, then all the + enabled APs execute the function specified by Procedure + simultaneously. + @param[in] TimeoutInMicroSeconds + Indicates the time limit in microseconds for APs to + return from Procedure, for blocking mode only. Zero + means infinity. If the timeout expires before all APs + return from Procedure, then Procedure on the failed APs + is terminated. All enabled APs are available for next + function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() + or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the + timeout expires in blocking mode, BSP returns + EFI_TIMEOUT. + @param[in] ProcedureArgument The parameter passed into Procedure for all APs. + + @retval EFI_SUCCESS In blocking mode, all APs have finished before the + timeout expired. + @retval EFI_DEVICE_ERROR Caller processor is AP. + @retval EFI_NOT_STARTED No enabled APs exist in the system. + @retval EFI_NOT_READY Any enabled APs are busy. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before all + enabled APs have finished. + @retval EFI_INVALID_PARAMETER Procedure is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL + ); + +/** + Activate a specific application processor. + + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] Procedure A pointer to the function to be run on enabled APs of + the system. + @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + @param[in] TimeoutInMicroSeconds + Indicates the time limit in microseconds for APs to + return from Procedure, for blocking mode only. Zero + means infinity. If the timeout expires before all APs + return from Procedure, then Procedure on the failed APs + is terminated. All enabled APs are available for next + function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() + or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the + timeout expires in blocking mode, BSP returns + EFI_TIMEOUT. + @param[in] ProcedureArgument The parameter passed into Procedure for all APs. + + @retval EFI_SUCCESS In blocking mode, specified AP finished before the + timeout expires. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before the + specified AP has finished. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP. + @retval EFI_INVALID_PARAMETER Procedure is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL + ); + +/** + Switch the boot strap processor. + + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an enabled + AP. Otherwise, it will be disabled. + + @retval EFI_SUCCESS BSP successfully switched. + @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to this + service returning. + @retval EFI_UNSUPPORTED Switching the BSP is not supported. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled + AP. + @retval EFI_NOT_READY The specified AP is busy. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP + ); + +/** + Enable or disable an application processor. + + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + @param[in] EnableAP Specifies the new state for the processor for enabled, + FALSE for disabled. + @param[in] HealthFlag If not NULL, a pointer to a value that specifies the + new health status of the AP. This flag corresponds to + StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo(). + Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other + bits are ignored. If it is NULL, this parameter is + ignored. + + @retval EFI_SUCCESS The specified AP was enabled or disabled successfully. + @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed prior + to this service returning. + @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber + does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL + ); + +/** + Identify the currently executing processor. + + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[out] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + + @retval EFI_SUCCESS The current processor handle number was returned in + ProcessorNumber. + @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + OUT UINTN *ProcessorNumber + ); + + +/** + Activate all of the application proessors. + + @param[in] This A pointer to the EDKII_PEI_MP_SERVICES2_PPI instance. + @param[in] Procedure A pointer to the function to be run on enabled APs of + the system. + @param[in] TimeoutInMicroSeconds + Indicates the time limit in microseconds for APs to + return from Procedure, for blocking mode only. Zero + means infinity. If the timeout expires in blocking + mode, BSP returns EFI_TIMEOUT. + @param[in] ProcedureArgument The parameter passed into Procedure for all CPUs. + + @retval EFI_SUCCESS In blocking mode, all APs have finished before the + timeout expired. + @retval EFI_DEVICE_ERROR Caller processor is AP. + @retval EFI_NOT_READY Any enabled APs are busy. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before all + enabled APs have finished. + @retval EFI_INVALID_PARAMETER Procedure is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS) ( + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL + ); + +struct _EDKII_PEI_MP_SERVICES2_PPI { + EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; + EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo; + EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs; + EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP; + EDKII_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP; + EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP; + EDKII_PEI_MP_SERVICES_WHOAMI WhoAmI; + EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS StartupAllCPUs; +}; + +extern EFI_GUID gEdkiiPeiMpServices2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 0e9ca02d35..d0421723eb 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -595,262 +595,262 @@ typedef struct { /** Offset 0x038F - Reserved
**/
- UINT8 Reserved21[11];
+ UINT8 Reserved21[3];
-/** Offset 0x039A - BiosGuard
+/** Offset 0x0392 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x039B
+/** Offset 0x0393
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x039C - Reserved
+/** Offset 0x0394 - Reserved
**/
UINT8 Reserved22[4];
-/** Offset 0x03A0 - PrmrrSize
+/** Offset 0x0398 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x03A4 - SinitMemorySize
+/** Offset 0x039C - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x03A8 - Reserved
+/** Offset 0x03A0 - Reserved
**/
UINT8 Reserved23[8];
-/** Offset 0x03B0 - TxtHeapMemorySize
+/** Offset 0x03A8 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x03B4 - TxtDprMemorySize
+/** Offset 0x03AC - TxtDprMemorySize
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x03B8 - Reserved
+/** Offset 0x03B0 - Reserved
**/
- UINT8 Reserved24[614];
+ UINT8 Reserved24[625];
-/** Offset 0x061E - Number of RsvdSmbusAddressTable.
+/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x061F - Reserved
+/** Offset 0x0622 - Reserved
**/
- UINT8 Reserved25[4];
+ UINT8 Reserved25[3];
-/** Offset 0x0623 - Usage type for ClkSrc
+/** Offset 0x0625 - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
(free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
-/** Offset 0x0635 - Reserved
+/** Offset 0x0637 - Reserved
**/
UINT8 Reserved26[14];
-/** Offset 0x0643 - ClkReq-to-ClkSrc mapping
+/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
-/** Offset 0x0655 - Reserved
+/** Offset 0x0657 - Reserved
**/
- UINT8 Reserved27[91];
+ UINT8 Reserved27[93];
-/** Offset 0x06B0 - Enable PCIE RP Mask
+/** Offset 0x06B4 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpEnableMask;
-/** Offset 0x06B4 - Reserved
+/** Offset 0x06B8 - Reserved
**/
UINT8 Reserved28[2];
-/** Offset 0x06B6 - Enable HD Audio Link
+/** Offset 0x06BA - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
-/** Offset 0x06B7 - Reserved
+/** Offset 0x06BB - Reserved
**/
UINT8 Reserved29[3];
-/** Offset 0x06BA - Enable HD Audio DMIC_N Link
+/** Offset 0x06BE - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
-/** Offset 0x06BC - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-/** Offset 0x06C4 - DMIC<N> ClkB Pin Muxing
+/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-/** Offset 0x06CC - Enable HD Audio DSP
+/** Offset 0x06D0 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x06CD - Reserved
+/** Offset 0x06D1 - Reserved
**/
UINT8 Reserved30[3];
-/** Offset 0x06D0 - DMIC<N> Data Pin Muxing
+/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-/** Offset 0x06D8 - Enable HD Audio SSP0 Link
+/** Offset 0x06DC - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
-/** Offset 0x06DE - Enable HD Audio SoundWire#N Link
+/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
-/** Offset 0x06E2 - iDisp-Link Frequency
+/** Offset 0x06E6 - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x06E3 - iDisp-Link T-mode
+/** Offset 0x06E7 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x06E4 - iDisplay Audio Codec disconnection
+/** Offset 0x06E8 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x06E5 - Debug Interfaces
+/** Offset 0x06E9 - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
-/** Offset 0x06E6 - Serial Io Uart Debug Controller Number
+/** Offset 0x06EA - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
Core interface, it cannot be used for debug purpose.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x06E7 - Reserved
+/** Offset 0x06EB - Reserved
**/
UINT8 Reserved31[13];
-/** Offset 0x06F4 - ISA Serial Base selection
+/** Offset 0x06F8 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x06F5 - Reserved
+/** Offset 0x06F9 - Reserved
**/
UINT8 Reserved32[4];
-/** Offset 0x06F9 - MRC Safe Config
+/** Offset 0x06FD - MRC Safe Config
Enables/Disable MRC Safe Config
$EN_DIS
**/
UINT8 MrcSafeConfig;
-/** Offset 0x06FA - TCSS Thunderbolt PCIE Root Port 0 Enable
+/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
-/** Offset 0x06FB - TCSS Thunderbolt PCIE Root Port 1 Enable
+/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
-/** Offset 0x06FC - TCSS Thunderbolt PCIE Root Port 2 Enable
+/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
-/** Offset 0x06FD - TCSS Thunderbolt PCIE Root Port 3 Enable
+/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
-/** Offset 0x06FE - TCSS USB HOST (xHCI) Enable
+/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
-/** Offset 0x06FF - TCSS USB DEVICE (xDCI) Enable
+/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
-/** Offset 0x0700 - TCSS DMA0 Enable
+/** Offset 0x0704 - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
-/** Offset 0x0701 - TCSS DMA1 Enable
+/** Offset 0x0705 - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
-/** Offset 0x0702 - Reserved
+/** Offset 0x0706 - Reserved
**/
UINT8 Reserved33[2];
-/** Offset 0x0704 - Early Command Training
+/** Offset 0x0708 - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
-/** Offset 0x0705 - Reserved
+/** Offset 0x0709 - Reserved
**/
UINT8 Reserved34[65];
-/** Offset 0x0746 - Ch Hash Mask
+/** Offset 0x074A - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
-/** Offset 0x0748 - Reserved
+/** Offset 0x074C - Reserved
**/
- UINT8 Reserved35[64];
+ UINT8 Reserved35[66];
-/** Offset 0x0788 - PcdSerialDebugLevel
+/** Offset 0x078E - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -859,91 +859,91 @@ typedef struct { **/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x0789 - Reserved
+/** Offset 0x078F - Reserved
**/
UINT8 Reserved36[2];
-/** Offset 0x078B - Safe Mode Support
+/** Offset 0x0791 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
$EN_DIS
**/
UINT8 SafeMode;
-/** Offset 0x078C - Reserved
+/** Offset 0x0792 - Reserved
**/
UINT8 Reserved37[2];
-/** Offset 0x078E - TCSS USB Port Enable
+/** Offset 0x0794 - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
-/** Offset 0x078F - Reserved
+/** Offset 0x0795 - Reserved
**/
- UINT8 Reserved38[35];
+ UINT8 Reserved38[33];
-/** Offset 0x07B2 - Command Pins Mapping
+/** Offset 0x07B6 - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x07B3 - Reserved
+/** Offset 0x07B7 - Reserved
**/
- UINT8 Reserved39[14];
+ UINT8 Reserved39[12];
-/** Offset 0x07C1 - Skip external display device scanning
+/** Offset 0x07C3 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x07C2 - Reserved
+/** Offset 0x07C4 - Reserved
**/
UINT8 Reserved40;
-/** Offset 0x07C3 - Lock PCU Thermal Management registers
+/** Offset 0x07C5 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x07C4 - Reserved
+/** Offset 0x07C6 - Reserved
**/
- UINT8 Reserved41[129];
+ UINT8 Reserved41[131];
-/** Offset 0x0845 - Skip CPU replacement check
+/** Offset 0x0849 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0846 - Reserved
+/** Offset 0x084A - Reserved
**/
UINT8 Reserved42[292];
-/** Offset 0x096A - Serial Io Uart Debug Mode
+/** Offset 0x096E - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x096B - Reserved
+/** Offset 0x096F - Reserved
**/
- UINT8 Reserved43[183];
+ UINT8 Reserved43[185];
-/** Offset 0x0A22 - GPIO Override
+/** Offset 0x0A28 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
**/
UINT8 GpioOverride;
-/** Offset 0x0A23 - Reserved
+/** Offset 0x0A29 - Reserved
**/
- UINT8 Reserved44[349];
+ UINT8 Reserved44[23];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -962,11 +962,11 @@ typedef struct { **/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0B80
+/** Offset 0x0A40
**/
- UINT8 UnusedUpdSpace29[6];
+ UINT8 UnusedUpdSpace25[6];
-/** Offset 0x0B86
+/** Offset 0x0A46
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index d9cbc5b832..8a92e001af 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -377,40 +377,44 @@ typedef struct { **/
UINT8 CnviMode;
-/** Offset 0x043D - CNVi BT Core
+/** Offset 0x043D - Reserved
+**/
+ UINT8 Reserved15;
+
+/** Offset 0x043E - CNVi BT Core
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtCore;
-/** Offset 0x043E - CNVi BT Audio Offload
+/** Offset 0x043F - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
-/** Offset 0x043F - Reserved
+/** Offset 0x0440 - Reserved
**/
- UINT8 Reserved15;
+ UINT8 Reserved16[4];
-/** Offset 0x0440 - CNVi RF_RESET pin muxing
+/** Offset 0x0444 - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
-/** Offset 0x0444 - CNVi CLKREQ pin muxing
+/** Offset 0x0448 - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
in GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
-/** Offset 0x0448 - Reserved
+/** Offset 0x044C - Reserved
**/
- UINT8 Reserved16[172];
+ UINT8 Reserved17[172];
-/** Offset 0x04F4 - CdClock Frequency selection
+/** Offset 0x04F8 - CdClock Frequency selection
0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
@@ -418,293 +422,293 @@ typedef struct { **/
UINT8 CdClock;
-/** Offset 0x04F5 - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit
<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
Disable: FSP will NOT initialize the framebuffer.
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
-/** Offset 0x04F6 - Enable D3 Hot in TCSS
+/** Offset 0x04FA - Enable D3 Hot in TCSS
This policy will enable/disable D3 hot support in IOM
$EN_DIS
**/
UINT8 D3HotEnable;
-/** Offset 0x04F7 - Reserved
+/** Offset 0x04FB - Reserved
**/
- UINT8 Reserved17;
+ UINT8 Reserved18;
-/** Offset 0x04F8 - TypeC port GPIO setting
+/** Offset 0x04FC - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
= AlderLake)
**/
UINT32 IomTypeCPortPadCfg[8];
-/** Offset 0x0518 - Reserved
+/** Offset 0x051C - Reserved
**/
- UINT8 Reserved18[8];
+ UINT8 Reserved19[8];
-/** Offset 0x0520 - Enable D3 Cold in TCSS
+/** Offset 0x0524 - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
$EN_DIS
**/
UINT8 D3ColdEnable;
-/** Offset 0x0521 - Reserved
+/** Offset 0x0525 - Reserved
**/
- UINT8 Reserved19[8];
+ UINT8 Reserved20[16];
-/** Offset 0x0529 - Enable VMD controller
- Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+/** Offset 0x0535 - Enable VMD controller
+ Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
$EN_DIS
**/
UINT8 VmdEnable;
-/** Offset 0x052A - Reserved
+/** Offset 0x0536 - Reserved
**/
- UINT8 Reserved20[120];
+ UINT8 Reserved21[120];
-/** Offset 0x05A2 - TCSS Aux Orientation Override Enable
+/** Offset 0x05AE - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssAuxOri;
-/** Offset 0x05A4 - TCSS HSL Orientation Override Enable
+/** Offset 0x05B0 - TCSS HSL Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssHslOri;
-/** Offset 0x05A6 - Reserved
+/** Offset 0x05B2 - Reserved
**/
- UINT8 Reserved21;
+ UINT8 Reserved22;
-/** Offset 0x05A7 - ITBT Root Port Enable
+/** Offset 0x05B3 - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
0:Disable, 1:Enable
**/
UINT8 ITbtPcieRootPortEn[4];
-/** Offset 0x05AB - Reserved
+/** Offset 0x05B7 - Reserved
**/
- UINT8 Reserved22[3];
+ UINT8 Reserved23[3];
-/** Offset 0x05AE - ITbtConnectTopology Timeout value
+/** Offset 0x05BA - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
is 0-10000. 100 = 100 ms.
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
-/** Offset 0x05B0 - Reserved
+/** Offset 0x05BC - Reserved
**/
- UINT8 Reserved23[7];
+ UINT8 Reserved24[7];
-/** Offset 0x05B7 - Enable/Disable PTM
+/** Offset 0x05C3 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
$EN_DIS
**/
UINT8 PtmEnabled[4];
-/** Offset 0x05BB - Reserved
+/** Offset 0x05C7 - Reserved
**/
- UINT8 Reserved24[200];
+ UINT8 Reserved25[200];
-/** Offset 0x0683 - Skip Multi-Processor Initialization
+/** Offset 0x068F - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. </b>0: Initialize; <b>1: Skip
$EN_DIS
**/
UINT8 SkipMpInit;
-/** Offset 0x0684 - Reserved
+/** Offset 0x0690 - Reserved
**/
- UINT8 Reserved25[8];
+ UINT8 Reserved26[8];
-/** Offset 0x068C - CpuMpPpi
+/** Offset 0x0698 - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
If not NULL, FSP will use the boot loader's implementation of multiprocessing.
See section 5.1.4 of the FSP Integration Guide for more details.
**/
UINT32 CpuMpPpi;
-/** Offset 0x0690 - Reserved
+/** Offset 0x069C - Reserved
**/
- UINT8 Reserved26[74];
+ UINT8 Reserved27[70];
-/** Offset 0x06DA - Enable Power Optimizer
+/** Offset 0x06E2 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x06DB - Reserved
+/** Offset 0x06E3 - Reserved
**/
- UINT8 Reserved27[33];
+ UINT8 Reserved28[33];
-/** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned
+/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
-/** Offset 0x06FD - Reserved
+/** Offset 0x0705 - Reserved
**/
- UINT8 Reserved28[2];
+ UINT8 Reserved29[2];
-/** Offset 0x06FF - Enable PCH ISH SPI pins assigned
+/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiEnable[1];
-/** Offset 0x0700 - Enable PCH ISH UART pins assigned
+/** Offset 0x0708 - Enable PCH ISH UART pins assigned
Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshUartEnable[2];
-/** Offset 0x0702 - Enable PCH ISH I2C pins assigned
+/** Offset 0x070A - Enable PCH ISH I2C pins assigned
Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI2cEnable[3];
-/** Offset 0x0705 - Enable PCH ISH GP pins assigned
+/** Offset 0x070D - Enable PCH ISH GP pins assigned
Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshGpEnable[8];
-/** Offset 0x070D - Reserved
+/** Offset 0x0715 - Reserved
**/
- UINT8 Reserved29[2];
+ UINT8 Reserved30[2];
-/** Offset 0x070F - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x0710 - Reserved
+/** Offset 0x0718 - Reserved
**/
- UINT8 Reserved30[2];
+ UINT8 Reserved31[2];
-/** Offset 0x0712 - RTC Cmos Memory Lock
+/** Offset 0x071A - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
-/** Offset 0x0713 - Enable PCIE RP HotPlug
+/** Offset 0x071B - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[28];
-/** Offset 0x072F - Reserved
+/** Offset 0x0737 - Reserved
**/
- UINT8 Reserved31[56];
+ UINT8 Reserved32[56];
-/** Offset 0x0767 - Enable PCIE RP Clk Req Detect
+/** Offset 0x076F - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[28];
-/** Offset 0x0783 - PCIE RP Advanced Error Report
+/** Offset 0x078B - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[28];
-/** Offset 0x079F - Reserved
+/** Offset 0x07A7 - Reserved
**/
- UINT8 Reserved32[196];
+ UINT8 Reserved33[196];
-/** Offset 0x0863 - PCIE RP Max Payload
+/** Offset 0x086B - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[28];
-/** Offset 0x087F - Touch Host Controller Port 0 Assignment
+/** Offset 0x0887 - Touch Host Controller Port 0 Assignment
Assign THC Port 0
0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
**/
UINT8 ThcPort0Assignment;
-/** Offset 0x0880 - Reserved
+/** Offset 0x0888 - Reserved
**/
- UINT8 Reserved33[5];
+ UINT8 Reserved34[5];
-/** Offset 0x0885 - Touch Host Controller Port 1 Assignment
+/** Offset 0x088D - Touch Host Controller Port 1 Assignment
Assign THC Port 1
0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
**/
UINT8 ThcPort1Assignment;
-/** Offset 0x0886 - Reserved
+/** Offset 0x088E - Reserved
**/
- UINT8 Reserved34[91];
+ UINT8 Reserved35[91];
-/** Offset 0x08E1 - PCIE RP Aspm
+/** Offset 0x08E9 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[28];
-/** Offset 0x08FD - PCIE RP L1 Substates
+/** Offset 0x0905 - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[28];
-/** Offset 0x0919 - Reserved
+/** Offset 0x0921 - Reserved
**/
- UINT8 Reserved35[28];
+ UINT8 Reserved36[28];
-/** Offset 0x0935 - PCIE RP Ltr Enable
+/** Offset 0x093D - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[28];
-/** Offset 0x0951 - Reserved
+/** Offset 0x0959 - Reserved
**/
- UINT8 Reserved36[132];
+ UINT8 Reserved37[132];
-/** Offset 0x09D5 - PCH Sata Pwr Opt Enable
+/** Offset 0x09DD - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x09D6 - Reserved
+/** Offset 0x09DE - Reserved
**/
- UINT8 Reserved37[50];
+ UINT8 Reserved38[50];
-/** Offset 0x0A08 - Enable SATA Port DmVal
+/** Offset 0x0A10 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x0A10 - Enable SATA Port DmVal
+/** Offset 0x0A18 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x0A20 - Reserved
+/** Offset 0x0A28 - Reserved
**/
- UINT8 Reserved38[62];
+ UINT8 Reserved39[62];
-/** Offset 0x0A5E - USB2 Port Over Current Pin
+/** Offset 0x0A66 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x0A6E - USB3 Port Over Current Pin
+/** Offset 0x0A76 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x0A78 - Reserved
+/** Offset 0x0A80 - Reserved
**/
- UINT8 Reserved39[16];
+ UINT8 Reserved40[16];
-/** Offset 0x0A88 - Enable 8254 Static Clock Gating
+/** Offset 0x0A90 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -712,7 +716,7 @@ typedef struct { **/
UINT8 Enable8254ClockGating;
-/** Offset 0x0A89 - Enable 8254 Static Clock Gating On S3
+/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -720,22 +724,22 @@ typedef struct { **/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x0A8A - Reserved
+/** Offset 0x0A92 - Reserved
**/
- UINT8 Reserved40;
+ UINT8 Reserved41;
-/** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode
+/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 HybridStorageMode;
-/** Offset 0x0A8C - Reserved
+/** Offset 0x0A94 - Reserved
**/
- UINT8 Reserved41[93];
+ UINT8 Reserved42[93];
-/** Offset 0x0AE9 - Enable PS_ON.
+/** Offset 0x0AF1 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -743,29 +747,29 @@ typedef struct { **/
UINT8 PsOnEnable;
-/** Offset 0x0AEA - Reserved
+/** Offset 0x0AF2 - Reserved
**/
- UINT8 Reserved42[318];
+ UINT8 Reserved43[318];
-/** Offset 0x0C28 - RpPtmBytes
+/** Offset 0x0C30 - RpPtmBytes
**/
UINT8 RpPtmBytes[4];
-/** Offset 0x0C2C - Reserved
+/** Offset 0x0C34 - Reserved
**/
- UINT8 Reserved43[95];
+ UINT8 Reserved44[95];
-/** Offset 0x0C8B - Enable/Disable IGFX PmSupport
+/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
-/** Offset 0x0C8C - Reserved
+/** Offset 0x0C94 - Reserved
**/
- UINT8 Reserved44;
+ UINT8 Reserved45;
-/** Offset 0x0C8D - GT Frequency Limit
+/** Offset 0x0C95 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -779,22 +783,22 @@ typedef struct { **/
UINT8 GtFreqMax;
-/** Offset 0x0C8E - Reserved
+/** Offset 0x0C96 - Reserved
**/
- UINT8 Reserved45[24];
+ UINT8 Reserved46[24];
-/** Offset 0x0CA6 - Enable or Disable HWP
+/** Offset 0x0CAE - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2-3:Reserved
$EN_DIS
**/
UINT8 Hwp;
-/** Offset 0x0CA7 - Reserved
+/** Offset 0x0CAF - Reserved
**/
- UINT8 Reserved46[8];
+ UINT8 Reserved47[8];
-/** Offset 0x0CAF - TCC Activation Offset
+/** Offset 0x0CB7 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
@@ -802,63 +806,63 @@ typedef struct { **/
UINT8 TccActivationOffset;
-/** Offset 0x0CB0 - Reserved
+/** Offset 0x0CB8 - Reserved
**/
- UINT8 Reserved47[34];
+ UINT8 Reserved48[34];
-/** Offset 0x0CD2 - Enable or Disable CPU power states (C-states)
+/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x0CD3 - Reserved
+/** Offset 0x0CDB - Reserved
**/
- UINT8 Reserved48[196];
+ UINT8 Reserved49[196];
-/** Offset 0x0D97 - Enable LOCKDOWN SMI
+/** Offset 0x0D9F - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x0D98 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x0D99 - Unlock all GPIO pads
+/** Offset 0x0DA1 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x0D9A - Reserved
+/** Offset 0x0DA2 - Reserved
**/
- UINT8 Reserved49[2];
+ UINT8 Reserved50[2];
-/** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[28];
-/** Offset 0x0DD4 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[28];
-/** Offset 0x0E0C - Reserved
+/** Offset 0x0E14 - Reserved
**/
- UINT8 Reserved50[313];
+ UINT8 Reserved51[313];
-/** Offset 0x0F45 - LpmStateEnableMask
+/** Offset 0x0F4D - LpmStateEnableMask
**/
UINT8 LpmStateEnableMask;
-/** Offset 0x0F46 - Reserved
+/** Offset 0x0F4E - Reserved
**/
- UINT8 Reserved51[698];
+ UINT8 Reserved52[122];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -877,11 +881,11 @@ typedef struct { **/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x1200
+/** Offset 0x0FC8
**/
- UINT8 UnusedUpdSpace45[6];
+ UINT8 UnusedUpdSpace43[6];
-/** Offset 0x1206
+/** Offset 0x0FCE
**/
UINT16 UpdTerminator;
} FSPS_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 816ce06f8c..31047af38a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -4,7 +4,7 @@ data hobs. @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR> + Copyright (c) 1999 - 2021, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -24,10 +24,8 @@ extern EFI_GUID gSiMemoryS3DataGuid; extern EFI_GUID gSiMemoryInfoDataGuid; extern EFI_GUID gSiMemoryPlatformDataGuid; -#define MAX_TRACE_CACHE_TYPE 3 - -#define MAX_NODE 1 -#define MAX_CH 2 +#define MAX_NODE 2 +#define MAX_CH 4 #define MAX_DIMM 2 /// @@ -153,6 +151,9 @@ typedef enum { #define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + // // DIMM timings // @@ -243,10 +244,11 @@ typedef struct { UINT32 TotalPhysicalMemorySize; UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; + UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 UINT8 RefClk; UINT32 VddVoltage[MAX_PROFILE_NUM]; CONTROLLER_INFO Controller[MAX_NODE]; + UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 } MEMORY_INFO_DATA_HOB; /** @@ -265,21 +267,12 @@ typedef struct { UINT32 TsegBase; UINT32 PrmrrSize; UINT64 PrmrrBase; - UINT32 PramSize; - UINT64 PramBase; - UINT64 DismLimit; - UINT64 DismBase; UINT32 GttBase; UINT32 MmioSize; UINT32 PciEBaseAddress; -// -// CPU:RestrictedBegin -// - UINT32 SharedMailboxBase; -// -// CPU:RestrictedEnd -// PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; } MEMORY_PLATFORM_DATA; typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 35cc43bcbb..909ba36708 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -1304,9 +1304,14 @@ typedef struct { **/ UINT8 IsTPMPresence; -/** Offset 0x0389 - Reserved +/** Offset 0x0389 - ConfigTdpLevel + Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ - UINT8 Reserved17[6]; + UINT8 ConfigTdpLevel; + +/** Offset 0x038A - Reserved +**/ + UINT8 Reserved17[5]; /** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. |