diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/samsung/exynos5420/clk.h | 2 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/clock.c | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index a4e538d370..b37c076582 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -33,6 +33,8 @@ enum periph_id; #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 enum pll_src_bit { EXYNOS_SRC_CPLL = 1, diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index ed5b102d94..b8e27ff5f0 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -103,6 +103,12 @@ unsigned long get_pll_clk(int pllreg) case SPLL: r = readl(&clk->spll_con0); break; + case CPLL: + r = readl(&clk->cpll_con0); + break; + case DPLL: + r = readl(&clk->dpll_con0); + break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); return 0; |