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-rw-r--r--src/arch/x86/Makefile.inc6
-rw-r--r--src/pc80/Makefile.inc6
-rw-r--r--src/southbridge/intel/sch/Makefile.inc2
3 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index c9a62c926e..04e613f4af 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -27,9 +27,9 @@ subdirs-y += smp
OPTION_TABLE_H:=
ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
-cbfs-files-y += $(obj)/cmos_layout.bin
-$(obj)/cmos_layout.bin-name = cmos_layout.bin
-$(obj)/cmos_layout.bin-type = 0x01aa
+cbfs-files-y += cmos_layout.bin
+cmos_layout.bin-file = $(obj)/cmos_layout.bin
+cmos_layout.bin-type = 0x01aa
OPTION_TABLE_H:=$(obj)/option_table.h
endif
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 659d2e225a..b82ea41336 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -10,7 +10,7 @@ subdirs-y += vga
$(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H)
$(obj)/pc80/mc146818rtc_early.romstage.o : $(OPTION_TABLE_H)
-cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += $(CONFIG_CMOS_DEFAULT_FILE)
-$(CONFIG_CMOS_DEFAULT_FILE)-name := cmos.default
-$(CONFIG_CMOS_DEFAULT_FILE)-type := 0xaa
+cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default
+cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE)
+cmos.default-type = 0xaa
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc
index 05f45ebe34..5d829dd31f 100644
--- a/src/southbridge/intel/sch/Makefile.inc
+++ b/src/southbridge/intel/sch/Makefile.inc
@@ -37,6 +37,6 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c
# We don't ship that, but booting without it is bound to fail
cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
-cmc.bin-name := $(CONFIG_CMC_FILE)
+cmc.bin-file := $(CONFIG_CMC_FILE)
cmc.bin-type := 0xaa
cmc.bin-position := 0xfffd0000