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-rw-r--r--src/mainboard/asrock/e350m1/romstage.c198
-rw-r--r--src/southbridge/amd/cimx_wrapper/sb800/bootblock.c63
2 files changed, 130 insertions, 131 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 4b45caf6e9..7d25ec1d38 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -44,110 +44,110 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- u32 val;
- u8 reg8;
-
- // all cores: allow caching of flash chip code and data
- // (there are no cache-as-ram reliability concerns with family 14h)
- __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
-
- // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
- __writemsr (0xc0010062, 0);
-
- // early enable of PrefetchEnSPIFromHost
- if (boot_cpu())
- {
- __outdword (0xcf8, 0x8000a3b8);
- __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
- }
-
- // early enable of SPI 33 MHz fast mode read
- if (boot_cpu())
- {
- volatile u32 *spiBase = (void *) 0xa0000000;
- u32 save;
- __outdword (0xcf8, 0x8000a3a0);
- save = __indword (0xcfc);
- __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
- spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
- spiBase [0] |= 1 << 18; // fast read enable
- __outdword (0xcfc, save); // clear temp base
- }
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- sb_poweron_init();
-
- post_code(0x31);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- }
+ u32 val;
+ u8 reg8;
+
+ // all cores: allow caching of flash chip code and data
+ // (there are no cache-as-ram reliability concerns with family 14h)
+ __writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+ __writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+ __writemsr(0xc0010062, 0);
+
+ // early enable of PrefetchEnSPIFromHost
+ if (boot_cpu()) {
+ __outdword(0xcf8, 0x8000a3b8);
+ __outdword(0xcfc, __indword(0xcfc) | 1 << 24);
+ }
+ // early enable of SPI 33 MHz fast mode read
+ if (boot_cpu()) {
+ volatile u32 *spiBase = (void *)0xa0000000;
+ u32 save;
+ __outdword(0xcf8, 0x8000a3a0);
+ save = __indword(0xcfc);
+ __outdword(0xcfc, (u32) spiBase | 2); // set temp MMIO base
+ spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14);
+ spiBase[0] |= 1 << 18; // fast read enable
+ __outdword(0xcfc, save); // clear temp base
+ }
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ sb_poweron_init();
+
+ post_code(0x31);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ }
//reg8 = pmio_read(0x24);
- outb(0x24, 0xCD6);
- reg8 = inb(0xCD7);
+ outb(0x24, 0xCD6);
+ reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
//pmio_write(0x24, reg8);
outb(0x24, 0xCD6);
outb(reg8, 0xCD7);
- *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- // Load MPB
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
- post_code(0x35);
- val = agesawrapper_amdinitmmio();
-
- post_code(0x37);
- val = agesawrapper_amdinitreset();
- if(val) {
- printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
- }
-
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
- post_code(0x39);
- val = agesawrapper_amdinitearly ();
- if(val) {
- printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
- }
- printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
-
- post_code(0x40);
- val = agesawrapper_amdinitpost ();
- if(val) {
- printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
- }
- printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
-
- post_code(0x41);
- val = agesawrapper_amdinitenv ();
- if(val) {
- printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
- }
- printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
-
- /* Initialize i8259 pic */
- post_code(0x41);
- setup_i8259 ();
-
- /* Initialize i8254 timers */
- post_code(0x42);
- setup_i8254 ();
-
- post_code(0x50);
- copy_and_run(0);
-
- post_code(0x54); // Should never see this post code.
+ *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ // Load MPB
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x35);
+ val = agesawrapper_amdinitmmio();
+
+ post_code(0x37);
+ val = agesawrapper_amdinitreset();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
+ val);
+ }
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+ post_code(0x39);
+ val = agesawrapper_amdinitearly();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
+ val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+ post_code(0x40);
+ val = agesawrapper_amdinitpost();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
+ val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+ post_code(0x41);
+ val = agesawrapper_amdinitenv();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
+ val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+ /* Initialize i8259 pic */
+ post_code(0x41);
+ setup_i8259();
+
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254();
+
+ post_code(0x50);
+ copy_and_run(0);
+
+ post_code(0x54); // Should never see this post code.
}
-
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
index 629685d689..9d8a349c6e 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
@@ -17,48 +17,47 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <arch/io.h>
#include <arch/romcc_io.h>
static void sb800_enable_rom(void)
{
- u32 word;
- u32 dword;
- device_t dev;
+ u32 word;
+ u32 dword;
+ device_t dev;
- dev = PCI_DEV(0, 0x14, 0x03);
- /* SB800 LPC Bridge 0:20:3:44h.
- * BIT6: Port Enable for serial port 0x3f8-0x3ff
- * BIT29: Port Enable for KBC port 0x60 and 0x64
- * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
- */
- dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30) ;
- /* Turn on all of LPC IO Port decode enable */
- dword = 0xffffffff;
- pci_io_write_config32(dev, 0x44, dword);
+ dev = PCI_DEV(0, 0x14, 0x03);
+ /* SB800 LPC Bridge 0:20:3:44h.
+ * BIT6: Port Enable for serial port 0x3f8-0x3ff
+ * BIT29: Port Enable for KBC port 0x60 and 0x64
+ * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+ */
+ dword = pci_io_read_config32(dev, 0x44);
+ //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ /* Turn on all of LPC IO Port decode enable */
+ dword = 0xffffffff;
+ pci_io_write_config32(dev, 0x44, dword);
- /* SB800 LPC Bridge 0:20:3:48h.
- * BIT0: Port Enable for SuperIO 0x2E-0x2F
- * BIT1: Port Enable for SuperIO 0x4E-0x4F
- * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
- * BIT6: Port Enable for RTC IO 0x70-0x73
- * BIT21: Port Enable for Port 0x80
- */
- dword = pci_io_read_config32(dev, 0x48);
- dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
- pci_io_write_config32(dev, 0x48, dword);
+ /* SB800 LPC Bridge 0:20:3:48h.
+ * BIT0: Port Enable for SuperIO 0x2E-0x2F
+ * BIT1: Port Enable for SuperIO 0x4E-0x4F
+ * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+ * BIT6: Port Enable for RTC IO 0x70-0x73
+ * BIT21: Port Enable for Port 0x80
+ */
+ dword = pci_io_read_config32(dev, 0x48);
+ dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
+ pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
- /* Set the 4MB enable bits */
- word = pci_io_read_config16(dev, 0x6c);
- word = 0xFFC0;
- pci_io_write_config16(dev, 0x6c, word);
+ /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Set the 4MB enable bits */
+ word = pci_io_read_config16(dev, 0x6c);
+ word = 0xFFC0;
+ pci_io_write_config16(dev, 0x6c, word);
}
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
- sb800_enable_rom();
+ /* Setup the rom access for 2M */
+ sb800_enable_rom();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 07:51:57 +0000