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-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h2
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c4
-rw-r--r--src/mainboard/google/eve/spd/spd.c1
-rw-r--r--src/mainboard/intel/kblrvp/spd/spd_util.c2
-rw-r--r--src/soc/intel/braswell/include/soc/pei_data.h50
-rw-r--r--src/soc/intel/braswell/include/soc/pei_wrapper.h26
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h2
-rw-r--r--src/soc/intel/skylake/Makefile.inc2
-rw-r--r--src/soc/intel/skylake/include/fsp11/soc/romstage.h2
-rw-r--r--src/soc/intel/skylake/include/soc/pei_data.h89
-rw-r--r--src/soc/intel/skylake/include/soc/pei_wrapper.h27
-rw-r--r--src/soc/intel/skylake/pei_data.c39
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c4
13 files changed, 0 insertions, 250 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 4e95dadadf..b01f11059c 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -25,13 +25,11 @@
#include <fsp/car.h>
#include <fsp/util.h>
#include <soc/intel/common/mma.h>
-#include <soc/pei_wrapper.h>
#include <soc/pm.h> /* chip_power_state */
struct romstage_params {
uint32_t fsp_version;
struct chipset_power_state *power_state;
- struct pei_data *pei_data;
void *chipset_context;
/* Fast boot and S3 resume MRC data */
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 87fd1a4c01..433e16cf13 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -41,9 +41,7 @@
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
void *top_of_stack;
- struct pei_data pei_data;
struct romstage_params params = {
- .pei_data = &pei_data,
.chipset_context = fih,
};
@@ -55,8 +53,6 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
- memset(&pei_data, 0, sizeof(pei_data));
-
/* Display parameters */
if (!CONFIG(NO_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c
index 2f365a7b5c..077bed4bf1 100644
--- a/src/mainboard/google/eve/spd/spd.c
+++ b/src/mainboard/google/eve/spd/spd.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <gpio.h>
#include <soc/gpio.h>
-#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <string.h>
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
index 10043843a2..f22dcaa3b7 100644
--- a/src/mainboard/intel/kblrvp/spd/spd_util.c
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -16,8 +16,6 @@
#include <arch/byteorder.h>
#include <stdint.h>
#include <string.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
#include "../board_id.h"
#include "spd.h"
diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h
deleted file mode 100644
index df18dc087a..0000000000
--- a/src/soc/intel/braswell/include/soc/pei_data.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * UEFI PEI wrapper
- *
- * Copyright (C) 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Google Inc. nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _PEI_DATA_H_
-#define _PEI_DATA_H_
-
-#include <types.h>
-
-#define PEI_VERSION 22
-
-#define ABI_X86 __attribute__((regparm(0)))
-
-typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
-
-struct pei_data {
- /* Chip settings */
- void *spd_data_ch0;
- void *spd_data_ch1;
- uint8_t spd_ch0_config;
- uint8_t spd_ch1_config;
-};
-
-typedef struct pei_data PEI_DATA;
-
-#endif /* _PEI_DATA_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/soc/intel/braswell/include/soc/pei_wrapper.h
deleted file mode 100644
index 3222328bef..0000000000
--- a/src/soc/intel/braswell/include/soc/pei_wrapper.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_PEI_WRAPPER_H_
-#define _SOC_PEI_WRAPPER_H_
-
-#include <soc/pei_data.h>
-
-typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
-
-void broadwell_fill_pei_data(struct pei_data *pei_data);
-void mainboard_fill_pei_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 2512430f75..633233e6c6 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -20,14 +20,12 @@
#include <stdint.h>
#include <fsp/romstage.h>
#include <fsp/util.h>
-#include <soc/pei_data.h>
#include <soc/pm.h>
void gfx_init(void);
void tco_disable(void);
void punit_init(void);
int early_spi_read_wpsr(u8 *sr);
-void mainboard_fill_spd_data(struct pei_data *pei_data);
void set_max_freq(void);
/* romstage_common.c functions */
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index ee2c928464..e9f555f13c 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -35,7 +35,6 @@ romstage-y += gspi.c
romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += me.c
-romstage-y += pei_data.c
romstage-y += pmc.c
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
@@ -58,7 +57,6 @@ ramstage-y += lpc.c
ramstage-y += me.c
ramstage-y += memmap.c
ramstage-y += p2sb.c
-ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index 36825f7aea..386931043d 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -24,6 +24,4 @@ void intel_early_me_status(void);
void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
deleted file mode 100644
index 5ea2190b8e..0000000000
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * UEFI PEI wrapper
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Google Inc. nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _PEI_DATA_H_
-#define _PEI_DATA_H_
-
-#include <types.h>
-
-#define PEI_VERSION 22
-
-#define ABI_X86 __attribute__((regparm(0)))
-
-typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
-
-struct pei_data {
- uint32_t pei_version;
-
- int ec_present;
-
- /* Console output function */
- tx_byte_func tx_byte;
-
- /*
- * DIMM SPD data for memory down configurations
- * [CHANNEL][SLOT][SPD]
- */
- uint8_t spd_data[2][2][512];
-
- /*
- * LPDDR3 DQ byte map
- * [CHANNEL][ITERATION][2]
- *
- * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
- * DQByteMap[0] - ClkDQByteMap:
- * - If clock is per rank, program to [0xFF, 0xFF]
- * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
- * - If clock is shared by 2 ranks but does not go to all bytes,
- * Entry[i] defines which DQ bytes Group i services
- * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
- * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
- * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
- * For DDR, DQByteMap[3:1] = [0xFF, 0]
- * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
- * since we have 1 CTL / rank
- * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
- * since we have 1 CA Vref
- */
- uint8_t dq_map[2][12];
-
- /*
- * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
- * [CHANNEL][MAX_BYTES]
- */
- uint8_t dqs_map[2][8];
- uint16_t RcompResistor[3];
- uint16_t RcompTarget[5];
-
- int mem_cfg_id;
-} __packed;
-
-typedef struct pei_data PEI_DATA;
-
-#endif /* _PEI_DATA_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/soc/intel/skylake/include/soc/pei_wrapper.h
deleted file mode 100644
index d53fe8b769..0000000000
--- a/src/soc/intel/skylake/include/soc/pei_wrapper.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_PEI_WRAPPER_H_
-#define _SOC_PEI_WRAPPER_H_
-
-#include <soc/pei_data.h>
-
-typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
-
-void soc_fill_pei_data(struct pei_data *pei_data);
-void mainboard_fill_pei_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c
deleted file mode 100644
index 7d314a106f..0000000000
--- a/src/soc/intel/skylake/pei_data.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/streams.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-
-#include "chip.h"
-
-static void ABI_X86 send_to_console(unsigned char b)
-{
- console_tx_byte(b);
-}
-
-void soc_fill_pei_data(struct pei_data *pei_data)
-{
- /* Set the parameters for MemoryInit */
- pei_data->pei_version = PEI_VERSION;
- pei_data->tx_byte = &send_to_console;
-}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 8ec08c2d0f..12239ae13e 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -26,7 +26,6 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/pmclib.h>
#include <soc/pci_devs.h>
-#include <soc/pei_wrapper.h>
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
@@ -44,9 +43,6 @@ void soc_pre_ram_init(struct romstage_params *params)
/* Program MCHBAR and DMIBAR */
systemagent_early_init();
- /* Prepare to initialize memory */
- soc_fill_pei_data(params->pei_data);
-
const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *const config =
dev ? dev->chip_info : NULL;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 17:14:55 +0000