diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/graysreef/romstage.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/early_init.c | 15 |
2 files changed, 4 insertions, 15 deletions
diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c index da839f41c8..bc29c0a1f2 100644 --- a/src/mainboard/intel/graysreef/romstage.c +++ b/src/mainboard/intel/graysreef/romstage.c @@ -193,6 +193,10 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); + /* + * FIXME: MCHBAR isn't setup yet. It's setup in + * haswell_early_initialization(). + */ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 4d174740f1..505fbf1125 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -139,21 +139,6 @@ static void haswell_setup_graphics(void) void haswell_early_initialization(int chipset_type) { - u32 capid0_a; - u8 reg8; - - /* Device ID Override Enable should be done very early */ - capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); - if (capid0_a & (1 << 10)) { - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == HASWELL_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); - } - /* Setup all BARs required for early PCIe and raminit */ haswell_setup_bars(); |