diff options
Diffstat (limited to 'src')
154 files changed, 2484 insertions, 405 deletions
diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index 7f16c5b6be..37317815ea 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -23,7 +23,7 @@ config BOARD_ASUS_MEW_AM select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb index 2ca0e68cda..016f6dbc51 100644 --- a/src/mainboard/asus/mew-am/devicetree.cb +++ b/src/mainboard/asus/mew-am/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index a7f74c42f4..8751e0ec28 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 616fb4bdde..f5cefd0df8 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -23,7 +23,7 @@ config BOARD_ASUS_MEW_VM select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index 0dc4b6f468..a5415a2bfe 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/i82810 device pci 1.0 on # Onboard Video # device pci 1.0 on end end - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index d9473a5880..703cd87de5 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -38,7 +38,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig index 3f14662be4..aeb14a008a 100644 --- a/src/mainboard/dell/s1850/Kconfig +++ b/src/mainboard/dell/s1850/Kconfig @@ -3,7 +3,7 @@ config BOARD_DELL_S1850 select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC8374 select ROMCC diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb index 4e93a3aefb..ab95e54a7b 100644 --- a/src/mainboard/dell/s1850/devicetree.cb +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 5f62ce80a8..952c37c1cf 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/pc8374_early_init.c" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index fd109e9d64..58b9f6f034 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -3,7 +3,7 @@ config BOARD_DIGITALLOGIC_ADL855PC select ARCH_X86 select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I855 - select SOUTHBRIDGE_INTEL_I82801DBM + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb index 0f600ac8f1..6846b4e59c 100644 --- a/src/mainboard/digitallogic/adl855pc/devicetree.cb +++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/intel/i855 device pci_domain 0 on device pci 0.0 on end device pci 1.0 on end - chip southbridge/intel/i82801dbm + chip southbridge/intel/i82801dx # pci 11.0 on end # pci 11.1 on end # pci 11.2 on end diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 16d9195d38..8903876057 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -16,7 +16,8 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" #if 0 diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 676d3eb5d8..755b3ac904 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -26,7 +26,7 @@ config BOARD_HP_E_VECTRA_P2706T select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index 82209d4317..7ea1f299e7 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 50d8c447b4..f2c643c854 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -37,7 +37,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 7a17ea7782..fc70befafa 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -4,7 +4,7 @@ config BOARD_INTEL_JARRELL select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_PXHD - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_NSC_PC87427 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb index e4cdbdeacb..32f70e3e85 100644 --- a/src/mainboard/intel/jarrell/devicetree.cb +++ b/src/mainboard/intel/jarrell/devicetree.cb @@ -17,7 +17,7 @@ chip northbridge/intel/e7520 end end device pci 06.0 on end - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 462bd8e25d..d7b1bf40c7 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig index 72c1d94fb2..d2a9f4779f 100644 --- a/src/mainboard/intel/xe7501devkit/Kconfig +++ b/src/mainboard/intel/xe7501devkit/Kconfig @@ -4,7 +4,7 @@ config BOARD_INTEL_XE7501DEVKIT select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801CA + select SOUTHBRIDGE_INTEL_I82801CX select SUPERIO_SMSC_LPC47B272 select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb index 00ed4eca84..efa0d88216 100644 --- a/src/mainboard/intel/xe7501devkit/devicetree.cb +++ b/src/mainboard/intel/xe7501devkit/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/intel/e7501 end end device pci 6.0 on end # E7501 Power management registers? (undocumented) - chip southbridge/intel/i82801ca + chip southbridge/intel/i82801cx device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) diff --git a/src/mainboard/intel/xe7501devkit/failover.c b/src/mainboard/intel/xe7501devkit/failover.c index 7aa9e405ed..9daf3b27d6 100644 --- a/src/mainboard/intel/xe7501devkit/failover.c +++ b/src/mainboard/intel/xe7501devkit/failover.c @@ -7,7 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" -#include "southbridge/intel/i82801ca/cmos_failover.c" +#include "southbridge/intel/i82801cx/cmos_failover.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/reset_test.c" diff --git a/src/mainboard/intel/xe7501devkit/reset.c b/src/mainboard/intel/xe7501devkit/reset.c index 8feaac64e5..7c8a729f5e 100644 --- a/src/mainboard/intel/xe7501devkit/reset.c +++ b/src/mainboard/intel/xe7501devkit/reset.c @@ -1,6 +1,6 @@ -void i82801ca_hard_reset(void); +void i82801cx_hard_reset(void); void hard_reset(void) { - i82801ca_hard_reset(); + i82801cx_hard_reset(); } diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 7269fa8d43..0bedaf9431 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -14,7 +14,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c" +#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c" diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index 20559b24b0..64937ce1c5 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -23,7 +23,7 @@ config BOARD_MITAC_6513WU select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb index 0369775c07..3cba778e10 100644 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ b/src/mainboard/mitac/6513wu/devicetree.cb @@ -27,7 +27,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" register "pirqc_routing" = "0x09" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index 6222ea8721..daa2e9660c 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index 16662da312..a6af3260d0 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -23,7 +23,7 @@ config BOARD_MSI_MS_6178 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb index baa0e040b8..4863957714 100644 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ b/src/mainboard/msi/ms6178/devicetree.cb @@ -27,7 +27,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index a320dde763..976d24a56c 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -35,7 +35,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index fa3532d028..7b818b45e1 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -23,7 +23,7 @@ config BOARD_NEC_POWERMATE_2000 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb index 0cb7e328b5..52cae5823c 100644 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ b/src/mainboard/nec/powermate2000/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/i82810 # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 701e312967..c923f9943a 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -35,7 +35,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c" diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index 1be2a752dc..cdca002ea3 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -3,7 +3,7 @@ config BOARD_RCA_RM4100 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82830 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb index 1844932114..2b04ad7d3a 100644 --- a/src/mainboard/rca/rm4100/devicetree.cb +++ b/src/mainboard/rca/rm4100/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801dx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index d51bc90e78..a27b7bb327 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -34,8 +34,8 @@ static void mb_gpio_init(void) dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); /* Set GPIO23 to high, this enables the LAN controller. */ udelay(10); diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 2f3892e3a0..cf7464442d 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -35,8 +35,8 @@ #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801xx/i82801xx.h" -#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -44,7 +44,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -127,4 +127,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ -}
\ No newline at end of file +} diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig index eb3330c023..a456abea8a 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig @@ -3,7 +3,7 @@ config BOARD_SUPERMICRO_X6DHE_G2 select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC87427 select ROMCC diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index 4bb720707c..e621594b93 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/e7520 # MCH device pnp 00.3 off end end device pci_domain 0 on - chip southbridge/intel/i82801er # ICH5R + chip southbridge/intel/i82801ex # ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 4e9c1e270b..f38f4e9b07 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig index 759e6d14ba..56653adc9b 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig @@ -3,7 +3,7 @@ config BOARD_SUPERMICRO_X6DHR_IG select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 8a82ed7c40..921c54fff5 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 314cc70325..0fd77d3a56 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig index e25f8bf7d0..126739be10 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig @@ -3,7 +3,7 @@ config BOARD_SUPERMICRO_X6DHR_IG2 select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index ab56509fd9..318d492b9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 3cb41ad037..7a9b696198 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index 6a87d0cfc8..b78a20e388 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -3,7 +3,7 @@ config BOARD_THOMSON_IP1000 select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82830 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE @@ -28,4 +28,4 @@ config HAVE_OPTION_TABLE config IRQ_SLOT_COUNT int default 7 - depends on BOARD_THOMSON_IP1000
\ No newline at end of file + depends on BOARD_THOMSON_IP1000 diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb index 7f5c42a8cf..f38c1c3e67 100644 --- a/src/mainboard/thomson/ip1000/devicetree.cb +++ b/src/mainboard/thomson/ip1000/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801dx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index ae2cd8eabf..6a69bb539d 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -34,8 +34,8 @@ static void mb_gpio_init(void) dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); /* Set GPIO23 to high, this enables the LAN controller. */ udelay(10); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 2f3892e3a0..cf7464442d 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -35,8 +35,8 @@ #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801xx/i82801xx.h" -#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -44,7 +44,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -127,4 +127,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ -}
\ No newline at end of file +} diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index 8d516fe660..0c3f8a573d 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -4,7 +4,7 @@ config BOARD_TYAN_S2735 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index 0fdd57814a..8ad5e0ecac 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -14,7 +14,7 @@ chip northbridge/intel/e7501 end end device pci 6.0 on end - chip southbridge/intel/i82801er + chip southbridge/intel/i82801ex device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end diff --git a/src/mainboard/tyan/s2735/reset.c b/src/mainboard/tyan/s2735/reset.c index 371920dca2..2601faa676 100644 --- a/src/mainboard/tyan/s2735/reset.c +++ b/src/mainboard/tyan/s2735/reset.c @@ -1,7 +1,7 @@ -void i82801er_hard_reset(void); +void i82801ex_hard_reset(void); /* FIXME: There's another hard_reset() in romstage.c. Why? */ void hard_reset(void) { - i82801er_hard_reset(); + i82801ex_hard_reset(); } diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 99a38a9fb3..5e2678a047 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -25,7 +25,7 @@ static void post_code(uint8_t value) { } #endif -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" @@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_USE_FALLBACK_IMAGE == 1 -#include "southbridge/intel/i82801er/cmos_failover.c" +#include "southbridge/intel/i82801ex/cmos_failover.c" void real_main(unsigned long bist); diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig index 92be28623d..61cd79696b 100644 --- a/src/southbridge/intel/Kconfig +++ b/src/southbridge/intel/Kconfig @@ -1,10 +1,11 @@ source src/southbridge/intel/esb6300/Kconfig source src/southbridge/intel/i3100/Kconfig source src/southbridge/intel/i82371eb/Kconfig -source src/southbridge/intel/i82801ca/Kconfig -source src/southbridge/intel/i82801dbm/Kconfig -source src/southbridge/intel/i82801er/Kconfig +source src/southbridge/intel/i82801ax/Kconfig +source src/southbridge/intel/i82801bx/Kconfig +source src/southbridge/intel/i82801cx/Kconfig +source src/southbridge/intel/i82801dx/Kconfig +source src/southbridge/intel/i82801ex/Kconfig source src/southbridge/intel/i82801gx/Kconfig -source src/southbridge/intel/i82801xx/Kconfig source src/southbridge/intel/i82870/Kconfig source src/southbridge/intel/pxhd/Kconfig diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc index e53450f95f..12ba7108ba 100644 --- a/src/southbridge/intel/Makefile.inc +++ b/src/southbridge/intel/Makefile.inc @@ -1,11 +1,12 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CA) += i82801ca -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DBM) += i82801dbm -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801ER) += i82801er +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd diff --git a/src/southbridge/intel/i82801xx/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index f86c65f2f3..25e2c3aa5f 100644 --- a/src/southbridge/intel/i82801xx/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config SOUTHBRIDGE_INTEL_I82801XX +config SOUTHBRIDGE_INTEL_I82801AX bool diff --git a/src/southbridge/intel/i82801xx/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc index 875141f494..3e66f04569 100644 --- a/src/southbridge/intel/i82801xx/Makefile.inc +++ b/src/southbridge/intel/i82801ax/Makefile.inc @@ -18,21 +18,21 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += i82801xx.o -driver-y += i82801xx_ac97.o -driver-y += i82801xx_ide.o -driver-y += i82801xx_lpc.o -driver-y += i82801xx_nic.o -driver-y += i82801xx_pci.o -driver-y += i82801xx_sata.o -# driver-y += i82801xx_smbus.o -driver-y += i82801xx_usb.o -driver-y += i82801xx_usb_ehci.o +driver-y += i82801ax.o +driver-y += i82801ax_ac97.o +driver-y += i82801ax_ide.o +driver-y += i82801ax_lpc.o +driver-y += i82801ax_nic.o +driver-y += i82801ax_pci.o +driver-y += i82801ax_sata.o +# driver-y += i82801ax_smbus.o +driver-y += i82801ax_usb.o +driver-y += i82801ax_usb_ehci.o -obj-y += i82801xx_reset.o -obj-y += i82801xx_watchdog.o +obj-y += i82801ax_reset.o +obj-y += i82801ax_watchdog.o # TODO: What about cmos_failover.c? -# TODO: Fix and enable i82801xx_smbus.o later. +# TODO: Fix and enable i82801ax_smbus.o later. diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801ax/chip.h index 443df451c3..90bbfcb7c5 100644 --- a/src/southbridge/intel/i82801xx/chip.h +++ b/src/southbridge/intel/i82801ax/chip.h @@ -19,7 +19,7 @@ */ /* - * The i82801xx code currently supports: + * The i82801ax code currently supports: * - 82801AA * - 82801AB * - 82801BA @@ -32,10 +32,10 @@ * This code should NOT be used for ICH6 and later versions. */ -#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H -#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H +#ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H -struct southbridge_intel_i82801xx_config { +struct southbridge_intel_i82801ax_config { /** * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -53,6 +53,6 @@ struct southbridge_intel_i82801xx_config { uint8_t ide1_enable; }; -extern struct chip_operations southbridge_intel_i82801xx_ops; +extern struct chip_operations southbridge_intel_i82801ax_ops; #endif diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801ax/cmos_failover.c index 9307f40305..a770005b73 100644 --- a/src/southbridge/intel/i82801xx/cmos_failover.c +++ b/src/southbridge/intel/i82801ax/cmos_failover.c @@ -16,7 +16,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "i82801xx.h" +#include "i82801ax.h" static void check_cmos_failed(void) { diff --git a/src/southbridge/intel/i82801ax/i82801ax.c b/src/southbridge/intel/i82801ax/i82801ax.c new file mode 100644 index 0000000000..ea4cda67eb --- /dev/null +++ b/src/southbridge/intel/i82801ax/i82801ax.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design) + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include "i82801ax.h" + +void i82801ax_enable(device_t dev) +{ + unsigned int index = 0; + uint16_t cur_disable_mask, new_disable_mask; + + /* All 82801xx devices should be on bus 0. */ + unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC + device_t lpc_dev = dev_find_slot(0, devfn); // 0 + if (!lpc_dev) + return; + + /* We're going to assume, perhaps incorrectly, that if a function + * exists it can be disabled. Workarounds for ICH variants that don't + * follow this should be done by checking the device ID. + */ + if (PCI_SLOT(dev->path.pci.devfn) == 31) { + index = PCI_FUNC(dev->path.pci.devfn); + } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { + index = 8 + PCI_FUNC(dev->path.pci.devfn); + } + + /* Function 0 is a bit of an exception. */ + if (index == 0) { + index = 14; + } + + cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); + new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */ + if (!dev->enabled) { + new_disable_mask |= (1 << index); /* Disable it, if desired. */ + } + if (new_disable_mask != cur_disable_mask) { + pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); + } +} + +struct chip_operations southbridge_intel_i82801ax_ops = { + CHIP_NAME("Intel ICH/ICH0 (82801AA/AB) Series Southbridge") + .enable_dev = i82801ax_enable, +}; diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801ax/i82801ax.h index d90cc32b37..f9b4977c67 100644 --- a/src/southbridge/intel/i82801xx/i82801xx.h +++ b/src/southbridge/intel/i82801ax/i82801ax.h @@ -18,12 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H -#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H +#ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H +#define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H #if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" -extern void i82801xx_enable(device_t dev); +extern void i82801ax_enable(device_t dev); #endif #define PCI_DMA_CFG 0x90 @@ -117,4 +117,4 @@ extern void i82801xx_enable(device_t dev); /* HPET, if present */ #define HPET_ADDR 0xfed0000 -#endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */ diff --git a/src/southbridge/intel/i82801xx/i82801xx_ac97.c b/src/southbridge/intel/i82801ax/i82801ax_ac97.c index ace04ffaeb..7ef4142d11 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_ac97.c +++ b/src/southbridge/intel/i82801ax/i82801ax_ac97.c @@ -25,7 +25,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h" static struct device_operations ac97_ops = { .read_resources = pci_dev_read_resources, @@ -33,7 +33,7 @@ static struct device_operations ac97_ops = { .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, }; /* 82801AA (ICH) */ diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c index 3ae91d7943..abcf9c60dc 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c @@ -18,7 +18,7 @@ * */ -static void i82801xx_halt_tco_timer(void) +static void i82801ax_halt_tco_timer(void) { device_t dev; uint16_t halt_tco_timer; diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c index d1bd051be0..d80c29c159 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c +++ b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c @@ -21,8 +21,8 @@ */ #include <device/pci_ids.h> -#include "i82801xx.h" -#include "i82801xx_smbus.h" +#include "i82801ax.h" +#include "i82801ax_smbus.h" static void enable_smbus(void) { diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c index 4173cc6a75..c13fb4d34a 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_ide.c +++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c @@ -25,9 +25,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h" -typedef struct southbridge_intel_i82801xx_config config_t; +typedef struct southbridge_intel_i82801ax_config config_t; static void ide_init(struct device *dev) { @@ -67,7 +67,7 @@ static struct device_operations ide_ops = { .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, }; /* 82801AA */ diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index f7fae37cb3..590f057ef7 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -30,13 +30,13 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801xx.h" +#include "i82801ax.h" #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ #define NMI_OFF 0 -typedef struct southbridge_intel_i82801xx_config config_t; +typedef struct southbridge_intel_i82801ax_config config_t; /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -74,7 +74,7 @@ typedef struct southbridge_intel_i82801xx_config config_t; * specific IRQ values in your mainboards Config.lb. */ -void i82801xx_enable_apic(struct device *dev) +void i82801ax_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; @@ -108,7 +108,7 @@ void i82801xx_enable_apic(struct device *dev) *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } -void i82801xx_enable_serial_irqs(struct device *dev) +void i82801ax_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, @@ -118,7 +118,7 @@ void i82801xx_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801ax_pirq_init(device_t dev, uint16_t ich_model) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -176,7 +176,7 @@ static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) } } -static void i82801xx_power_options(device_t dev) +static void i82801ax_power_options(device_t dev) { uint8_t byte; int pwr_on = -1; @@ -220,7 +220,7 @@ static void gpio_init(device_t dev, uint16_t ich_model) } } -void i82801xx_rtc_init(struct device *dev) +void i82801ax_rtc_init(struct device *dev) { uint8_t reg8; uint32_t reg32; @@ -240,7 +240,7 @@ void i82801xx_rtc_init(struct device *dev) pci_write_config8(dev, RTC_CONF, 0x04); } -void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask) +void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) { uint16_t reg16; int i; @@ -255,7 +255,7 @@ void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -302,36 +302,36 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - i82801xx_enable_apic(dev); + i82801ax_enable_apic(dev); - i82801xx_enable_serial_irqs(dev); + i82801ax_enable_serial_irqs(dev); /* Setup the PIRQ. */ - i82801xx_pirq_init(dev, ich_model); + i82801ax_pirq_init(dev, ich_model); /* Setup power options. */ - i82801xx_power_options(dev); + i82801ax_power_options(dev); /* Set the state of the GPIO lines. */ gpio_init(dev, ich_model); /* Initialize the real time clock. */ - i82801xx_rtc_init(dev); + i82801ax_rtc_init(dev); /* Route DMA. */ - i82801xx_lpc_route_dma(dev, 0xff); + i82801ax_lpc_route_dma(dev, 0xff); /* Initialize ISA DMA. */ isa_dma_init(); /* Setup decode ports and LPC I/F enables. */ - i82801xx_lpc_decode_en(dev, ich_model); + i82801ax_lpc_decode_en(dev, ich_model); /* Initialize the High Precision Event Timers, if present. */ enable_hpet(dev); } -static void i82801xx_lpc_read_resources(device_t dev) +static void i82801ax_lpc_read_resources(device_t dev) { struct resource *res; @@ -357,19 +357,19 @@ static void i82801xx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801xx_lpc_enable_resources(device_t dev) +static void i82801ax_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); } static struct device_operations lpc_ops = { - .read_resources = i82801xx_lpc_read_resources, + .read_resources = i82801ax_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801xx_lpc_enable_resources, + .enable_resources = i82801ax_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801xx_enable, + .enable = i82801ax_enable, }; static const struct pci_driver i82801aa_lpc __pci_driver = { diff --git a/src/southbridge/intel/i82801xx/i82801xx_nic.c b/src/southbridge/intel/i82801ax/i82801ax_nic.c index 3728d28bd7..3728d28bd7 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_nic.c +++ b/src/southbridge/intel/i82801ax/i82801ax_nic.c diff --git a/src/southbridge/intel/i82801xx/i82801xx_pci.c b/src/southbridge/intel/i82801ax/i82801ax_pci.c index 1f01e5dc46..1f01e5dc46 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_pci.c +++ b/src/southbridge/intel/i82801ax/i82801ax_pci.c diff --git a/src/southbridge/intel/i82801xx/i82801xx_reset.c b/src/southbridge/intel/i82801ax/i82801ax_reset.c index 239a727968..239a727968 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_reset.c +++ b/src/southbridge/intel/i82801ax/i82801ax_reset.c diff --git a/src/southbridge/intel/i82801xx/i82801xx_sata.c b/src/southbridge/intel/i82801ax/i82801ax_sata.c index de8b3b02cf..5d6d6f204e 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_sata.c +++ b/src/southbridge/intel/i82801ax/i82801ax_sata.c @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h" /* TODO: Set dynamically, if the user only wants one SATA channel or none * at all. @@ -64,7 +64,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, }; /* 82801EB */ diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_smbus.c index 1608650be5..739cfdb988 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_smbus.c +++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.c @@ -24,7 +24,7 @@ #include <smbus.h> #include <pci.h> #include <arch/io.h> -#include "i82801xx.h" +#include "i82801ax.h" #include "i82801_smbus.h" static int smbus_read_byte(struct bus *bus, device_t dev, u8 address) diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h index 7a7850835b..7a7850835b 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_smbus.h +++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.h diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb.c b/src/southbridge/intel/i82801ax/i82801ax_usb.c index 74bbbee17c..a1d36e8600 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_usb.c +++ b/src/southbridge/intel/i82801ax/i82801ax_usb.c @@ -24,7 +24,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h" static void usb_init(struct device *dev) { @@ -37,7 +37,7 @@ static struct device_operations usb_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, }; /* 82801AA (ICH) */ diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c b/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c index 032f19863b..a3f7e7c9fd 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c +++ b/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h" static void usb_ehci_init(struct device *dev) { @@ -65,7 +65,7 @@ static struct device_operations usb_ehci_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801xx/i82801xx_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c index aea10e1c7b..aea10e1c7b 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_watchdog.c +++ b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig new file mode 100644 index 0000000000..682b725af0 --- /dev/null +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_INTEL_I82801BX + bool + diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc new file mode 100644 index 0000000000..3d7d61836a --- /dev/null +++ b/src/southbridge/intel/i82801bx/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += i82801bx.o +driver-y += i82801bx_ac97.o +driver-y += i82801bx_ide.o +driver-y += i82801bx_lpc.o +driver-y += i82801bx_nic.o +driver-y += i82801bx_pci.o +driver-y += i82801bx_sata.o +# driver-y += i82801bx_smbus.o +driver-y += i82801bx_usb.o +driver-y += i82801bx_usb_ehci.o + +obj-y += i82801bx_reset.o +obj-y += i82801bx_watchdog.o + +# TODO: What about cmos_failover.c? + +# TODO: Fix and enable i82801bx_smbus.o later. + diff --git a/src/southbridge/intel/i82801bx/chip.h b/src/southbridge/intel/i82801bx/chip.h new file mode 100644 index 0000000000..a168e8502e --- /dev/null +++ b/src/southbridge/intel/i82801bx/chip.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The i82801bx code currently supports: + * - 82801AA + * - 82801AB + * - 82801BA + * - 82801CA + * - 82801DB + * - 82801DBM + * - 82801EB + * - 82801ER + * + * This code should NOT be used for ICH6 and later versions. + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801BX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801BX_CHIP_H + +struct southbridge_intel_i82801bx_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + uint8_t ide0_enable; + uint8_t ide1_enable; +}; + +extern struct chip_operations southbridge_intel_i82801bx_ops; + +#endif diff --git a/src/southbridge/intel/i82801bx/cmos_failover.c b/src/southbridge/intel/i82801bx/cmos_failover.c new file mode 100644 index 0000000000..d2e4081da0 --- /dev/null +++ b/src/southbridge/intel/i82801bx/cmos_failover.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i82801bx.h" + +static void check_cmos_failed(void) +{ + uint8_t byte; + byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (byte & RTC_FAILED) { + //clear bit 1 and bit 2 + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + byte |= CONFIG_MAX_REBOOT_CNT << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } +} diff --git a/src/southbridge/intel/i82801xx/i82801xx.c b/src/southbridge/intel/i82801bx/i82801bx.c index 385b122d47..2352723935 100644 --- a/src/southbridge/intel/i82801xx/i82801xx.c +++ b/src/southbridge/intel/i82801bx/i82801bx.c @@ -23,9 +23,9 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include "i82801xx.h" +#include "i82801bx.h" -void i82801xx_enable(device_t dev) +void i82801bx_enable(device_t dev) { unsigned int index = 0; uint16_t cur_disable_mask, new_disable_mask; @@ -61,7 +61,7 @@ void i82801xx_enable(device_t dev) } } -struct chip_operations southbridge_intel_i82801xx_ops = { - CHIP_NAME("Intel 82801 Series Southbridge") - .enable_dev = i82801xx_enable, +struct chip_operations southbridge_intel_i82801bx_ops = { + CHIP_NAME("Intel ICH2 (82801Bx) Series Southbridge") + .enable_dev = i82801bx_enable, }; diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h new file mode 100644 index 0000000000..9705beed36 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H +#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H + +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#include "chip.h" +extern void i82801bx_enable(device_t dev); +#endif + +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */ +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0x4E +#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ +#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */ +#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */ +#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */ + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + +#define FUNC_DIS 0xF2 + +#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */ +#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */ +#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */ + +#define SBUS_NUM 0x19 +#define SUB_BUS_NUM 0x1A +#define SMLT 0x1B +#define IOBASE 0x1C +#define IOLIM 0x1D +#define MEMBASE 0x20 +#define MEMLIM 0x22 +#define CNF 0x50 +#define MTT 0x70 +#define PCI_MAST_STS 0x82 + +#define TCOBASE 0x60 /* TCO Base Address Register */ +#define TCO1_CNT 0x08 /* TCO1 Control Register */ + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +/* PCI Configuration Space (D31:F1) */ +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ + +/* IDE_TIM bits */ +#define IDE_DECODE_ENABLE (1 << 15) + +/* PCI Configuration Space (D31:F3) */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. + * TODO: Does it matter where we put the SMBus IO base, as long as we keep + * consistent and don't interfere with anything else? + */ +/* #define SMBUS_IO_BASE 0x1000 */ +#define SMBUS_IO_BASE 0x0f00 + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + +/* HPET, if present */ +#define HPET_ADDR 0xfed0000 + +#endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */ + diff --git a/src/southbridge/intel/i82801bx/i82801bx_ac97.c b/src/southbridge/intel/i82801bx/i82801bx_ac97.c new file mode 100644 index 0000000000..2966d204e4 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_ac97.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with AC97 audio/modem. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801bx.h" + +static struct device_operations ac97_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801AA (ICH) */ +static const struct pci_driver i82801aa_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO, +}; + +static const struct pci_driver i82801aa_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM, +}; + +/* 82801AB (ICH0) */ +static const struct pci_driver i82801ab_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO, +}; + +static const struct pci_driver i82801ab_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO, +}; + +static const struct pci_driver i82801ba_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM, +}; + +/* 82801CA/CAM (ICH3-S/ICH3-M) */ +static const struct pci_driver i82801ca_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO, +}; + +static const struct pci_driver i82801ca_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM, +}; + +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ +static const struct pci_driver i82801db_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO, +}; + +static const struct pci_driver i82801db_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM, +}; + +/* 82801EB/ER (ICH5/ICH5R) */ +static const struct pci_driver i82801eb_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_AC97_AUDIO, +}; + +static const struct pci_driver i82801eb_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_AC97_MODEM, +}; + +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ +static const struct pci_driver i82801fb_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_AUDIO, +}; + +static const struct pci_driver i82801fb_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c new file mode 100644 index 0000000000..b64c3d89f8 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +static void i82801bx_halt_tco_timer(void) +{ + device_t dev; + uint16_t halt_tco_timer; + + /* Set the LPC device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Temporarily set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + + /* Temporarily enable ACPI I/O. */ + pci_write_config8(dev, ACPI_CNTL, 0x10); + + /* Halt the TCO timer, preventing SMI and automatic reboot */ + outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT); + + /* Disable ACPI I/O. */ + pci_write_config8(dev, ACPI_CNTL, 0x00); +} diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c new file mode 100644 index 0000000000..b8ec9b7528 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer) + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include "i82801bx.h" +#include "i82801bx_smbus.h" + +static void enable_smbus(void) +{ + device_t dev; + uint16_t device_id; + + /* Set the SMBus device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device. */ + device_id = pci_read_config16(dev, 0x2); + + /* Clear bits 7-4 (the only bits that vary between models). */ + device_id &= 0xff0f; + + if (device_id != 0x2403) { + die("Device not found, Corey probably screwed up!"); + } + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + print_debug("SMBus controller enabled\r\n"); +} + +static inline int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(device, address); +} + +static void smbus_write_byte(unsigned device, unsigned address, + unsigned char val) +{ + print_err("Unimplemented smbus_write_byte() called\r\n"); + return; +} + +static inline int smbus_write_block(unsigned device, unsigned length, + unsigned cmd, unsigned data1, + unsigned data2) +{ + return do_smbus_write_block(device, length, cmd, data1, data2); +} diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c new file mode 100644 index 0000000000..9bfab00399 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer) + * Copyright (C) 2005 Digital Design Corporation + * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801bx.h" + +typedef struct southbridge_intel_i82801bx_config config_t; + +static void ide_init(struct device *dev) +{ + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + /* TODO: Needs to be tested for compatibility with ICH5(R). */ + /* Enable IDE devices so the Linux IDE driver will work. */ + uint16_t ideTimingConfig; + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (!config || config->ide0_enable) { + /* Enable primary IDE interface. */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk_debug("IDE0: Primary IDE interface is enabled\n"); + } else { + printk_info("IDE0: Primary IDE interface is disabled\n"); + } + pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (!config || config->ide1_enable) { + /* Enable secondary IDE interface. */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk_debug("IDE1: Secondary IDE interface is enabled\n"); + } else { + printk_info("IDE1: Secondary IDE interface is disabled\n"); + } + pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801AA */ +static const struct pci_driver i82801aa_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2411, +}; + +/* 82801AB */ +static const struct pci_driver i82801ab_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2421, +}; + +/* 82801BA */ +static const struct pci_driver i82801ba_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244b, +}; + +/* 82801CA */ +static const struct pci_driver i82801ca_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x248b, +}; + +/* 82801DB */ +static const struct pci_driver i82801db_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24cb, +}; + +/* 82801DBM */ +static const struct pci_driver i82801dbm_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24ca, +}; + +/* 82801EB & 82801ER */ +static const struct pci_driver i82801ex_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24db, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c new file mode 100644 index 0000000000..4691ed4137 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -0,0 +1,416 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2003 SuSE Linux AG + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* From 82801DBM, needs to be fixed to support everything the 82801ER does. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <arch/io.h> +#include "i82801bx.h" + +#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ + +#define NMI_OFF 0 + +typedef struct southbridge_intel_i82801bx_config config_t; + +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +#define PIRQA 0x03 +#define PIRQB 0x04 +#define PIRQC 0x05 +#define PIRQD 0x06 +#define PIRQE 0x07 +#define PIRQF 0x09 +#define PIRQG 0x0A +#define PIRQH 0x0B + +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. + * Use the defined IRQ values above or set mainboard + * specific IRQ values in your mainboards Config.lb. +*/ + +void i82801bx_enable_apic(struct device *dev) +{ + uint32_t reg32; + volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; + volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + + /* Enable ACPI I/O and power management. */ + pci_write_config8(dev, ACPI_CNTL, 0x10); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* Enable IOAPIC */ + reg32 |= (1 << 13); /* Coprocessor error enable */ + reg32 |= (1 << 1); /* Delayed transaction enable */ + reg32 |= (1 << 2); /* DMA collection buffer enable */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk_debug("Southbridge APIC ID = %x\n", reg32); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + /* TODO: From i82801ca, needed/useful on other ICH? */ + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +void i82801bx_enable_serial_irqs(struct device *dev) +{ + /* Set packet length and toggle silent mode bit. */ + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + /* TODO: Explain/#define the real meaning of these magic numbers. */ +} + +static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +{ + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + if (config->pirqa_routing) { + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + } else { + pci_write_config8(dev, PIRQA_ROUT, PIRQA); + } + + if (config->pirqb_routing) { + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + } else { + pci_write_config8(dev, PIRQB_ROUT, PIRQB); + } + + if (config->pirqc_routing) { + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + } else { + pci_write_config8(dev, PIRQC_ROUT, PIRQC); + } + + if (config->pirqd_routing) { + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + } else { + pci_write_config8(dev, PIRQD_ROUT, PIRQD); + } + + /* Route PIRQE - PIRQH (for ICH2-ICH9). */ + if (ich_model >= 0x2440) { + + if (config->pirqe_routing) { + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + } else { + pci_write_config8(dev, PIRQE_ROUT, PIRQE); + } + + if (config->pirqf_routing) { + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + } else { + pci_write_config8(dev, PIRQF_ROUT, PIRQF); + } + + if (config->pirqg_routing) { + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + } else { + pci_write_config8(dev, PIRQG_ROUT, PIRQG); + } + + if (config->pirqh_routing) { + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + } else { + pci_write_config8(dev, PIRQH_ROUT, PIRQH); + } + } +} + +static void i82801bx_power_options(device_t dev) +{ + uint8_t byte; + int pwr_on = -1; + int nmi_option; + + /* power after power fail */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); + printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); + + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* Set NMI. */ + outb(byte, 0x70); + } +} + +static void gpio_init(device_t dev, uint16_t ich_model) +{ + /* Set the value for GPIO base address register and enable GPIO. + * Note: ICH-ICH5 registers differ from ICH6-ICH9. + */ + if (ich_model <= 0x24D0) { + pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + } else if (ich_model >= 0x2640) { + pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10); + } +} + +void i82801bx_rtc_init(struct device *dev) +{ + uint8_t reg8; + uint32_t reg32; + int rtc_failed; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~(1 << 1); /* Preserve the power fail state. */ + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + reg32 = pci_read_config32(dev, GEN_STS); + rtc_failed |= reg32 & (1 << 2); + rtc_init(rtc_failed); + + /* Enable access to the upper 128 byte bank of CMOS RAM. */ + pci_write_config8(dev, RTC_CONF, 0x04); +} + +void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) +{ + uint16_t reg16; + int i; + + reg16 = pci_read_config16(dev, PCI_DMA_CFG); + reg16 &= 0x300; + for (i = 0; i < 8; i++) { + if (i == 4) + continue; + reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); + } + pci_write_config16(dev, PCI_DMA_CFG, reg16); +} + +static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +{ + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + * Note: ICH-ICH5 registers differ from ICH6-ICH9. + */ + if (ich_model <= 0x24D0) { + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F); + } else if (ich_model >= 0x2640) { + pci_write_config8(dev, LPC_IO_DEC, 0x10); + pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F); + } +} + +static void enable_hpet(struct device *dev) +{ +#ifdef HPET_PRESENT + uint32_t reg32; + uint32_t code = (0 & 0x3); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 17); /* Enable HPET. */ + /* + * Bits [16:15] Memory Address Range + * 00 FED0_0000h - FED0_03FFh + * 01 FED0_1000h - FED0_13FFh + * 10 FED0_2000h - FED0_23FFh + * 11 FED0_3000h - FED0_33FFh + */ + reg32 &= ~(3 << 15); /* Clear it */ + reg32 |= (code << 15); + /* TODO: reg32 is never written to anywhere? */ + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); +#endif +} + +static void lpc_init(struct device *dev) +{ + uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + i82801bx_enable_apic(dev); + + i82801bx_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + i82801bx_pirq_init(dev, ich_model); + + /* Setup power options. */ + i82801bx_power_options(dev); + + /* Set the state of the GPIO lines. */ + gpio_init(dev, ich_model); + + /* Initialize the real time clock. */ + i82801bx_rtc_init(dev); + + /* Route DMA. */ + i82801bx_lpc_route_dma(dev, 0xff); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Setup decode ports and LPC I/F enables. */ + i82801bx_lpc_decode_en(dev, ich_model); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(dev); +} + +static void i82801bx_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void i82801bx_lpc_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static struct device_operations lpc_ops = { + .read_resources = i82801bx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801bx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801bx_enable, +}; + +static const struct pci_driver i82801aa_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2410, +}; + +static const struct pci_driver i82801ab_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2420, +}; + +static const struct pci_driver i82801ba_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2440, +}; + +static const struct pci_driver i82801ca_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2480, +}; + +static const struct pci_driver i82801db_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c0, +}; + +static const struct pci_driver i82801dbm_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24cc, +}; + +/* 82801EB and 82801ER */ +static const struct pci_driver i82801ex_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d0, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_nic.c b/src/southbridge/intel/i82801bx/i82801bx_nic.c new file mode 100644 index 0000000000..3728d28bd7 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_nic.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */ + +/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */ +static const struct pci_driver i82801ba_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_LAN, +}; + +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ +static const struct pci_driver i82801db_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_LAN, +}; + +/* 82801EB/ER (ICH5/ICH5R) */ +static const struct pci_driver i82801eb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_LAN, +}; + +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ +static const struct pci_driver i82801fb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_LAN, +}; + +/* 82801E (C-ICH) */ +static const struct pci_driver i82801e_nic1 __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_LAN1, +}; + +static const struct pci_driver i82801e_nic2 __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_LAN2, +}; + diff --git a/src/southbridge/intel/i82801bx/i82801bx_pci.c b/src/southbridge/intel/i82801bx/i82801bx_pci.c new file mode 100644 index 0000000000..1f01e5dc46 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_pci.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + uint16_t reg16; + + /* Clear system errors */ + reg16 = pci_read_config16(dev, 0x06); + reg16 |= 0xf900; /* Clear possible errors */ + pci_write_config16(dev, 0x06, reg16); + + reg16 = pci_read_config16(dev, 0x1e); + reg16 |= 0xf800; /* Clear possible errors */ + pci_write_config16(dev, 0x1e, reg16); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +}; + +static const struct pci_driver i82801aa_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2418, +}; + +static const struct pci_driver i82801ab_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2428, +}; + +/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */ +static const struct pci_driver i82801misc_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244e, +}; + +static const struct pci_driver i82801dbm_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2448, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_reset.c b/src/southbridge/intel/i82801bx/i82801bx_reset.c new file mode 100644 index 0000000000..239a727968 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_reset.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9. */ + outb((1 << 2) | (1 << 1), 0xcf9); +} diff --git a/src/southbridge/intel/i82801bx/i82801bx_sata.c b/src/southbridge/intel/i82801bx/i82801bx_sata.c new file mode 100644 index 0000000000..19a892ab1b --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_sata.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801bx.h" + +/* TODO: Set dynamically, if the user only wants one SATA channel or none + * at all. + */ +static void sata_init(struct device *dev) +{ + /* SATA configuration */ + pci_write_config8(dev, 0x04, 0x07); + pci_write_config8(dev, 0x09, 0x8f); + + /* Set timmings */ + pci_write_config16(dev, 0x40, 0x0a307); + pci_write_config16(dev, 0x42, 0x0a307); + + /* Sync DMA */ + pci_write_config16(dev, 0x48, 0x000f); + pci_write_config16(dev, 0x4a, 0x1111); + + /* 66 MHz */ + pci_write_config16(dev, 0x54, 0xf00f); + + /* Combine IDE - SATA configuration */ + pci_write_config8(dev, 0x90, 0x0); + + /* Port 0 & 1 enable */ + pci_write_config8(dev, 0x92, 0x33); + + /* Initialize SATA. */ + pci_write_config16(dev, 0xa0, 0x0018); + pci_write_config32(dev, 0xa4, 0x00000264); + pci_write_config16(dev, 0xa0, 0x0040); + pci_write_config32(dev, 0xa4, 0x00220043); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801EB */ +static const struct pci_driver i82801eb_sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d1, +}; + +/* 82801ER */ +static const struct pci_driver i82801er_sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24df, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_smbus.c new file mode 100644 index 0000000000..8a5476f494 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* TODO: Check datasheets if this will work for all ICH* southbridges. */ + +#include <stdint.h> +#include <smbus.h> +#include <pci.h> +#include <arch/io.h> +#include "i82801bx.h" +#include "i82801_smbus.h" + +static int smbus_read_byte(struct bus *bus, device_t dev, u8 address) +{ + unsigned device; /* TODO: u16? */ + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(bus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = smbus_read_byte, +}; + +static const struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i82801er_enable, + .ops_smbus_bus = &lops_smbus_bus, +}; + +/* 82801AA (ICH) */ +static const struct pci_driver i82801aa_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AA_SMB, +}; + +/* 82801AB (ICH0) */ +static const struct pci_driver i82801ab_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AB_SMB, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_SMB, +}; + +/* 82801CA/CAM (ICH3-S/ICH3-M) */ +static const struct pci_driver i82801ca_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_SMB, +}; + +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ +static const struct pci_driver i82801db_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_SMB, +}; + +/* 82801EB/ER (ICH5/ICH5R) */ +static const struct pci_driver i82801eb_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_SMB, +}; + +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ +static const struct pci_driver i82801fb_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_SMB, +}; + +/* 82801E (C-ICH) */ +static const struct pci_driver i82801e_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_SMB, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h new file mode 100644 index 0000000000..7a7850835b --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & (1 << 7)) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ +#warning "do_smbus_write_block is commented out" + print_err("Untested smbus_write_block called\r\n"); +#if 0 + unsigned char global_control_register; + unsigned char global_status_register; + unsigned char byte; + unsigned char stat; + int i; + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\r\n"); + return 0; +#endif +} diff --git a/src/southbridge/intel/i82801bx/i82801bx_usb.c b/src/southbridge/intel/i82801bx/i82801bx_usb.c new file mode 100644 index 0000000000..721f5bf155 --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_usb.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with USB. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801bx.h" + +static void usb_init(struct device *dev) +{ + /* TODO: Any init needed? Some ports have it, others don't. */ +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801AA (ICH) */ +static const struct pci_driver i82801aa_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AA_USB, +}; + +/* 82801AB (ICH0) */ +static const struct pci_driver i82801ab_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801AB_USB, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_USB1, +}; + +static const struct pci_driver i82801ba_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_USB2, +}; + +/* 82801CA/CAM (ICH3-S/ICH3-M) */ +static const struct pci_driver i82801ca_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB1, +}; + +static const struct pci_driver i82801ca_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB2, +}; + +static const struct pci_driver i82801ca_usb3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB3, +}; + +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ +static const struct pci_driver i82801db_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_USB1, +}; + +static const struct pci_driver i82801db_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_USB2, +}; + +static const struct pci_driver i82801db_usb3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_USB3, +}; + +/* 82801EB/ER (ICH5/ICH5R) */ +static const struct pci_driver i82801eb_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_USB1, +}; + +static const struct pci_driver i82801eb_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_USB2, +}; + +static const struct pci_driver i82801eb_usb3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_USB3, +}; + +static const struct pci_driver i82801eb_usb4 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_USB4, +}; + +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ +static const struct pci_driver i82801fb_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_USB1, +}; + +static const struct pci_driver i82801fb_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_USB2, +}; + +static const struct pci_driver i82801fb_usb3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_USB3, +}; + +static const struct pci_driver i82801fb_usb4 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_USB4, +}; + +/* 82801E (C-ICH) */ +static const struct pci_driver i82801e_usb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_USB, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c new file mode 100644 index 0000000000..1e885e920d --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801bx.h" + +static void usb_ehci_init(struct device *dev) +{ + /* TODO: Is any special init really needed? */ + uint32_t cmd; + + printk_debug("EHCI: Setting up controller.. "); + cmd = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); + + printk_debug("done.\n"); +} + +static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + uint8_t access_cntl; + + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + /* Write the subsystem vendor and device ID. */ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = 0, + .enable = i82801bx_enable, + .ops_pci = &lops_pci, +}; + +/* 82801DB and 82801DBM */ +static const struct pci_driver i82801db_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24cd, +}; + +/* 82801EB and 82801ER */ +static const struct pci_driver i82801ex_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24dd, +}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c new file mode 100644 index 0000000000..aea10e1c7b --- /dev/null +++ b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 John Dufresne <jon.dufresne@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +/* TODO: I'm fairly sure the same functionality is provided elsewhere. */ + +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH5 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk_debug("ICH Watchdog disabled\r\n"); +} diff --git a/src/southbridge/intel/i82801ca/Kconfig b/src/southbridge/intel/i82801ca/Kconfig deleted file mode 100644 index c5404e909c..0000000000 --- a/src/southbridge/intel/i82801ca/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config SOUTHBRIDGE_INTEL_I82801CA - bool diff --git a/src/southbridge/intel/i82801ca/Makefile.inc b/src/southbridge/intel/i82801ca/Makefile.inc deleted file mode 100644 index 587b06780c..0000000000 --- a/src/southbridge/intel/i82801ca/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -driver-y += i82801ca.o -driver-y += i82801ca_usb.o -driver-y += i82801ca_lpc.o -driver-y += i82801ca_ide.o -driver-y += i82801ca_ac97.o -#driver-y += i82801ca_nic.o -driver-y += i82801ca_pci.o -obj-y += i82801ca_reset.o diff --git a/src/southbridge/intel/i82801ca/chip.h b/src/southbridge/intel/i82801ca/chip.h deleted file mode 100644 index f9583ca1fd..0000000000 --- a/src/southbridge/intel/i82801ca/chip.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef I82801CA_CHIP_H -#define I82801CA_CHIP_H - -struct southbridge_intel_i82801ca_config -{ -}; -extern struct chip_operations southbridge_intel_i82801ca_ops; - -#endif /* I82801CA_CHIP_H */ diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig new file mode 100644 index 0000000000..a0c775d31e --- /dev/null +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -0,0 +1,2 @@ +config SOUTHBRIDGE_INTEL_I82801CX + bool diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc new file mode 100644 index 0000000000..163c0726cb --- /dev/null +++ b/src/southbridge/intel/i82801cx/Makefile.inc @@ -0,0 +1,8 @@ +driver-y += i82801cx.o +driver-y += i82801cx_usb.o +driver-y += i82801cx_lpc.o +driver-y += i82801cx_ide.o +driver-y += i82801cx_ac97.o +#driver-y += i82801cx_nic.o +driver-y += i82801cx_pci.o +obj-y += i82801cx_reset.o diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h new file mode 100644 index 0000000000..99b069e82d --- /dev/null +++ b/src/southbridge/intel/i82801cx/chip.h @@ -0,0 +1,9 @@ +#ifndef I82801CX_CHIP_H +#define I82801CX_CHIP_H + +struct southbridge_intel_i82801cx_config +{ +}; +extern struct chip_operations southbridge_intel_i82801cx_ops; + +#endif /* I82801CX_CHIP_H */ diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801cx/cmos_failover.c index bf35764c19..ab1816fbd8 100644 --- a/src/southbridge/intel/i82801ca/cmos_failover.c +++ b/src/southbridge/intel/i82801cx/cmos_failover.c @@ -1,6 +1,6 @@ //kind of cmos_err for ich3 -#include "i82801ca.h" +#include "i82801cx.h" static void check_cmos_failed(void) { diff --git a/src/southbridge/intel/i82801ca/i82801ca.c b/src/southbridge/intel/i82801cx/i82801cx.c index 23a64f7104..ddbbc7da37 100644 --- a/src/southbridge/intel/i82801ca/i82801ca.c +++ b/src/southbridge/intel/i82801cx/i82801cx.c @@ -3,9 +3,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <assert.h> -#include "i82801ca.h" +#include "i82801cx.h" -void i82801ca_enable(device_t dev) +void i82801cx_enable(device_t dev) { unsigned int index = 0; uint8_t bHasDisableBit = 0; @@ -47,7 +47,7 @@ void i82801ca_enable(device_t dev) } } -struct chip_operations southbridge_intel_i82801ca_ops = { - CHIP_NAME("Intel 82801CA Southbridge") - .enable_dev = i82801ca_enable, +struct chip_operations southbridge_intel_i82801cx_ops = { + CHIP_NAME("Intel ICH3 (82801Cx) Series Southbridge") + .enable_dev = i82801cx_enable, }; diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801cx/i82801cx.h index a761056bff..b9b3511a4a 100644 --- a/src/southbridge/intel/i82801ca/i82801ca.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -1,9 +1,9 @@ -#ifndef I82801CA_H -#define I82801CA_H +#ifndef I82801CX_H +#define I82801CX_H #if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" -extern void i82801ca_enable(device_t dev); +extern void i82801cx_enable(device_t dev); #endif @@ -75,4 +75,4 @@ extern void i82801ca_enable(device_t dev); */ #define SMBUS_TIMEOUT (100*1000) -#endif /* I82801CA_H */ +#endif /* I82801CX_H */ diff --git a/src/southbridge/intel/i82801ca/i82801ca_ac97.c b/src/southbridge/intel/i82801cx/i82801cx_ac97.c index 7e03cc382e..5de44fc382 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_ac97.c +++ b/src/southbridge/intel/i82801cx/i82801cx_ac97.c @@ -6,14 +6,14 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h" static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801ca_enable, + .enable = i82801cx_enable, .init = 0, .scan_bus = 0, }; @@ -29,7 +29,7 @@ static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801ca_enable, + .enable = i82801cx_enable, .init = 0, .scan_bus = 0, }; diff --git a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c index d33e40484c..9c3480283c 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c @@ -1,5 +1,5 @@ #include <device/pci_ids.h> -#include "i82801ca.h" +#include "i82801cx.h" static void enable_smbus(void) { diff --git a/src/southbridge/intel/i82801ca/i82801ca_ide.c b/src/southbridge/intel/i82801cx/i82801cx_ide.c index d1a19c77aa..2506b2f329 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_ide.c +++ b/src/southbridge/intel/i82801cx/i82801cx_ide.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h" static void ide_init(struct device *dev) @@ -38,7 +38,7 @@ static struct device_operations ide_ops = { .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801ca_enable, + .enable = i82801cx_enable, }; static const struct pci_driver ide_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c index fd16fef9b1..4785242a79 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c +++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c @@ -11,7 +11,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801ca.h" +#include "i82801cx.h" #define NMI_OFF 0 @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 -void i82801ca_enable_ioapic( struct device *dev) +void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; @@ -54,14 +54,14 @@ void i82801ca_enable_ioapic( struct device *dev) } // This is how interrupts are received from the Super I/O chip -void i82801ca_enable_serial_irqs( struct device *dev) +void i82801cx_enable_serial_irqs( struct device *dev) { // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); } //---------------------------------------------------------------------------------- -// Function: i82801ca_lpc_route_dma +// Function: i82801cx_lpc_route_dma // Parameters: dev // mask - identifies whether each channel should be used for PCI DMA // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. @@ -69,7 +69,7 @@ void i82801ca_enable_serial_irqs( struct device *dev) // Return Value: None // Description: Route all DMA channels to either PCI or LPC. // -void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) +void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; int channelIndex; @@ -84,7 +84,7 @@ void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, dmaConfig); } -void i82801ca_rtc_init(struct device *dev) +void i82801cx_rtc_init(struct device *dev) { uint32_t dword; int rtc_failed; @@ -116,7 +116,7 @@ void i82801ca_rtc_init(struct device *dev) } -void i82801ca_1f0_misc(struct device *dev) +void i82801cx_1f0_misc(struct device *dev) { // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); @@ -161,9 +161,9 @@ static void lpc_init(struct device *dev) int nmi_option; /* IO APIC initialization */ - i82801ca_enable_ioapic(dev); + i82801cx_enable_ioapic(dev); - i82801ca_enable_serial_irqs(dev); + i82801cx_enable_serial_irqs(dev); /* power after power fail */ /* FIXME this doesn't work! */ @@ -193,17 +193,17 @@ static void lpc_init(struct device *dev) } /* Initialize the real time clock */ - i82801ca_rtc_init(dev); + i82801cx_rtc_init(dev); - i82801ca_lpc_route_dma(dev, 0xff); + i82801cx_lpc_route_dma(dev, 0xff); /* Initialize isa dma */ isa_dma_init(); - i82801ca_1f0_misc(dev); + i82801cx_1f0_misc(dev); } -static void i82801ca_lpc_read_resources(device_t dev) +static void i82801cx_lpc_read_resources(device_t dev) { struct resource *res; @@ -229,16 +229,16 @@ static void i82801ca_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801ca_lpc_enable_resources(device_t dev) +static void i82801cx_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); } static struct device_operations lpc_ops = { - .read_resources = i82801ca_lpc_read_resources, + .read_resources = i82801cx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801ca_lpc_enable_resources, + .enable_resources = i82801cx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = 0, diff --git a/src/southbridge/intel/i82801ca/i82801ca_nic.c b/src/southbridge/intel/i82801cx/i82801cx_nic.c index c0b01bce70..00ce038143 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_nic.c +++ b/src/southbridge/intel/i82801cx/i82801cx_nic.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h" static struct device_operations nic_ops = { diff --git a/src/southbridge/intel/i82801ca/i82801ca_pci.c b/src/southbridge/intel/i82801cx/i82801cx_pci.c index 5f7b89700e..842b214fc8 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_pci.c +++ b/src/southbridge/intel/i82801cx/i82801cx_pci.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h" static void pci_init(struct device *dev) { diff --git a/src/southbridge/intel/i82801ca/i82801ca_reset.c b/src/southbridge/intel/i82801cx/i82801cx_reset.c index 93ef6d9f23..20e8530c54 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_reset.c +++ b/src/southbridge/intel/i82801cx/i82801cx_reset.c @@ -1,6 +1,6 @@ #include <arch/io.h> -void i82801ca_hard_reset(void) +void i82801cx_hard_reset(void) { /* Try rebooting through port 0xcf9 */ // Hard reset without power cycle diff --git a/src/southbridge/intel/i82801ca/i82801ca_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c index 0eceba7103..b69bbc1d9d 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_smbus.c @@ -1,7 +1,7 @@ #include <smbus.h> #include <pci.h> #include <arch/io.h> -#include "i82801ca.h" +#include "i82801cx.h" #define PM_BUS 0 #define PM_DEVFN PCI_DEVFN(0x1f,3) diff --git a/src/southbridge/intel/i82801ca/i82801ca_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c index 7e7c058b46..258581a78b 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_usb.c +++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h" static void usb_init(struct device *dev) { @@ -28,7 +28,7 @@ static struct device_operations usb_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801ca_enable, + .enable = i82801cx_enable, }; static const struct pci_driver usb_driver_1 __pci_driver = { diff --git a/src/southbridge/intel/i82801dbm/Kconfig b/src/southbridge/intel/i82801dbm/Kconfig deleted file mode 100644 index 3433d598e4..0000000000 --- a/src/southbridge/intel/i82801dbm/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config SOUTHBRIDGE_INTEL_I82801DBM - bool diff --git a/src/southbridge/intel/i82801dbm/Makefile.inc b/src/southbridge/intel/i82801dbm/Makefile.inc deleted file mode 100644 index 713427971c..0000000000 --- a/src/southbridge/intel/i82801dbm/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -driver-y += i82801dbm.o -driver-y += i82801dbm_usb.o -driver-y += i82801dbm_lpc.o -driver-y += i82801dbm_ide.o -driver-y += i82801dbm_usb2.o -driver-y += i82801dbm_ac97.o -#driver-y += i82801dbm_nic.o -#driver-y += i82801dbm_pci.o -obj-y += i82801dbm_reset.o diff --git a/src/southbridge/intel/i82801dbm/chip.h b/src/southbridge/intel/i82801dbm/chip.h deleted file mode 100644 index e1e3da0e6f..0000000000 --- a/src/southbridge/intel/i82801dbm/chip.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef I82801DBM_CHIP_H -#define I82801DBM_CHIP_H - -struct southbridge_intel_i82801dbm_config -{ - int enable_usb; - int enable_native_ide; -}; -struct chip_operations; -extern struct chip_operations southbridge_intel_i82801dbm_ops; - -#endif /* I82801DBM_CHIP_H */ diff --git a/src/southbridge/intel/i82801dbm/i82801dbm.h b/src/southbridge/intel/i82801dbm/i82801dbm.h deleted file mode 100644 index 824d23a0b6..0000000000 --- a/src/southbridge/intel/i82801dbm/i82801dbm.h +++ /dev/null @@ -1,81 +0,0 @@ -/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. - * fb1 code is what we want, fb2 structure is needed however. - * so we need to get fb1 code for 82801dbm into fb2 structure. - */ -/* What I did: took the 80801er stuff from fb2, verify it against the - * db stuff in fb1, and made sure it was right. - */ - -#ifndef I82801DBM_H -#define I82801DBM_H - -#include "chip.h" -extern void i82801dbm_enable(device_t dev); - -/* -000 = Non-combined. P0 is primary master. P1 is secondary master. -001 = Non-combined. P0 is secondary master. P1 is primary master. -100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel -disabled. -101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. -110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE -channel disabled. -111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. -*/ - -#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 - -#define PCICMD 0x04 -#define PMBASE 0x40 -#define ACPI_CNTL 0x44 -#define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 -#define GPIO_CNTL 0x5C -#define PIRQA_ROUT 0x60 -#define PIRQE_ROUT 0x68 -#define COM_DEC 0xE0 -#define LPC_EN 0xE6 -#define FUNC_DIS 0xF2 - -/* 1e f0 244e */ - -#define CMD 0x04 -#define SBUS_NUM 0x19 -#define SUB_BUS_NUM 0x1A -#define SMLT 0x1B -#define IOBASE 0x1C -#define IOLIM 0x1D -#define MEMBASE 0x20 -#define MEMLIM 0x22 -#define CNF 0x50 -#define MTT 0x70 -#define PCI_MAST_STS 0x82 - -#define RTC_FAILED (1 <<2) - - -#define SMBUS_IO_BASE 0x1000 - -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000) - -#endif /* I82801DBM_H */ diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig new file mode 100644 index 0000000000..6a35691b5d --- /dev/null +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -0,0 +1,2 @@ +config SOUTHBRIDGE_INTEL_I82801DX + bool diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc new file mode 100644 index 0000000000..7167e1d391 --- /dev/null +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -0,0 +1,9 @@ +driver-y += i82801dx.o +driver-y += i82801dx_usb.o +driver-y += i82801dx_lpc.o +driver-y += i82801dx_ide.o +driver-y += i82801dx_usb2.o +driver-y += i82801dx_ac97.o +#driver-y += i82801dx_nic.o +#driver-y += i82801dx_pci.o +obj-y += i82801dx_reset.o diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h new file mode 100644 index 0000000000..fdbb7d2d0d --- /dev/null +++ b/src/southbridge/intel/i82801dx/chip.h @@ -0,0 +1,27 @@ +#ifndef I82801DX_CHIP_H +#define I82801DX_CHIP_H + +struct southbridge_intel_i82801dx_config +{ + int enable_usb; + int enable_native_ide; + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + uint8_t ide0_enable; + uint8_t ide1_enable; +}; + +extern struct chip_operations southbridge_intel_i82801dx_ops; + +#endif /* I82801DBM_CHIP_H */ diff --git a/src/southbridge/intel/i82801dbm/cmos_failover.c b/src/southbridge/intel/i82801dx/cmos_failover.c index 4821fad3d2..4821fad3d2 100644 --- a/src/southbridge/intel/i82801dbm/cmos_failover.c +++ b/src/southbridge/intel/i82801dx/cmos_failover.c diff --git a/src/southbridge/intel/i82801dbm/i82801dbm.c b/src/southbridge/intel/i82801dx/i82801dx.c index 157ffcac1e..abfd8c21cf 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -2,9 +2,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801dbm.h" +#include "i82801dx.h" -void i82801dbm_enable(device_t dev) +void i82801dx_enable(device_t dev) { unsigned int index = 0; uint8_t bHasDisableBit = 0; @@ -59,7 +59,7 @@ void i82801dbm_enable(device_t dev) } } -struct chip_operations southbridge_intel_i82801dbm_ops = { - CHIP_NAME("Intel 82801DBM Southbridge") - .enable_dev = i82801dbm_enable, +struct chip_operations southbridge_intel_i82801dx_ops = { + CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge") + .enable_dev = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h new file mode 100644 index 0000000000..d4e1aa0928 --- /dev/null +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -0,0 +1,163 @@ +/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. + * fb1 code is what we want, fb2 structure is needed however. + * so we need to get fb1 code for 82801dbm into fb2 structure. + */ +/* What I did: took the 80801er stuff from fb2, verify it against the + * db stuff in fb1, and made sure it was right. + */ + +#ifndef I82801DX_H +#define I82801DX_H + +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#include "chip.h" +extern void i82801dx_enable(device_t dev); +#endif + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +/* +000 = Non-combined. P0 is primary master. P1 is secondary master. +001 = Non-combined. P0 is secondary master. P1 is primary master. +100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel +disabled. +101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. +110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE +channel disabled. +111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. +*/ + +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4 + +#define PCICMD 0x04 +#define PMBASE 0x40 +#define PMBASE_ADDR 0x0400 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0x4E +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define PIRQA_ROUT 0x60 +#define PIRQE_ROUT 0x68 +#define COM_DEC 0xE0 +#define LPC_EN 0xE6 +#define FUNC_DIS 0xF2 + +/* 1e f0 244e */ + +#define CMD 0x04 +#define SBUS_NUM 0x19 +#define SUB_BUS_NUM 0x1A +#define SMLT 0x1B +#define IOBASE 0x1C +#define IOLIM 0x1D +#define MEMBASE 0x20 +#define MEMLIM 0x22 +#define CNF 0x50 +#define MTT 0x70 +#define PCI_MAST_STS 0x82 + +#define RTC_FAILED (1 <<2) + + +#define SMBUS_IO_BASE 0x1000 + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000) + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define GST_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) +#define GPE0_EN 0x2c +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define SMI_EN 0x30 +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 + +#define TCOBASE 0x60 /* TCO Base Address Register */ +#define TCO1_CNT 0x08 /* TCO1 Control Register */ + +#endif /* I82801DX_H */ diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c b/src/southbridge/intel/i82801dx/i82801dx_ac97.c index 3b364017dd..752449865d 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c +++ b/src/southbridge/intel/i82801dx/i82801dx_ac97.c @@ -6,14 +6,14 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, .init = 0, .scan_bus = 0, }; @@ -29,7 +29,7 @@ static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, .init = 0, .scan_bus = 0, }; diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c index a85c08b9bb..0a0ff91f34 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c @@ -1,6 +1,6 @@ //#define SMBUS_IO_BASE 0x1000 -#define SMBUS_IO_BASE 0x0f00 +//#define SMBUS_IO_BASE 0x0f00 #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 @@ -17,7 +17,7 @@ /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ -#define SMBUS_TIMEOUT (100*1000*10) +//#define SMBUS_TIMEOUT (100*1000*10) static void enable_smbus(void) { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_ide.c b/src/southbridge/intel/i82801dx/i82801dx_ide.c index f7d799657b..bb3510783d 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_ide.c +++ b/src/southbridge/intel/i82801dx/i82801dx_ide.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static void ide_init(struct device *dev) @@ -42,7 +42,7 @@ static struct device_operations ide_ops = { .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, }; static const struct pci_driver ide_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index c461673cbf..59225d2c9a 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -10,13 +10,13 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801dbm.h" +#include "i82801dx.h" #define NMI_OFF 0 -void i82801dbm_enable_ioapic( struct device *dev) +void i82801dx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000; @@ -46,11 +46,11 @@ void i82801dbm_enable_ioapic( struct device *dev) } -void i82801dbm_enable_serial_irqs( struct device *dev) +void i82801dx_enable_serial_irqs( struct device *dev) { pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); } -void i82801dbm_lpc_route_dma( struct device *dev, uint8_t mask) +void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t word; int i; @@ -63,7 +63,7 @@ void i82801dbm_lpc_route_dma( struct device *dev, uint8_t mask) } pci_write_config16(dev, PCI_DMA_CFG, word); } -void i82801dbm_rtc_init(struct device *dev) +void i82801dx_rtc_init(struct device *dev) { uint8_t byte; uint32_t dword; @@ -80,7 +80,7 @@ void i82801dbm_rtc_init(struct device *dev) } -void i82801dbm_1f0_misc(struct device *dev) +void i82801dx_1f0_misc(struct device *dev) { pci_write_config16(dev, PCICMD, 0x014f); pci_write_config32(dev, PMBASE, 0x00001001); @@ -122,9 +122,9 @@ static void lpc_init(struct device *dev) int nmi_option; /* IO APIC initialization */ - i82801dbm_enable_ioapic(dev); + i82801dx_enable_ioapic(dev); - i82801dbm_enable_serial_irqs(dev); + i82801dx_enable_serial_irqs(dev); #ifdef SUSPICIOUS_LOOKING_CODE // The ICH-4 datasheet does not mention this configuration register. @@ -166,19 +166,19 @@ static void lpc_init(struct device *dev) } /* Initialize the real time clock */ - i82801dbm_rtc_init(dev); + i82801dx_rtc_init(dev); - i82801dbm_lpc_route_dma(dev, 0xff); + i82801dx_lpc_route_dma(dev, 0xff); /* Initialize isa dma */ isa_dma_init(); - i82801dbm_1f0_misc(dev); + i82801dx_1f0_misc(dev); /* Initialize the High Precision Event Timers */ enable_hpet(dev); } -static void i82801dbm_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(device_t dev) { struct resource *res; @@ -204,19 +204,19 @@ static void i82801dbm_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801dbm_lpc_enable_resources(device_t dev) +static void i82801dx_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); } static struct device_operations lpc_ops = { - .read_resources = i82801dbm_lpc_read_resources, + .read_resources = i82801dx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801dbm_lpc_enable_resources, + .enable_resources = i82801dx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_nic.c b/src/southbridge/intel/i82801dx/i82801dx_nic.c index e25f1bcaf7..6221ba4889 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_nic.c +++ b/src/southbridge/intel/i82801dx/i82801dx_nic.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static struct device_operations nic_ops = { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_pci.c b/src/southbridge/intel/i82801dx/i82801dx_pci.c index b69cd601c4..0c88bf2827 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_pci.c +++ b/src/southbridge/intel/i82801dx/i82801dx_pci.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static void pci_init(struct device *dev) { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_reset.c b/src/southbridge/intel/i82801dx/i82801dx_reset.c index 3d7a4b79b6..3d7a4b79b6 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_reset.c +++ b/src/southbridge/intel/i82801dx/i82801dx_reset.c diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_sata.c b/src/southbridge/intel/i82801dx/i82801dx_sata.c index 405ee0e92f..22c6cd77fd 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_sata.c +++ b/src/southbridge/intel/i82801dx/i82801dx_sata.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static void sata_init(struct device *dev) { @@ -64,7 +64,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, }; static const struct pci_driver stat_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_smbus.c index fd06871234..e56a67c1e0 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_smbus.c @@ -1,3 +1,4 @@ +#include "i82801dx.h" #include <smbus.h> #include <pci.h> #include <arch/io.h> @@ -5,6 +6,7 @@ #define PM_BUS 0 #define PM_DEVFN PCI_DEVFN(0x1f,3) +#if 0 #define SMBUS_IO_BASE 0x1000 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 @@ -13,6 +15,7 @@ #define SMBHSTDAT0 5 #define SMBHSTDAT1 6 #define SMBBLKDAT 7 +#endif void smbus_enable(void) { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_usb.c b/src/southbridge/intel/i82801dx/i82801dx_usb.c index 3fd61673b2..2e60193855 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_usb.c +++ b/src/southbridge/intel/i82801dx/i82801dx_usb.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static void usb_init(struct device *dev) { @@ -29,7 +29,7 @@ static struct device_operations usb_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, }; static const struct pci_driver usb_driver_1 __pci_driver = { diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c b/src/southbridge/intel/i82801dx/i82801dx_usb2.c index f05fbbb933..ca13e92995 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c +++ b/src/southbridge/intel/i82801dx/i82801dx_usb2.c @@ -5,7 +5,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h" static void usb2_init(struct device *dev) { @@ -30,7 +30,7 @@ static struct device_operations usb2_ops = { .enable_resources = pci_dev_enable_resources, .init = usb2_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, }; static const struct pci_driver usb2_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801er/Kconfig b/src/southbridge/intel/i82801er/Kconfig deleted file mode 100644 index adb6c1d11c..0000000000 --- a/src/southbridge/intel/i82801er/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config SOUTHBRIDGE_INTEL_I82801ER - bool - select IOAPIC diff --git a/src/southbridge/intel/i82801er/Makefile.inc b/src/southbridge/intel/i82801er/Makefile.inc deleted file mode 100644 index b2f81f8b2e..0000000000 --- a/src/southbridge/intel/i82801er/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -driver-y += i82801er.o -driver-y += i82801er_uhci.o -driver-y += i82801er_lpc.o -driver-y += i82801er_ide.o -driver-y += i82801er_sata.o -driver-y += i82801er_ehci.o -driver-y += i82801er_smbus.o -driver-y += i82801er_pci.o -driver-y += i82801er_ac97.o -obj-y += i82801er_watchdog.o -obj-y += i82801er_reset.o diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig new file mode 100644 index 0000000000..905af26235 --- /dev/null +++ b/src/southbridge/intel/i82801ex/Kconfig @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I82801EX + bool + select IOAPIC diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc new file mode 100644 index 0000000000..66a217ba6a --- /dev/null +++ b/src/southbridge/intel/i82801ex/Makefile.inc @@ -0,0 +1,11 @@ +driver-y += i82801ex.o +driver-y += i82801ex_uhci.o +driver-y += i82801ex_lpc.o +driver-y += i82801ex_ide.o +driver-y += i82801ex_sata.o +driver-y += i82801ex_ehci.o +driver-y += i82801ex_smbus.o +driver-y += i82801ex_pci.o +driver-y += i82801ex_ac97.o +obj-y += i82801ex_watchdog.o +obj-y += i82801ex_reset.o diff --git a/src/southbridge/intel/i82801er/chip.h b/src/southbridge/intel/i82801ex/chip.h index eb63889794..34a0a97ffd 100644 --- a/src/southbridge/intel/i82801er/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -1,7 +1,7 @@ -#ifndef I82801ER_CHIP_H -#define I82801ER_CHIP_H +#ifndef I82801EX_CHIP_H +#define I82801EX_CHIP_H -struct southbridge_intel_i82801er_config +struct southbridge_intel_i82801ex_config { #define ICH5R_GPIO_USE_MASK 0x03 @@ -30,7 +30,7 @@ struct southbridge_intel_i82801er_config unsigned int pirq_a_d; unsigned int pirq_e_h; }; -extern struct chip_operations southbridge_intel_i82801er_ops; +extern struct chip_operations southbridge_intel_i82801ex_ops; -#endif /* I82801ER_CHIP_H */ +#endif /* I82801EX_CHIP_H */ diff --git a/src/southbridge/intel/i82801er/cmos_failover.c b/src/southbridge/intel/i82801ex/cmos_failover.c index 4821fad3d2..4821fad3d2 100644 --- a/src/southbridge/intel/i82801er/cmos_failover.c +++ b/src/southbridge/intel/i82801ex/cmos_failover.c diff --git a/src/southbridge/intel/i82801er/i82801er.c b/src/southbridge/intel/i82801ex/i82801ex.c index 19b0666cdb..bc5f04bf44 100644 --- a/src/southbridge/intel/i82801er/i82801er.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -2,15 +2,15 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801er.h" +#include "i82801ex.h" -void i82801er_enable(device_t dev) +void i82801ex_enable(device_t dev) { device_t lpc_dev; unsigned index = 0; uint16_t reg_old, reg; - /* See if we are behind the i82801er pci bridge */ + /* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); if((dev->path.pci.devfn &0xf8)== 0xf8) { index = dev->path.pci.devfn & 7; @@ -42,7 +42,7 @@ void i82801er_enable(device_t dev) } -struct chip_operations southbridge_intel_i82801er_ops = { - CHIP_NAME("Intel 82801ER Southbridge") - .enable_dev = i82801er_enable, +struct chip_operations southbridge_intel_i82801ex_ops = { + CHIP_NAME("Intel ICH5 (82801Ex) Series Southbridge") + .enable_dev = i82801ex_enable, }; diff --git a/src/southbridge/intel/i82801er/i82801er.h b/src/southbridge/intel/i82801ex/i82801ex.h index bd7410162b..67fecdd57e 100644 --- a/src/southbridge/intel/i82801er/i82801er.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -1,9 +1,9 @@ -#ifndef I82801ER_H -#define I82801ER_H +#ifndef I82801EX_H +#define I82801EX_H #include "chip.h" -extern void i82801er_enable(device_t dev); +extern void i82801ex_enable(device_t dev); #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 @@ -12,4 +12,4 @@ extern void i82801er_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 -#endif /* I82801ER_H */ +#endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801er/i82801er_ac97.c b/src/southbridge/intel/i82801ex/i82801ex_ac97.c index 0525a5ebdf..65502dd8cc 100644 --- a/src/southbridge/intel/i82801er/i82801er_ac97.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ac97.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h" static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { @@ -21,7 +21,7 @@ static struct device_operations ac97_ops = { .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801er/i82801er_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index 42a55680af..c86bf23bb7 100644 --- a/src/southbridge/intel/i82801er/i82801er_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -1,4 +1,4 @@ -#include "i82801er_smbus.h" +#include "i82801ex_smbus.h" #define SMBUS_IO_BASE 0x0f00 diff --git a/src/southbridge/intel/i82801er/i82801er_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c index 47b18de505..60b1f304c2 100644 --- a/src/southbridge/intel/i82801er/i82801er_ehci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h" static void ehci_init(struct device *dev) { @@ -39,7 +39,7 @@ static struct device_operations ehci_ops = { .enable_resources = pci_dev_enable_resources, .init = ehci_init, .scan_bus = 0, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801er/i82801er_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c index 8d8e391a97..b4d2311e0b 100644 --- a/src/southbridge/intel/i82801er/i82801er_ide.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h" static void ide_init(struct device *dev) { @@ -16,7 +16,7 @@ static void ide_init(struct device *dev) printk_debug("IDE Enabled\n"); } -static void i82801er_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -24,7 +24,7 @@ static void i82801er_ide_set_subsystem(device_t dev, unsigned vendor, unsigned d } static struct pci_operations lops_pci = { - .set_subsystem = i82801er_ide_set_subsystem, + .set_subsystem = i82801ex_ide_set_subsystem, }; static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index 357e181a9d..6cf8124c50 100644 --- a/src/southbridge/intel/i82801er/i82801er_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -10,7 +10,7 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include "i82801er.h" +#include "i82801ex.h" #define ACPI_BAR 0x40 #define GPIO_BAR 0x58 @@ -24,7 +24,7 @@ #endif #define SERIRQ_CNTL 0x64 -static void i82801er_enable_serial_irqs(device_t dev) +static void i82801ex_enable_serial_irqs(device_t dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -32,22 +32,22 @@ static void i82801er_enable_serial_irqs(device_t dev) } #define PCI_DMA_CFG 0x90 -static void i82801er_pci_dma_cfg(device_t dev) +static void i82801ex_pci_dma_cfg(device_t dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); } #define LPC_EN 0xe6 -static void i82801er_enable_lpc(device_t dev) +static void i82801ex_enable_lpc(device_t dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); } -typedef struct southbridge_intel_i82801er_config config_t; +typedef struct southbridge_intel_i82801ex_config config_t; -static void set_i82801er_gpio_use_sel( +static void set_i82801ex_gpio_use_sel( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; @@ -76,7 +76,7 @@ static void set_i82801er_gpio_use_sel( outl(gpio_use_sel2, res->base + 0x30); } -static void set_i82801er_gpio_direction( +static void set_i82801ex_gpio_direction( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; @@ -105,7 +105,7 @@ static void set_i82801er_gpio_direction( outl(gpio_io_sel2, res->base + 0x34); } -static void set_i82801er_gpio_level( +static void set_i82801ex_gpio_level( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; @@ -140,7 +140,7 @@ static void set_i82801er_gpio_level( outl(gpio_lvl2, res->base + 0x38); } -static void set_i82801er_gpio_inv( +static void set_i82801ex_gpio_inv( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_inv; @@ -161,7 +161,7 @@ static void set_i82801er_gpio_inv( outl(gpio_inv, res->base + 0x2c); } -static void i82801er_pirq_init(device_t dev) +static void i82801ex_pirq_init(device_t dev) { config_t *config; @@ -177,7 +177,7 @@ static void i82801er_pirq_init(device_t dev) } -static void i82801er_gpio_init(device_t dev) +static void i82801ex_gpio_init(device_t dev) { struct resource *res; config_t *config; @@ -199,16 +199,16 @@ static void i82801er_gpio_init(device_t dev) } /* Set the use selects */ - set_i82801er_gpio_use_sel(dev, res, config); + set_i82801ex_gpio_use_sel(dev, res, config); /* Set the IO direction */ - set_i82801er_gpio_direction(dev, res, config); + set_i82801ex_gpio_direction(dev, res, config); /* Setup the input inverters */ - set_i82801er_gpio_inv(dev, res, config); + set_i82801ex_gpio_inv(dev, res, config); /* Set the value on the GPIO output pins */ - set_i82801er_gpio_level(dev, res, config); + set_i82801ex_gpio_level(dev, res, config); } @@ -250,11 +250,11 @@ static void lpc_init(struct device *dev) pci_write_config32(dev, 0xd4, value); setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. - i82801er_enable_serial_irqs(dev); + i82801ex_enable_serial_irqs(dev); - i82801er_pci_dma_cfg(dev); + i82801ex_pci_dma_cfg(dev); - i82801er_enable_lpc(dev); + i82801ex_enable_lpc(dev); /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00); @@ -269,10 +269,10 @@ static void lpc_init(struct device *dev) printk_info("set power %s after power fail\n", pwr_on?"on":"off"); /* Set up the PIRQ */ - i82801er_pirq_init(dev); + i82801ex_pirq_init(dev); /* Set the state of the gpio lines */ - i82801er_gpio_init(dev); + i82801ex_gpio_init(dev); /* Initialize the real time clock */ rtc_init(0); @@ -286,7 +286,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801er_lpc_read_resources(device_t dev) +static void i82801ex_lpc_read_resources(device_t dev) { struct resource *res; @@ -318,7 +318,7 @@ static void i82801er_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void i82801er_lpc_enable_resources(device_t dev) +static void i82801ex_lpc_enable_resources(device_t dev) { uint8_t acpi_cntl, gpio_cntl; @@ -343,12 +343,12 @@ static struct pci_operations lops_pci = { }; static struct device_operations lpc_ops = { - .read_resources = i82801er_lpc_read_resources, + .read_resources = i82801ex_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801er_lpc_enable_resources, + .enable_resources = i82801ex_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801er/i82801er_pci.c b/src/southbridge/intel/i82801ex/i82801ex_pci.c index 6aa578f7f6..650628b5e5 100644 --- a/src/southbridge/intel/i82801er/i82801er_pci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_pci.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h" static void pci_init(struct device *dev) { diff --git a/src/southbridge/intel/i82801er/i82801er_reset.c b/src/southbridge/intel/i82801ex/i82801ex_reset.c index fa41756557..a1d92a7cc1 100644 --- a/src/southbridge/intel/i82801er/i82801er_reset.c +++ b/src/southbridge/intel/i82801ex/i82801ex_reset.c @@ -1,6 +1,6 @@ #include <arch/io.h> -void i82801er_hard_reset(void) +void i82801ex_hard_reset(void) { /* Try rebooting through port 0xcf9 */ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); diff --git a/src/southbridge/intel/i82801er/i82801er_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c index c710d83364..98431edc78 100644 --- a/src/southbridge/intel/i82801er/i82801er_sata.c +++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h" static void sata_init(struct device *dev) { diff --git a/src/southbridge/intel/i82801er/i82801er_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_smbus.c index ee32c697a7..adfbcb7cc9 100644 --- a/src/southbridge/intel/i82801er/i82801er_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.c @@ -5,8 +5,8 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <arch/io.h> -#include "i82801er.h" -#include "i82801er_smbus.h" +#include "i82801ex.h" +#include "i82801ex_smbus.h" static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address) { @@ -32,7 +32,7 @@ static struct device_operations smbus_ops = { .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801er/i82801er_smbus.h b/src/southbridge/intel/i82801ex/i82801ex_smbus.h index 861230e130..861230e130 100644 --- a/src/southbridge/intel/i82801er/i82801er_smbus.h +++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.h diff --git a/src/southbridge/intel/i82801er/i82801er_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c index c0f42314a5..177b82089c 100644 --- a/src/southbridge/intel/i82801er/i82801er_uhci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h" static void uhci_init(struct device *dev) { @@ -32,7 +32,7 @@ static struct device_operations uhci_ops = { .enable_resources = pci_dev_enable_resources, .init = uhci_init, .scan_bus = 0, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801er/i82801er_watchdog.c b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c index c9c09f5896..c9c09f5896 100644 --- a/src/southbridge/intel/i82801er/i82801er_watchdog.c +++ b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c |