diff options
Diffstat (limited to 'src')
92 files changed, 0 insertions, 14802 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index b388c50f29..ab63682414 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -11,7 +11,6 @@ source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/model_1067x/Kconfig source src/cpu/intel/model_106cx/Kconfig source src/cpu/intel/model_206ax/Kconfig -source src/cpu/intel/fsp_model_206ax/Kconfig source src/cpu/intel/fsp_model_406dx/Kconfig source src/cpu/intel/model_2065x/Kconfig source src/cpu/intel/model_f0x/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 859b73beab..8d9833aa68 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -22,8 +22,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig deleted file mode 100644 index 606000e4be..0000000000 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - - -config CPU_INTEL_FSP_MODEL_206AX - bool - -config CPU_INTEL_FSP_MODEL_306AX - bool - -if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX - -config CPU_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SSE2 - select UDELAY_LAPIC - select SMM_TSEG - select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN - select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE - select LAPIC_MONOTONIC_TIMER - -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/fsp_model_206ax/bootblock.c" - -config SMM_TSEG_SIZE - hex - default 0x800000 - -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - -config CPU_MICROCODE_CBFS_LOC - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xfff70000 - -endif diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc deleted file mode 100644 index d2d61ef883..0000000000 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -ramstage-y += model_206ax_init.c -subdirs-y += ../../x86/name -subdirs-y += ../smm/gen1 - -ramstage-y += acpi.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c - -CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c deleted file mode 100644 index 272f4863fa..0000000000 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> -#include <cpu/intel/turbo.h> -#include <device/device.h> -#include "model_206ax.h" -#include "chip.h" - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - -static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - -static void generate_C_state_entries(void) -{ - struct cpu_info *info; - struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_fsp_model_206ax_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; - - /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) - return; - cpu = find_cpu_driver(info->cpu); - if (!cpu || !cpu->cstates) - return; - - acpigen_write_method("_CST", 0); - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); -} - -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * SANDYBRIDGE_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, cores_per_package, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * SANDYBRIDGE_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(device_t device) -{ - int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID=1; coreID<=cores_per_package; coreID++) { - if (coreID>1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - cpuID-1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID-1, cores_per_package); - - acpigen_pop_len(); - } - } -} - -struct chip_operations cpu_intel_model_206ax_ops = { - CHIP_NAME("Intel SandyBridge/IvyBridge CPU") -}; diff --git a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl deleted file mode 100644 index 114dbe3b98..0000000000 --- a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, - \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} diff --git a/src/cpu/intel/fsp_model_206ax/bootblock.c b/src/cpu/intel/fsp_model_206ax/bootblock.c deleted file mode 100644 index 28cbd7ef77..0000000000 --- a/src/cpu/intel/fsp_model_206ax/bootblock.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <arch/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <arch/io.h> - -#include "model_206ax.h" - -static void bootblock_cpu_init(void) -{ -} diff --git a/src/cpu/intel/fsp_model_206ax/chip.h b/src/cpu/intel/fsp_model_206ax/chip.h deleted file mode 100644 index 759a74cdde..0000000000 --- a/src/cpu/intel/fsp_model_206ax/chip.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - -struct cpu_intel_fsp_model_206ax_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ - - int tcc_offset; /* TCC Activation Offset */ -}; diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c deleted file mode 100644 index 839d9508ee..0000000000 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include "model_206ax.h" - -/* MSR Documentation based on - * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" - * Document Number 504790 - * Revision 1.6.0, June 2012 */ - -static void msr_set_bit(unsigned reg, unsigned bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} - -void intel_model_206ax_finalize_smm(void) -{ - /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); - - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); - -#ifdef LOCK_POWER_CONTROL_REGISTERS - /* - * Lock the power control registers. - * - * These registers can be left unlocked if modifying power - * limits from the OS is desirable. Modifying power limits - * from the OS can be especially useful for experimentation - * during early phases of system bringup while the thermal - * power envelope is being proven. - */ - - msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PKG_POWER_LIMIT, 63); - msr_set_bit(MSR_PP0_POWER_LIMIT, 31); - msr_set_bit(MSR_PP1_POWER_LIMIT, 31); -#endif - - /* Lock TM interupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); - - /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); -} diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h deleted file mode 100644 index bf5de53705..0000000000 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _CPU_INTEL_MODEL_206AX_H -#define _CPU_INTEL_MODEL_206AX_H - -/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ -#define SANDYBRIDGE_BCLK 100 - -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 - -#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 - -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_POWER_CTL 0x1fc - -#define MSR_PKGC3_IRTL 0x60a -#define MSR_PKGC6_IRTL 0x60b -#define MSR_PKGC7_IRTL 0x60c -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) - -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - -#define MSR_PP0_CURRENT_CONFIG 0x601 -#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ -#define MSR_PP1_CURRENT_CONFIG 0x602 -#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ -#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - -/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - -#ifndef __ROMCC__ -#ifdef __SMM__ -/* Lock MSRs */ -void intel_model_206ax_finalize_smm(void); -#else -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); -void smm_relocate(void); -#endif -#endif - -#endif diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c deleted file mode 100644 index 9b76c22aa2..0000000000 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ /dev/null @@ -1,437 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <device/device.h> -#include <string.h> -#include <arch/acpi.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/speedstep.h> -#include <cpu/intel/turbo.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/name.h> -#include <pc80/mc146818rtc.h> -#include "model_206ax.h" -#include "chip.h" -#include <cpu/intel/smm/gen1/smi.h> - -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); - - regs = cpuid(1); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) - return; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - - if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Minimum CPU revision */ - if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return 0; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned power_unit; - unsigned tdp, min_power, max_power, max_time; - u8 power_limit_1_val; - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - return; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP */ - limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - /* Power limit 2 time is only programmable on SNB EP/EX */ - - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - limit.hi = 0; - limit.lo = msr.lo & 0xff; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - struct cpuid_result cpuid_regs; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - cpuid_regs = cpuid(1); - if (cpuid_regs.ecx & (1 << 18)) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - -static void set_max_ratio(void) -{ - msr_t msr, perf_ctl; - - perf_ctl.hi = 0; - - /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); -} - -static void configure_mca(void) -{ - msr_t msr; - int i; - - msr.lo = msr.hi = 0; - /* This should only be done on a cold boot */ - for (i = 0; i < 7; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - -int cpu_get_apic_id_map(int *apic_id_map) -{ - struct cpuid_result result; - unsigned threads_per_package, threads_per_core, i, shift = 0; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - if (threads_per_core == 1) - shift++; - - for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; i++) - apic_id_map[i] = i << shift; - - return threads_per_package; -} - -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(struct device *cpu) -{ - struct cpuid_result result; - unsigned threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - struct device *new; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new cpu device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ - if (!start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } -#endif - } -} - -static void model_206ax_init(struct device *cpu) -{ - char processor_name[49]; - struct cpuid_result cpuid_regs; - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Clear out pending MCEs */ - configure_mca(); - - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); - x86_mtrr_check(); - - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - - /* Enable the local cpu apics */ - enable_lapic_tpr(); - setup_lapic(); - - /* Enable virtualization if Kconfig option is set */ - enable_vmx(); - - /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); - - /* Enable Direct Cache Access */ - configure_dca_cap(); - - /* Set Max Ratio */ - set_max_ratio(); - - /* Enable Turbo */ - enable_turbo(); - - /* Start up extra cores */ - intel_cores_init(cpu); -} - -static struct device_operations cpu_dev_ops = { - .init = model_206ax_init, -}; - -static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */ - { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */ - { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */ - { X86_VENDOR_INTEL, 0x306a0 }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */ - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig deleted file mode 100644 index 0432a53f4a..0000000000 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -if BOARD_INTEL_COUGAR_CANYON2 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_FSP_IVYBRIDGE - select SOUTHBRIDGE_INTEL_FSP_BD82X6X - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select MMCONF_SUPPORT - select SUPERIO_SMSC_SIO1007 - select ENABLE_VMX - select INTEL_INT15 - select VGA - -config MAINBOARD_DIR - string - default intel/cougar_canyon2 - -config MAINBOARD_PART_NUMBER - string - default "Cougar Canyon 2" - -config MMCONF_BASE_ADDRESS - hex - default 0xf8000000 # set to match FSP - -config MAX_CPUS - int - default 16 - -config SMBIOS_SYSTEM_ENCLOSURE_TYPE - hex - default 0x09 # This is a mobile platform - -config UDELAY_LAPIC_FIXED_FSB - int - default 100 - -config VIRTUAL_ROM_SIZE - hex - default 0x1000000 - -if HAVE_FSP_BIN - -config VGA_BIOS - bool - default y - -config VGA_BIOS_FILE - string - default "../intel/mainboard/intel/cougar_canyon2/vbios/snm_2170.dat" - -config VGA_BIOS_ID - string - default "8086,0166" - - -endif # HAVE_FSP_BIN - -endif # BOARD_INTEL_COUGAR_CANYON2 diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig.name b/src/mainboard/intel/cougar_canyon2/Kconfig.name deleted file mode 100644 index b2c8c1cb75..0000000000 --- a/src/mainboard/intel/cougar_canyon2/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_COUGAR_CANYON2 - bool "Cougar Canyon 2 CRB" diff --git a/src/mainboard/intel/cougar_canyon2/acpi/ec.asl b/src/mainboard/intel/cougar_canyon2/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/ec.asl +++ /dev/null diff --git a/src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl b/src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl deleted file mode 100644 index d0a5dc6691..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 19 }, - - // Network 0:19.0 - Package() { 0x0019ffff, 0, 0, 20 }, - - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 }, - - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - - /* MEI */ - Package() { 0x0016ffff, 0, 0, 16 }, - Package() { 0x0016ffff, 1, 0, 17 }, - - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 23 }, - - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 2, 0, 18 }, - Package() { 0x001fffff, 3, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - - // EHCI #2 0:19.0 - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - - /* Management Engine Interface */ - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl b/src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl deleted file mode 100644 index a55894c5d7..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) -} diff --git a/src/mainboard/intel/cougar_canyon2/acpi/platform.asl b/src/mainboard/intel/cougar_canyon2/acpi/platform.asl deleted file mode 100644 index 210dca6adf..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/platform.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - // NVS has a flag to determine USB policy in S3 - if (S3U0) { - Store (One, GP47) // Enable USB0 - } Else { - Store (Zero, GP47) // Disable USB0 - } - - // NVS has a flag to determine USB policy in S3 - if (S3U1) { - Store (One, GP56) // Enable USB1 - } Else { - Store (Zero, GP56) // Disable USB1 - } -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/intel/cougar_canyon2/acpi/superio.asl b/src/mainboard/intel/cougar_canyon2/acpi/superio.asl deleted file mode 100644 index 62103ce6df..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi/superio.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Values should match those defined in devicetree.cb */ - -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR - -#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 - -#include "superio/smsc/sio1007/acpi/superio.asl" diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c deleted file mode 100644 index fce84fefde..0000000000 --- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/x86/msr.h> - -#include "southbridge/intel/fsp_bd82x6x/nvs.h" -#include "thermal.h" - -static global_nvs_t *gnvs_; - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 5; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - gnvs_ = gnvs; - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/intel/cougar_canyon2/board_info.txt b/src/mainboard/intel/cougar_canyon2/board_info.txt deleted file mode 100644 index b89835dfc8..0000000000 --- a/src/mainboard/intel/cougar_canyon2/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: eval -Release year: 2010 diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout deleted file mode 100644 index 0c391ecff2..0000000000 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ /dev/null @@ -1,118 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode -#412 4 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb deleted file mode 100644 index d7c6aabd4e..0000000000 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ /dev/null @@ -1,70 +0,0 @@ -chip northbridge/intel/fsp_sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort 1 Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DisplayPort 0 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable DVI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end - chip cpu/intel/fsp_model_206ax - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - - chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH - register "sata_port_map" = "0x3f" - - register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" - - device pci 14.0 on end # XHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - # TODO: insert SIO UART and WDT - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/intel/cougar_canyon2/dsdt.asl b/src/mainboard/intel/cougar_canyon2/dsdt.asl deleted file mode 100644 index 82d6ee5076..0000000000 --- a/src/mainboard/intel/cougar_canyon2/dsdt.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/bd82x6x/acpi/platform.asl> - - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - #include <cpu/intel/fsp_model_206ax/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/fsp_bd82x6x/acpi/pch.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/fsp_bd82x6x/acpi/sleepstates.asl> -} diff --git a/src/mainboard/intel/cougar_canyon2/gpio.h b/src/mainboard/intel/cougar_canyon2/gpio.h deleted file mode 100644 index 61cc88bdd7..0000000000 --- a/src/mainboard/intel/cougar_canyon2/gpio.h +++ /dev/null @@ -1,308 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include "southbridge/intel/fsp_bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* SINAI */ - .gpio1 = GPIO_MODE_GPIO, /* SMC_SMI */ - .gpio2 = GPIO_MODE_GPIO, /* PIRQE# */ - .gpio3 = GPIO_MODE_GPIO, /* PIRQF# */ - .gpio4 = GPIO_MODE_GPIO, /* PIRQG# */ - .gpio5 = GPIO_MODE_GPIO, /* PIRQH# */ - .gpio6 = GPIO_MODE_GPIO, /* DGPU_HPD_INTR*/ - .gpio7 = GPIO_MODE_GPIO, /* SMC_SCI# */ - .gpio8 = GPIO_MODE_NONE, /* NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /* USB OC10-11*/ - .gpio10 = GPIO_MODE_NATIVE, /* USB OC12-13 */ - .gpio11 = GPIO_MODE_GPIO, /* SMB_ALERT*/ - .gpio12 = GPIO_MODE_NATIVE, /* LAN DISABLE */ - .gpio13 = GPIO_MODE_NATIVE, /* HDA_DOCK_RST */ - .gpio14 = GPIO_MODE_GPIO, /* SMC_WAKE */ - .gpio15 = GPIO_MODE_GPIO, /* HOST ALERT */ - .gpio16 = GPIO_MODE_NATIVE, /* SATA4GP */ - .gpio17 = GPIO_MODE_GPIO, /* DGPU POWEROK */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ - .gpio19 = GPIO_MODE_NATIVE, /* BBS0 */ - .gpio20 = GPIO_MODE_NATIVE, /* CIECLKRQ2# */ - .gpio21 = GPIO_MODE_NATIVE, /* SATA0GP */ - .gpio22 = GPIO_MODE_GPIO, /* BIOS Recovery */ - .gpio23 = GPIO_MODE_NATIVE, /* LDRQ1 */ - .gpio24 = GPIO_MODE_NONE, /* HOST ALERT */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ - .gpio26 = GPIO_MODE_NATIVE, /* PCIECLKRQ4# */ - .gpio27 = GPIO_MODE_GPIO, /* SATA0 PWR EN */ - .gpio28 = GPIO_MODE_GPIO, /* PLL ODVR */ - .gpio29 = GPIO_MODE_GPIO, /* SLP_LAN# */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_OUTPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, - .gpio30 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_HIGH, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_HIGH, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_HIGH, - .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_HIGH, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio3 = GPIO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* SIO CLKREQ */ - .gpio33 = GPIO_MODE_NATIVE, /* DOCK ENABLE*/ - .gpio34 = GPIO_MODE_GPIO, /* STP PCI LED */ - .gpio35 = GPIO_MODE_NATIVE, /* SATA POWER EN */ - .gpio36 = GPIO_MODE_NATIVE, /* SATA2 PRESENT DET */ - .gpio37 = GPIO_MODE_NONE, /* NOT USED */ - .gpio38 = GPIO_MODE_GPIO, /* MFG MODE */ - .gpio39 = GPIO_MODE_GPIO, /* GP39 GFX CRB DET */ - .gpio40 = GPIO_MODE_NATIVE, /* USB OC 2-3 */ - .gpio41 = GPIO_MODE_NATIVE, /* USB OC 4-5 */ - .gpio42 = GPIO_MODE_NATIVE, /* USB OC 6-7 */ - .gpio43 = GPIO_MODE_NATIVE, /* USB OC 8-9 */ - .gpio44 = GPIO_MODE_NATIVE, /* PCI SLOT5 CLKREQ5 */ - .gpio45 = GPIO_MODE_NATIVE, /* LAN CLKREQ6 */ - .gpio46 = GPIO_MODE_GPIO, /* PCI SLOT5 CLKREQ5 */ - .gpio47 = GPIO_MODE_NATIVE, /* PEG CLKREQ7 */ - .gpio48 = GPIO_MODE_GPIO, /* SV_ADVANCE_GP48 */ - .gpio49 = GPIO_MODE_GPIO, /* CRIT_TEMP */ - .gpio50 = GPIO_MODE_GPIO, /* DGPU RESET */ - .gpio51 = GPIO_MODE_NONE, /* NOT USED */ - .gpio52 = GPIO_MODE_GPIO, /* DGPU SEL */ - .gpio53 = GPIO_MODE_GPIO, /* DGPU PWM SEL */ - .gpio54 = GPIO_MODE_GPIO, /* DGPU PWM EN */ - .gpio55 = GPIO_MODE_NONE, /* NOT USED */ - .gpio56 = GPIO_MODE_NATIVE, /* NOT USED */ - .gpio57 = GPIO_MODE_NATIVE, /* GP57_SV_DETECT */ - .gpio58 = GPIO_MODE_NATIVE, /* SML1CLK_PCH */ - .gpio59 = GPIO_MODE_NATIVE, /* USB OC 0-1 */ - .gpio60 = GPIO_MODE_GPIO, /* DDR RST CTRL */ - .gpio61 = GPIO_MODE_NATIVE, /* LPC SUSTAT */ - .gpio62 = GPIO_MODE_NATIVE, /* LPC SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* SLP S5*/ - -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_OUTPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_OUTPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_OUTPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_OUTPUT, - .gpio55 = GPIO_DIR_OUTPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_HIGH, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_HIGH, - .gpio42 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_LOW, - .gpio48 = GPIO_LEVEL_HIGH, - .gpio49 = GPIO_LEVEL_HIGH, - .gpio50 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_HIGH, - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_HIGH, - .gpio62 = GPIO_LEVEL_HIGH, - .gpio63 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, /* CLK_FLEX0 */ - .gpio65 = GPIO_MODE_NATIVE, /* NOT USED / CLK_FLEX1 */ - .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 */ - .gpio67 = GPIO_MODE_GPIO, /* GPU PRSNT */ - .gpio68 = GPIO_MODE_GPIO, /* SATA PORT2 PWR EN*/ - .gpio69 = GPIO_MODE_GPIO, /* TESTMODE */ - .gpio70 = GPIO_MODE_NATIVE, /* USB3 SLOT 2DET */ - .gpio71 = GPIO_MODE_NATIVE, /* USB3 SLOT 1 DET */ - .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# */ - .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0#*/ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT# /PCHHOT# */ - .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_OUTPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_INPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_HIGH, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_HIGH, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_HIGH, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, - .gpio73 = GPIO_LEVEL_HIGH, - .gpio74 = GPIO_LEVEL_HIGH, - .gpio75 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/intel/cougar_canyon2/hda_verb.c b/src/mainboard/intel/cougar_canyon2/hda_verb.c deleted file mode 100644 index a110246622..0000000000 --- a/src/mainboard/intel/cougar_canyon2/hda_verb.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ - AZALIA_SUBVENDOR(0x0, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c deleted file mode 100644 index 01febd6d84..0000000000 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/fsp_bd82x6x/pch.h> - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} -#endif - - - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/cougar_canyon2/mainboard_smi.c b/src/mainboard/intel/cougar_canyon2/mainboard_smi.c deleted file mode 100644 index 731a842ca4..0000000000 --- a/src/mainboard/intel/cougar_canyon2/mainboard_smi.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/fsp_bd82x6x/nvs.h> -#include <southbridge/intel/fsp_bd82x6x/pch.h> -#include <southbridge/intel/fsp_bd82x6x/me.h> -#include <northbridge/intel/fsp_sandybridge/sandybridge.h> -#include <cpu/intel/fsp_model_206ax/model_206ax.h> - -/* - * Change LED_POWER# (SIO GPIO 45) state based on sleep type. - * The IO address is hardcoded as we don't have device path in SMM. - */ -#define SIO_GPIO_BASE_SET4 (0x730 + 3) -#define SIO_GPIO_BLINK_GPIO45 0x25 -void mainboard_smi_sleep(u8 slp_typ) -{ - u8 reg8; - - switch (slp_typ) { - case SLP_TYP_S3: - case SLP_TYP_S4: - break; - - case SLP_TYP_S5: - /* Turn off LED */ - reg8 = inb(SIO_GPIO_BASE_SET4); - reg8 |= (1 << 5); - outb(reg8, SIO_GPIO_BASE_SET4); - break; - } -} - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); - intel_model_206ax_finalize_smm(); - - mainboard_finalized = 1; - break; - } - return 0; -} diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c deleted file mode 100644 index 45da7d1fdf..0000000000 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - - -#include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <cbmem.h> -#include <console/console.h> -#include <halt.h> -#include <reset.h> -#include <superio/smsc/sio1007/chip.h> -#include <fsp_util.h> -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#include <northbridge/intel/fsp_sandybridge/raminit.h> -#include <southbridge/intel/fsp_bd82x6x/pch.h> -#include <southbridge/intel/fsp_bd82x6x/gpio.h> -#include <southbridge/intel/fsp_bd82x6x/me.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include "gpio.h" -#include <arch/stages.h> - -#define SIO_PORT 0x164e - -static inline void reset_system(void) -{ - hard_reset(); - halt(); -} - -static void pch_enable_lpc(void) -{ - device_t dev = PCH_LPC_DEV; - - /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); - - /* Enable SuperIO + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); - - /* Map 256 bytes at 0x1600 to the LPC bus. */ - pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); - - /* Map a range for the runtime registers to the LPC bus. */ - pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - - if (sio1007_enable_uart_at(SIO_PORT)) { - pci_write_config16(dev, LPC_EN, - lpc_config | COMA_LPC_EN); - } -} - -static void setup_sio_gpios(void) -{ - const u16 port = SIO_PORT; - const u16 runtime_port = 0x180; - - /* Turn on configuration mode. */ - outb(0x55, port); - - /* Set the GPIO direction, polarity, and type. */ - sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); - sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); - sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); - - /* Set the base address for the runtime register block. */ - sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); - sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); - - /* Turn on address decoding for it. */ - sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); - - /* - * Enable the RS232 transiver. - * Set the value of GPIO 10 by changing GP1, bit 0. - */ - u8 byte; - byte = inb(runtime_port + 0xc); - byte |= (1 << 0); - outb(byte, runtime_port + 0xc); - - /* Turn off address decoding for it. */ - sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); - - /* Turn off configuration mode. */ - outb(0xaa, port); -} - -static void rcba_config(void) -{ - u32 reg32; - - /* - * GFX INTA -> PIRQA (MSI) - * D31IP_SIP SATA INTB -> PIRQD - * D31IP_SMIP SMBUS INTC -> PIRQC - * D31IP_SIP SATA2 INTB -> PIRQD - * D31IP_TTIP THRT INTC -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D28IP_P1IP INTA -> PIRQD - * D28IP_P2IP INTB -> PIRQC - * D28IP_P3IP INTC -> PIRQB - * D28IP_P4IP INTD -> PIRQA - * D28IP_P5IP INTA -> PIRQD - * D28IP_P6IP INTB -> PIRQC - * D28IP_P7IP INTC -> PIRQB - * D28IP_P8IP INTD -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQD (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTB << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) | - (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | - (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (INTA << D25IP_LIP); - RCBA32(D22IP) = (INTB << D22IP_KTIP) | (INTC << D22IP_IDERIP) | - (INTB << D22IP_MEI2IP) | (INTA << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); - DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); - DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQF, PIRQA, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); - DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - reg32 |= PCH_DISABLE_ALWAYS; - RCBA32(FD) = reg32; -} - -void main(FSP_INFO_HEADER *fsp_info_header) -{ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - int boot_mode = 0; -#endif - u32 pm1_cnt; - u16 pm1_sts; - - post_code(0x40); - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&gpio_map); - setup_sio_gpios(); - - console_init(); - post_code(0x41); - - post_code(0x42); - sandybridge_sb_early_initialization(); - - post_code(0x43); - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - post_code(0x44); - /* Wait for ME to be ready */ - intel_early_me_status(); - intel_early_me_init(); - intel_early_me_uma_size(); - - post_code(0x45); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - post_code(0x46); - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif - } - - post_code(0x48); - - timestamp_add_now(TS_BEFORE_INITRAM); - - /* - * Call early init to initialize memory and chipset. This function returns - * to the romstage_main_continue function with a pointer to the HOB - * structure. - */ - printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); - fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); -} - -/******************************************************************************* - * The FSP early_init function returns to this function. - * Memory is setup and the stack is set by the FSP. - ******************************************************************************/ -void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { - int cbmem_was_initted; - u32 reg32; - void *cbmem_hob_ptr; - - timestamp_add_now(TS_AFTER_INITRAM); - - /* - * HD AUDIO is not used on this system, so we're using some registers - * in there as temporary registers to save TSC values. This is complete - * now, so disable the audio block. - */ - reg32 = RCBA32(FD); - reg32 |= PCH_DISABLE_HD_AUDIO; - RCBA32(FD) = reg32; - - post_code(0x49); - -#if CONFIG_USBDEBUG - /* FSP reconfigures USB, so reinit it to have debug */ - early_usbdebug_init(); -#endif - - /* For reference print FSP version */ - u32 version = MCHBAR32(0x5034); - printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n", - version >> 24 , (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); - printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); - - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); - - printk(BIOS_SPEW, "FD & FD2 Settings:\n"); - display_fd_settings(); - - report_memory_config(); - - post_code(0x4b); - - early_pch_init(); - post_code(0x4c); - - rcba_config(); - post_code(0x4d); - - quick_ram_check(); - post_code(0x4e); - - cbmem_was_initted = !cbmem_recovery(0); - - if(cbmem_was_initted) { - reset_system(); - } - - /* Save the HOB pointer in CBMEM to be used in ramstage. */ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*HobListPtr)); - *(u32*)cbmem_hob_ptr = (u32)HobListPtr; - post_code(0x4f); - - /* Load the ramstage. */ - copy_and_run(); - while (1); -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} - -uint64_t get_initial_timestamp(void) -{ - return (uint64_t) pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 4; -} diff --git a/src/mainboard/intel/cougar_canyon2/thermal.h b/src/mainboard/intel/cougar_canyon2/thermal.h deleted file mode 100644 index 7d61e6a408..0000000000 --- a/src/mainboard/intel/cougar_canyon2/thermal.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 -#define FAN0_PWM 0xff - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 105 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 91 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig deleted file mode 100644 index e1f2e888fd..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - -config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE - bool - select CPU_INTEL_FSP_MODEL_206AX - select INTEL_GMA_ACPI - -config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE - bool - select CPU_INTEL_FSP_MODEL_306AX - select INTEL_GMA_ACPI - -if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0106" - help - This is the default PCI ID for the sandybridge/ivybridge graphics - devices. This string names the vbios ROM in cbfs. The following - PCI IDs will be remapped to load this ROM: - 0x80860102, 0x8086010a, 0x80860112, 0x80860116 - 0x80860122, 0x80860126, 0x80860166 - -# Ivybridge Specific FSP Kconfig -source src/northbridge/intel/fsp_sandybridge/fsp/Kconfig - -endif # NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc deleted file mode 100644 index 6c5e09f9b4..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2010 Google Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc. -# - -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE),y) - -subdirs-y += fsp -ramstage-y += northbridge.c -ramstage-y += ram_calc.c -ramstage-y += gma.c - -ramstage-y += acpi.c - -romstage-y += raminit.c -romstage-y += ram_calc.c -romstage-y += early_init.c -romstage-y += report_platform.c -romstage-y += ../../../arch/x86/walkcbfs.S - -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c - -CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_sandybridge/fsp - -endif diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c deleted file mode 100644 index 1e20945138..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <drivers/intel/gma/i915.h> -#include <arch/acpigen.h> -#include "northbridge.h" -#include <cbmem.h> - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0); - if (!dev) - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0); - if (!dev) - return current; - - pciexbar_reg=pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); - - return current; -} - -static void *get_intel_vbios(void) -{ - /* This should probably be looking at CBFS or we should always - * deploy the VBIOS on Intel systems, even if we don't run it - * in coreboot (e.g. SeaBIOS only scenarios). - */ - u8 *vbios = (u8 *)0xc0000; - - optionrom_header_t *oprom = (optionrom_header_t *)vbios; - optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios + - oprom->pcir_offset); - - - printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n", - oprom->signature, pcir->vendor, pcir->classcode[0], - pcir->classcode[1], pcir->classcode[2]); - - - if ((oprom->signature == OPROM_SIGNATURE) && - (pcir->vendor == PCI_VENDOR_ID_INTEL) && - (pcir->classcode[0] == 0x00) && - (pcir->classcode[1] == 0x00) && - (pcir->classcode[2] == 0x03)) - return (void *)vbios; - - return NULL; -} - -static int init_opregion_vbt(igd_opregion_t *opregion) -{ - void *vbios; - vbios = get_intel_vbios(); - if (!vbios) { - printk(BIOS_DEBUG, "VBIOS not found.\n"); - return 1; - } - - printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios); - optionrom_header_t *oprom = (optionrom_header_t *)vbios; - optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios + - oprom->vbt_offset); - - if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { - printk(BIOS_DEBUG, "VBT not found!\n"); - return 1; - } - - memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); - memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ? - vbt->hdr_vbt_size : 7168); - - return 0; -} - - -/* Initialize IGD OpRegion, called from ACPI code */ -int init_igd_opregion(igd_opregion_t *opregion) -{ - device_t igd; - u16 reg16; - - memset((void *)opregion, 0, sizeof(igd_opregion_t)); - - // FIXME if IGD is disabled, we should exit here. - - memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(opregion->header.signature)); - - /* 8kb */ - opregion->header.size = sizeof(igd_opregion_t) / 1024; - opregion->header.version = IGD_OPREGION_VERSION; - - // FIXME We just assume we're mobile for now - opregion->header.mailboxes = MAILBOXES_MOBILE; - - // TODO Initialize Mailbox 1 - - // TODO Initialize Mailbox 3 - opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; - opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; - opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e - opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; - opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; - opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; - opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; - opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; - opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; - opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; - opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; - opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; - opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; - opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; - opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - init_opregion_vbt(opregion); - - /* TODO This needs to happen in S3 resume, too. - * Maybe it should move to the finalize handler - */ - igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); - - pci_write_config32(igd, ASLS, (u32)opregion); - reg16 = pci_read_config16(igd, SWSCI); - reg16 &= ~(1 << 0); - reg16 |= (1 << 15); - pci_write_config16(igd, SWSCI, reg16); - - /* clear dmisci status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 |= DMISCI_STS; // reference code does an &= - outw(DEFAULT_PMBASE + TCO1_STS, reg16); - - /* clear acpi tco status */ - outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - - /* enable acpi tco scis */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(DEFAULT_PMBASE + GPE0_EN, reg16); - - return 0; -} - -void *igd_make_opregion(void) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof (*opregion)); - if (opregion) - init_igd_opregion(opregion); - return opregion; -} diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl deleted file mode 100644 index a1b99b899c..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_ADR, 0) -Name(_BBN, 0) - -Device (MCHC) -{ - Name(_ADR, 0x00000000) // 0:0.0 - - OperationRegion(MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 24, // EPBAR - - Offset (0x48), // MCHBAR - MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR - - Offset (0x60), // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 10, // PCIe BAR - - Offset (0x68), // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 24, // DMIBAR - - Offset (0x70), // ME Base Address - MEBA, 64, - - // ... - - Offset (0x80), // PAM0 - , 4, - PM0H, 2, - , 2, - Offset (0x81), // PAM1 - PM1L, 2, - , 2, - PM1H, 2, - , 2, - Offset (0x82), // PAM2 - PM2L, 2, - , 2, - PM2H, 2, - , 2, - Offset (0x83), // PAM3 - PM3L, 2, - , 2, - PM3H, 2, - , 2, - Offset (0x84), // PAM4 - PM4L, 2, - , 2, - PM4H, 2, - , 2, - Offset (0x85), // PAM5 - PM5L, 2, - , 2, - PM5H, 2, - , 2, - Offset (0x86), // PAM6 - PM6L, 2, - , 2, - PM6H, 2, - , 2, - - Offset (0xa0), // Top of Used Memory - TOM, 64, - - Offset (0xbc), // Top of Low Used Memory - TLUD, 32, - } - - Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ - Name (CTCC, 0) /* CTDP Current Selection */ - Name (CTCN, 0) /* CTDP Nominal Select */ - Name (CTCD, 1) /* CTDP Down Select */ - Name (CTCU, 2) /* CTDP Up Select */ - - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) - Field (MCHB, DWordAcc, Lock, Preserve) - { - Offset (0x5930), - CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x59a0), - PL1V, 15, /* Power Limit 1 Value */ - PL1E, 1, /* Power Limit 1 Enable */ - PL1C, 1, /* Power Limit 1 Clamp */ - PL1T, 7, /* Power Limit 1 Time */ - Offset (0x59a4), - PL2V, 15, /* Power Limit 2 Value */ - PL2E, 1, /* Power Limit 2 Enable */ - PL2C, 1, /* Power Limit 2 Clamp */ - PL2T, 7, /* Power Limit 2 Time */ - Offset (0x5f3c), - TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0x5f40), - CTDD, 15, /* CTDP Down PL1 */ - , 1, - TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0x5f48), - CTDU, 15, /* CTDP Up PL1 */ - , 1, - TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0x5f50), - CTCS, 2, /* CTDP Select */ - Offset (0x5f54), - TARS, 8, /* Turbo Activation Ratio Select */ - } - - /* - * Search CPU0 _PSS looking for control=arg0 and then - * return previous P-state entry number for new _PPC - * - * Format of _PSS: - * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } - * } - */ - External (\_PR.CP00._PSS) - Method (PSSS, 1, NotSerialized) - { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CP00._PSS), Local1) - - While (LLess (Local0, Local1)) { - /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) - } - Increment (Local0) - } - - Return (0) - } - - /* Set TDP Down */ - Method (STND, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (LEqual (CTCD, CTCC)) { - Release (CTCM) - Return (0) - } - - Store ("Set TDP Down", Debug) - - /* Set CTC */ - Store (CTCD, CTCS) - - /* Set TAR */ - Store (TARD, TARS) - - /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) - PPCN () - - /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, Local0, PL2V) - - /* Set PL1 */ - Store (CTDD, PL1V) - - /* Store the new TDP Down setting */ - Store (CTCD, CTCC) - - Release (CTCM) - Return (1) - } - - /* Set TDP Nominal from Down */ - Method (STDN, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (LEqual (CTCN, CTCC)) { - Release (CTCM) - Return (0) - } - - Store ("Set TDP Nominal", Debug) - - /* Set PL1 */ - Store (CTDN, PL1V) - - /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, Local0, PL2V) - - /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) - PPCN () - - /* Set TAR */ - Store (TARN, TARS) - - /* Set CTC */ - Store (CTCN, CTCS) - - /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) - - Release (CTCM) - Return (1) - } -} - -// Current Resource Settings - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR3) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) - - // Fix up PCI memory region - // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) - - // Check if ME base is equal - If (LEqual (Local0, Local1)) { - // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) - } - - Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) - - Return (MCRS) -} - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/hostbridge_pci_irqs.asl" diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl deleted file mode 100644 index df8a389797..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -Device (GFX0) -{ - Name (_ADR, 0x00020000) - - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), - BAR0, 64 - } - - OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) - Field (GFRG, DWordAcc, NoLock, Preserve) - { - Offset (0x48254), - BCLV, 16, - Offset (0xc8250), - CR1, 32, - CR2, 32 - } - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (XBCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), BCLV) - Store (0x80000000, CR1) - Store (0x061a061a, CR2) - } - - Method (XBQC, 0, NotSerialized) - { - Store (BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } -#include <drivers/intel/gma/igd.asl> -} diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl deleted file mode 100644 index 1c853e1208..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include "../northbridge.h" -#include "hostbridge.asl" - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) - Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH - -#if CONFIG_CHROMEOS_RAMOOPS - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - - /* Required for SandyBridge sighting 3715511 */ - Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) - Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return(PDRS) - } -} - -// Integrated graphics 0:2.0 -#include "igd.asl" diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h deleted file mode 100644 index 6e823dc986..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <drivers/intel/gma/i915.h> - -/* - * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse - * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse - * 0x07 = Enabled, 100ms short pulse - */ -struct northbridge_intel_fsp_sandybridge_config { - u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ - u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ - u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ - u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ - u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ - - u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - - struct i915_gpu_controller_info gfx; -}; diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c deleted file mode 100644 index 6ba1ab6828..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/early_init.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <console/console.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <elog.h> -#include "northbridge.h" - -static void sandybridge_setup_bars(void) -{ - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); - /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - -#if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif -} - -void sandybridge_early_initialization(int chipset_type) -{ - u32 capid0_a; - u8 reg8; - - /* Device ID Override Enable should be done very early */ - capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); - if (capid0_a & (1 << 10)) { - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); - } - - /* Setup all BARs required for early PCIe and raminit */ - sandybridge_setup_bars(); -} diff --git a/src/northbridge/intel/fsp_sandybridge/finalize.c b/src/northbridge/intel/fsp_sandybridge/finalize.c deleted file mode 100644 index 90c3635a7c..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/finalize.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <stdlib.h> -#include "northbridge.h" - -#define PCI_DEV_SNB PCI_DEV(0, 0, 0) - -void intel_sandybridge_finalize_smm(void) -{ - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ - - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); - - /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; - - /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); -} diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/Kconfig b/src/northbridge/intel/fsp_sandybridge/fsp/Kconfig deleted file mode 100644 index 82e5361505..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - -config SANDYBRIDGE_FSP_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select USE_GENERIC_FSP_CAR_INC - -config FSP_FILE - string - default "../intel/fsp/ivybridge_bd82x6x/FvFsp.bin" if SOUTHBRIDGE_INTEL_FSP_BD82X6X - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex "Intel FSP Binary location in CBFS" - default 0xfff80000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with the Intel's BCT (tool). - - The Ivy Bridge Processor/Panther Point FSP is built with a preferred - base address of 0xFFF80000 diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc deleted file mode 100644 index 282570351b..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc. -# - -ramstage-y += chipset_fsp_util.c -romstage-y += chipset_fsp_util.c diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c deleted file mode 100644 index e9dad29f4c..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <bootstate.h> -#include <cbmem.h> -#include <device/device.h> -#include <southbridge_pci_devs.h> -#include <fsp_util.h> -#include "../chip.h" -#include <reset.h> - -#ifndef CONFIG_ENABLE_FSP_FAST_BOOT -# error "CONFIG_ENABLE_FSP_FAST_BOOT must be set." -#endif - -#ifdef __PRE_RAM__ - -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) -static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - VPD_DATA_REGION *VpdDataRgnPtr; - UPD_DATA_REGION *UpdDataRgnPtr; - VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); - UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); -} - -static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) -{ - UpdData->HTEnable = TRUE; - UpdData->TurboEnable = FALSE; - UpdData->MemoryDownEnable = FALSE; - UpdData->FastBootEnable = CONFIG_ENABLE_FSP_FAST_BOOT; -} -#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) */ -const PLATFORM_CONFIG DefaultPlatformConfig = { - TRUE, /* Hyperthreading */ - FALSE, /* Turbo Mode */ - FALSE, /* Memory Down */ -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) - TRUE, /* Fast Boot */ -#else - FALSE, /* Fast Boot */ -#endif /* CONFIG_ENABLE_FSP_FAST_BOOT */ -}; -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) */ - -/* - * - * Call the FSP to do memory init. The FSP doesn't return to this function. - * The FSP returns to the romstage_main_continue(). - * - */ -void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, - FSP_INFO_HEADER *fsp_ptr) -{ - FSP_INIT_RT_BUFFER *pFspRtBuffer = FspInitParams->RtBufferPtr; -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) - UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr; -#else - MEM_CONFIG MemoryConfig; - memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG)); -#endif - FspInitParams->NvsBufferPtr = NULL; - -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) - /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); - ConfigureDefaultUpdData(fsp_upd_data); -#else - pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; - pFspRtBuffer->PlatformConfiguration.PlatformConfig = &DefaultPlatformConfig; -#endif - -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) - /* Find the fastboot cache that was saved in the ROM */ - FspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif - - pFspRtBuffer->Common.BootMode = 0; -} - -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; - if (Status == 0xFFFFFFFF) { - hard_reset(); - } - romstage_main_continue(Status, HobListPtr); -} - -#endif /* __PRE_RAM__ */ diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h deleted file mode 100644 index cb0434776b..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef CHIPSET_FSP_UTIL_H -#define CHIPSET_FSP_UTIL_H - -#include <fsptypes.h> -#include <fspfv.h> -#include <fspffs.h> -#include <fspapi.h> -#include <fspplatform.h> -#include <fspinfoheader.h> -#include <fsphob.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) -#include <peifsp.h> -#include <fsp_vpd.h> -#endif - -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - { \ - 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ - } - - -/* - *The FSP Image ID is different for each platform's FSP and - * can be used to verify that the right FSP binary is loaded. - */ - -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) -/* ST2-FSP0 */ -#define FSP_IMAGE_ID_DWORD0 0x2D325453 -#define FSP_IMAGE_ID_DWORD1 0x30505346 -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) -/* CC2-FSP\0 */ -#define FSP_IMAGE_ID_DWORD0 0x2D324343 -#define FSP_IMAGE_ID_DWORD1 0x00505346 -#endif - -#ifdef __PRE_RAM__ -void main(FSP_INFO_HEADER *fsp_info_header); -void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr); -#endif - -#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c deleted file mode 100644 index 132a1b869b..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Chromium OS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#include "chip.h" -#include "northbridge.h" - - -/* some vga option roms are used for several chipsets but they only have one - * PCI ID in their header. If we encounter such an option rom, we need to do - * the mapping ourselfes - */ - -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev=vendev; - - switch (vendev) { - case 0x80860102: /* GT1 Desktop */ - case 0x8086010a: /* GT1 Server */ - case 0x80860112: /* GT2 Desktop */ - case 0x80860116: /* GT2 Mobile */ - case 0x80860122: /* GT2 Desktop >=1.3GHz */ - case 0x80860126: /* GT2 Mobile >=1.3GHz */ - case 0x80860166: /* IVB */ - new_vendev=0x80860106; /* GT1 Mobile */ - break; - } - - return new_vendev; -} - -static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) -{ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); - if (!dev) { - return NULL; - } - struct northbridge_intel_fsp_sandybridge_config *chip = dev->chip_info; - return &chip->gfx; -} - -static void gma_ssdt(device_t device) -{ - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - if (!gfx) { - return; - } - - drivers_intel_gma_displays_ssdt_generate(gfx); -} - -static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, -}; - -static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = gma_ssdt, - .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, -}; - -static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x166, - 0, -}; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= gma_ids, -}; diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h deleted file mode 100644 index 9cc2241410..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/gma.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Chromium OS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* mailbox 0: header */ -typedef struct { - u8 signature[16]; - u32 size; - u32 version; - u8 sbios_version[32]; - u8 vbios_version[16]; - u8 driver_version[16]; - u32 mailboxes; - u8 reserved[164]; -} __attribute__((packed)) opregion_header_t; - -#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" -#define IGD_OPREGION_VERSION 2 - -#define IGD_MBOX1 (1 << 0) -#define IGD_MBOX2 (1 << 1) -#define IGD_MBOX3 (1 << 2) -#define IGD_MBOX4 (1 << 3) -#define IGD_MBOX5 (1 << 4) - -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) -#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) - -#define SBIOS_VERSION_SIZE 32 - -/* mailbox 1: public acpi methods */ -typedef struct { - u32 drdy; - u32 csts; - u32 cevt; - u8 reserved1[20]; - u32 didl[8]; - u32 cpdl[8]; - u32 cadl[8]; - u32 nadl[8]; - u32 aslp; - u32 tidx; - u32 chpd; - u32 clid; - u32 cdck; - u32 sxsw; - u32 evts; - u32 cnot; - u32 nrdy; - u8 reserved2[60]; -} __attribute__((packed)) opregion_mailbox1_t; - -/* mailbox 2: software sci interface */ -typedef struct { - u32 scic; - u32 parm; - u32 dslp; - u8 reserved[244]; -} __attribute__((packed)) opregion_mailbox2_t; - -/* mailbox 3: power conservation */ -typedef struct { - u32 ardy; - u32 aslc; - u32 tche; - u32 alsi; - u32 bclp; - u32 pfit; - u32 cblv; - u16 bclm[20]; - u32 cpfm; - u32 epfm; - u8 plut[74]; - u32 pfmb; - u32 ccdv; - u32 pcft; - u8 reserved[94]; -} __attribute__((packed)) opregion_mailbox3_t; - -#define IGD_BACKLIGHT_BRIGHTNESS 0xff -#define IGD_INITIAL_BRIGHTNESS 0x64 - -#define IGD_FIELD_VALID (1 << 31) -#define IGD_WORD_FIELD_VALID (1 << 15) -#define IGD_PFIT_STRETCH 6 - -/* mailbox 4: vbt */ -typedef struct { - u8 gvd1[7168]; -} __attribute__((packed)) opregion_vbt_t; - -/* IGD OpRegion */ -typedef struct { - opregion_header_t header; - opregion_mailbox1_t mailbox1; - opregion_mailbox2_t mailbox2; - opregion_mailbox3_t mailbox3; - opregion_vbt_t vbt; -} __attribute__((packed)) igd_opregion_t; - -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c deleted file mode 100644 index 3f982c4a17..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <stdint.h> -#include <delay.h> -#include <cpu/intel/fsp_model_206ax/model_206ax.h> -#include <cpu/x86/msr.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/hypertransport.h> -#include <stdlib.h> -#include <string.h> -#include <cpu/cpu.h> -#include <cbmem.h> -#include "chip.h" -#include "northbridge.h" -#include <fsp_util.h> -#include <cpu/intel/smm/gen1/smi.h> - -static int bridge_revision_id = -1; - -/* IGD UMA memory */ -static uint64_t uma_memory_base = 0; -static uint64_t uma_memory_size = 0; - -int bridge_silicon_revision(void) -{ - if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( - dev_find_slot(0, PCI_DEVFN(0, 0)), - PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; - } - return bridge_revision_id; -} - -/* Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - -static int get_pcie_bar(u32 *base, u32 *len) -{ - device_t dev; - u32 pciexbar_reg; - - *base = 0; - *len = 0; - - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (!dev) - return 0; - - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); -} - -static void pci_domain_set_resources(device_t dev) -{ - uint64_t tom, me_base, touud; - uint32_t tseg_base, uma_size, tolud; - uint16_t ggc; - unsigned long long tomk; - - tomk = ggc = tseg_base = uma_size = tolud = tom = me_base = touud = 0; - - /* Total Memory 2GB example: - * - * 00000000 0000MB-1992MB 1992MB RAM (writeback) - * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) - * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) - * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) - * 7f200000 2034MB TOLUD - * 7f800000 2040MB MEBASE - * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) - * 80000000 2048MB TOM - * 100000000 4096MB-4102MB 6MB RAM (writeback) - * - * Total Memory 4GB example: - * - * 00000000 0000MB-2768MB 2768MB RAM (writeback) - * ad000000 2768MB-2776MB 8MB TSEG (SMRR) - * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) - * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) - * afa00000 2810MB TOLUD - * ff800000 4088MB MEBASE - * ff800000 4088MB-4096MB 8MB ME UMA (uncached) - * 100000000 4096MB TOM - * 100000000 4096MB-5374MB 1278MB RAM (writeback) - * 14fe00000 5368MB TOUUD - */ - - /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(dev, TOUUD+4); - touud <<= 32; - touud |= pci_read_config32(dev, TOUUD) & ~(1UL << 0); - - /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(dev, TOLUD) & ~(1UL << 0); - - /* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(dev, 0xa4); - tom <<= 32; - tom |= pci_read_config32(dev, 0xa0) & ~(1UL << 0); - - printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", - touud, tolud, tom); - - /* ME UMA needs excluding if total memory <4GB */ - me_base = pci_read_config32(dev, 0x74); - me_base <<= 32; - me_base |= pci_read_config32(dev, 0x70); - - printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); - - tomk = tolud >> 10; - if (me_base == tolud) { - /* ME is from MEBASE-TOM */ - uma_size = (tom - me_base) >> 10; - /* Increment TOLUD to account for ME as RAM */ - tolud += uma_size << 10; - /* UMA starts at old TOLUD */ - uma_memory_base = tomk * 1024ULL; - uma_memory_size = uma_size * 1024ULL; - printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", - me_base, uma_size >> 10); - } - - /* Graphics memory comes next */ - ggc = pci_read_config16(dev, GGC); - if (!(ggc & 2)) { - printk(BIOS_DEBUG, "IGD decoded, subtracting "); - - /* Graphics memory */ - uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; - printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); - tomk -= uma_size; - uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; - - /* GTT Graphics Stolen Memory Size (GGMS) */ - uma_size = ((ggc >> 8) & 0x3) * 1024ULL; - tomk -= uma_size; - uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; - printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); - } - - /* Calculate TSEG size from its base which must be below GTT */ - uma_memory_base = tomk * 1024ULL; - tseg_base = pci_read_config32(dev, 0xb8) & ~(1UL << 0); - uma_size = (uma_memory_base - tseg_base) >> 10; - tomk -= uma_size; - uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; - printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", - tseg_base, uma_size >> 10); - - printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); - - /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (tomk - (legacy_hole_base_k + legacy_hole_size_k))); - - /* - * If >= 4GB installed then memory from TOLUD to 4GB - * is remapped above TOM, TOUUD will account for both - */ - touud >>= 10; /* Convert to KB */ - if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); - } - - add_fixed_resources(dev, 6); - - assign_resources(dev->link_list); -} - - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. - */ -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void mc_read_resources(device_t dev) -{ - struct resource *resource; - - pci_dev_read_resources(dev); - - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); -} - -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static void northbridge_init(struct device *dev) -{ - u8 bios_reset_cpl; - - /* - * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management - */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 1; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; - printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); -} - -static u32 northbridge_get_base_reg(device_t dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -void -northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) -{ - device_t dev; - u32 bgsm; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - *tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - *tseg_size = bgsm - *tsegmb; -} - -void northbridge_write_smram(u8 smram) -{ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); -} - -static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, -}; - -static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = mc_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, - .acpi_fill_ssdt_generator = generate_cpu_entries, -}; - -static const struct pci_driver mc_driver_0100 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0100, -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0104, /* Sandy bridge */ -}; - -static const struct pci_driver mc_driver_1 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0154, /* Ivy bridge */ -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(device_t dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_fsp_sandybridge_ops = { - CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h deleted file mode 100644 index 4861254902..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ - -/* Chipset types */ -#define SANDYBRIDGE_MOBILE 0 -#define SANDYBRIDGE_DESKTOP 1 -#define SANDYBRIDGE_SERVER 2 - -/* Device ID for SandyBridge and IvyBridge */ -#define BASE_REV_SNB 0x00 -#define BASE_REV_IVB 0x50 -#define BASE_REV_MASK 0x50 - -/* SandyBridge CPU stepping */ -#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ -#define SNB_STEP_D1 (BASE_REV_SNB + 6) -#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ - -/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 (BASE_REV_IVB + 0) -#define IVB_STEP_B0 (BASE_REV_IVB + 2) -#define IVB_STEP_C0 (BASE_REV_IVB + 4) -#define IVB_STEP_K0 (BASE_REV_IVB + 5) -#define IVB_STEP_D0 (BASE_REV_IVB + 6) - -/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 - -/* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X -#include <southbridge/intel/fsp_bd82x6x/pch.h> -#endif - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ - -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define X60BAR 0x60 - -#define GGC 0x50 /* GMCH Graphics Control */ - -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_PEG60 (1 << 13) -#define DEVEN_IGD (1 << 4) -#define DEVEN_PEG10 (1 << 3) -#define DEVEN_PEG11 (1 << 2) -#define DEVEN_PEG12 (1 << 1) -#define DEVEN_HOST (1 << 0) - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define LAC 0x87 /* Legacy Access Control */ -#define SMRAM 0x88 /* System Management RAM Control */ - -#define TOM 0xa0 -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ - -#define SKPAD 0xdc /* Scratchpad Data */ - -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - - -/* Device 0:2.0 PCI configuration space (Graphics Device) */ - -#define MSAC 0x62 /* Multi Size Aperture Control */ -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - -/* - * MCHBAR - */ - -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) - -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ - -/* - * EPBAR - Egress Port Root Complex Register Block - */ - -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) - -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCAP2 0x008 /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define PORTARB 0x100 /* 256bit */ - -/* - * DMIBAR - */ - -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) - -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ -#define DMIPVCCAP2 0x008 /* 32bit */ - -#define DMIPVCCCTL 0x00c /* 16bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL0 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ - -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ - -#define DMICC 0x208 /* 32bit */ - -#define DMIDRCCFG 0xeb4 /* 32bit */ - -#ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } - -#define PCI_DEVICE_ID_SB 0x0104 -#define PCI_DEVICE_ID_IB 0x0154 - -#ifdef __SMM__ -void intel_sandybridge_finalize_smm(void); -#else /* !__SMM__ */ -int bridge_silicon_revision(void); -void sandybridge_early_initialization(int chipset_type); -void sandybridge_late_initialization(void); - -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); -#endif /* !__SMM__ */ - - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -#if !defined(__PRE_RAM__) -#include "gma.h" -int init_igd_opregion(igd_opregion_t *igd_opregion); -#endif - -#endif -#endif -#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h b/src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h deleted file mode 100644 index b63149f61f..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ -#define _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* NB PCIe PEG slot */ -#define NB_PEG_DEV 0x01 -#define NB_PEG_FUNC 0 -# define NB_PEG_DEVFN PCI_DEVFN(NB_PEG_DEV, NB_PEG_FUNC) -#define PCIE_CTRL1_FUNC 1 -# define PCIE_CTRL1_DEVFN PCI_DEVFN(NB_PEG_DEV, PCIE_CTRL1_FUNC) -#define PCIE_CTRL2_FUNC 2 -# define PCIE_CTRL2_DEVFN PCI_DEVFN(NB_PEG_DEV, PCIE_CTRL2_FUNC) - -/* Onboard Graphics */ -#define GFX_DEV 0x02 -#define GFX_FUNC 0 -# define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) - -/* NB PCIe slot */ -#define NB_PCIE_DEV 0x06 -#define NB_PCIE_FUNC 0 -# define NB_PCIE_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_FUNC) - -#endif /* _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ */ diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c deleted file mode 100644 index 37d74fc617..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/ram_calc.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cbmem.h> -#include <fsp_util.h> -#include "northbridge.h" - -static uintptr_t smm_region_start(void) -{ - /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); - return tom; -} - -void *cbmem_top(void) -{ - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); -} diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c deleted file mode 100644 index 408b4b0611..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/raminit.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <string.h> -#include <arch/io.h> -#include <cbmem.h> -#include <device/pci_def.h> -#include "raminit.h" -#include "northbridge.h" - -static const char* ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active" -}; - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.h b/src/northbridge/intel/fsp_sandybridge/raminit.h deleted file mode 100644 index c97b64cb2c..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/raminit.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef RAMINIT_H -#define RAMINIT_H - -void report_memory_config(void); - -#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/report_platform.c b/src/northbridge/intel/fsp_sandybridge/report_platform.c deleted file mode 100644 index e661487a6f..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/report_platform.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <arch/cpu.h> -#include <string.h> - -#if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X -#include <southbridge/intel/fsp_bd82x6x/pch.h> -#endif - -#include <arch/io.h> -#include "northbridge.h" - -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - const char *mode[] = {"NOT ", ""}; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - cpuidr = cpuid(1); - printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_name); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - -/* The PCI id name match comes from Intel document 472178 */ -static struct { - u16 dev_id; - const char *dev_name; -} pch_table [] = { - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, -}; - -static void report_pch_info(void) -{ - int i; - u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); - - - const char *pch_type = "Unknown"; - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].dev_id == dev_id) { - pch_type = pch_table[i].dev_name; - break; - } - } - printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", - pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); -} - -void report_platform_info(void) -{ - report_cpu_info(); - report_pch_info(); -} diff --git a/src/northbridge/intel/fsp_sandybridge/udelay.c b/src/northbridge/intel/fsp_sandybridge/udelay.c deleted file mode 100644 index e6dcbf180e..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/udelay.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> - -/** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 100, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(0xce); - divisor = (msr.lo >> 8) & 0xff; - - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig deleted file mode 100644 index 85c6ee7862..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ /dev/null @@ -1,57 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - -config SOUTHBRIDGE_INTEL_FSP_BD82X6X - bool - -if SOUTHBRIDGE_INTEL_FSP_BD82X6X - -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select IOAPIC - select HAVE_HARD_RESET - select HAVE_SMI_HANDLER - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select SPI_FLASH - select COMMON_FADT - select HAVE_INTEL_FIRMWARE - -config EHCI_BAR - hex - default 0xfef00000 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/fsp_bd82x6x/bootblock.c" - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config HPET_MIN_TICKS - hex - default 0x80 - -endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc deleted file mode 100644 index d14d303c75..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ /dev/null @@ -1,51 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) - -ramstage-y += pch.c -ramstage-y += azalia.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += me.c -ramstage-y += me_8.x.c -ramstage-y += me_status.c -ramstage-y += reset.c -ramstage-y += watchdog.c - -ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += ../common/spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c - -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c - -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c - -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c -smm-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-y += reset.c -romstage-y += early_spi.c - -CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x - -endif diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/audio.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/audio.asl deleted file mode 100644 index 6679bd1126..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/audio.asl +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Intel PCH HDA */ - -// Intel High Definition Audio (Azalia) 0:1b.0 - -Device (HDEF) -{ - Name (_ADR, 0x001b0000) - - // Power Resources for Wake - Name (_PRW, Package(){ - 13, // Bit 13 of GPE - 4 // Can wake from S4 state. - }) -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl deleted file mode 100644 index f124eb0aee..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl +++ /dev/null @@ -1,286 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - /* Thermal policy */ - Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit - FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold - TPSV, 8, // 0x14 - Passive Threshold - TMAX, 8, // 0x15 - CPU Tj_max - F0OF, 8, // 0x16 - FAN 0 OFF Threshold - F0ON, 8, // 0x17 - FAN 0 ON Threshold - F0PW, 8, // 0x18 - FAN 0 PWM value - F1OF, 8, // 0x19 - FAN 1 OFF Threshold - F1ON, 8, // 0x1a - FAN 1 ON Threshold - F1PW, 8, // 0x1b - FAN 1 PWM value - F2OF, 8, // 0x1c - FAN 2 OFF Threshold - F2ON, 8, // 0x1d - FAN 2 ON Threshold - F2PW, 8, // 0x1e - FAN 2 PWM value - F3OF, 8, // 0x1f - FAN 3 OFF Threshold - F3ON, 8, // 0x20 - FAN 3 ON Threshold - F3PW, 8, // 0x21 - FAN 3 PWM value - F4OF, 8, // 0x22 - FAN 4 OFF Threshold - F4ON, 8, // 0x23 - FAN 4 ON Threshold - F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID - /* Processor Identification */ - Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable - PCP0, 8, // 0x2a - PDC CPU/CORE 0 - PCP1, 8, // 0x2b - PDC CPU/CORE 1 - PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count - /* Super I/O & CMOS config */ - Offset (0x32), - NATP, 8, // 0x32 - - S5U0, 8, // 0x33 - Enable USB0 in S5 - S5U1, 8, // 0x34 - Enable USB1 in S5 - S3U0, 8, // 0x35 - Enable USB0 in S3 - S3U1, 8, // 0x36 - Enable USB1 in S3 - S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC - /* Integrated Graphics Device */ - Offset (0x3c), - IGDS, 8, // 0x3c - IGD state (primary = 1) - TLST, 8, // 0x3d - Display Toggle List pointer - CADL, 8, // 0x3e - Currently Attached Devices List - PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 - /* Backlight Control */ - Offset (0x64), - BLCS, 8, // 0x64 - Backlight control possible? - BRTL, 8, // 0x65 - Brightness Level - ODDS, 8, // 0x66 - /* Ambient Light Sensors */ - Offset (0x6e), - ALSE, 8, // 0x6e - ALS enable - ALAF, 8, // 0x6f - Ambient light adjustment factor - LLOW, 8, // 0x70 - LUX Low - LHIH, 8, // 0x71 - LUX High - /* EMA */ - Offset (0x78), - EMAE, 8, // 0x78 - EMA enable - EMAP, 16, // 0x79 - EMA pointer - EMAL, 16, // 0x7b - EMA length - /* MEF */ - Offset (0x82), - MEFE, 8, // 0x82 - MEF enable - /* TPM support */ - Offset (0x8c), - TPMP, 8, // 0x8c - TPM - TPME, 8, // 0x8d - TPM enable - /* SATA */ - Offset (0x96), - GTF0, 56, // 0x96 - GTF task file buffer for port 0 - GTF1, 56, // 0x9d - GTF task file buffer for port 1 - GTF2, 56, // 0xa4 - GTF task file buffer for port 2 - IDEM, 8, // 0xab - IDE mode (compatible / enhanced) - IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> -} - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) - Store (One, \S3U1) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) - Store (Zero, \S3U1) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) - Store (One, \S5U1) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) - Store (Zero, \S5U1) -} - -/* Set flag to enable 3G module in S3 */ -Method (S3GE) -{ - Store (One, \S33G) -} - -/* Set flag to disable 3G module in S3 */ -Method (S3GD) -{ - Store (Zero, \S33G) -} - -External (\_TZ.THRM) -External (\_TZ.SKIN) - -Method (TZUP) -{ - /* Update Primary Thermal Zone */ - If (CondRefOf (\_TZ.THRM, Local0)) { - Notify (\_TZ.THRM, 0x81) - } - - /* Update Secondary Thermal Zone */ - If (CondRefOf (\_TZ.SKIN, Local0)) { - Notify (\_TZ.SKIN, 0x81) - } -} - -/* Update Fan 0 thresholds */ -Method (F0UT, 2) -{ - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) - TZUP () -} - -/* Update Fan 1 thresholds */ -Method (F1UT, 2) -{ - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) - TZUP () -} - -/* Update Fan 2 thresholds */ -Method (F2UT, 2) -{ - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) - TZUP () -} - -/* Update Fan 3 thresholds */ -Method (F3UT, 2) -{ - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) - TZUP () -} - -/* Update Fan 4 thresholds */ -Method (F4UT, 2) -{ - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) - TZUP () -} - -/* Update Temperature Sensor ID */ -Method (TMPU, 1) -{ - Store (Arg0, \TMPS) - TZUP () -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/irqlinks.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/irqlinks.asl deleted file mode 100644 index acc03f0ceb..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/irqlinks.asl +++ /dev/null @@ -1,491 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl deleted file mode 100644 index 83c04d5045..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -// Intel LPC Bus Device - 0:1f.0 - -Device (LPCB) -{ - Name(_ADR, 0x001f0000) - - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) - Field (LPC0, AnyAcc, NoLock, Preserve) - { - Offset (0x40), - PMBS, 16, // PMBASE - Offset (0x60), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - Offset (0x68), - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - - Offset (0x80), // IO Decode Ranges - IOD0, 8, - IOD1, 8, - - Offset (0xb8), // GPIO Routing Control - GR00, 2, - GR01, 2, - GR02, 2, - GR03, 2, - GR04, 2, - GR05, 2, - GR06, 2, - GR07, 2, - GR08, 2, - GR09, 2, - GR10, 2, - GR11, 2, - GR12, 2, - GR13, 2, - GR14, 2, - GR15, 2, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, - } - - #include "irqlinks.asl" - - #include "acpi/ec.asl" - - Device (DMAC) // DMA Controller - { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x00, 0x00, 0x01, 0x20) - IO (Decode16, 0x81, 0x81, 0x01, 0x11) - IO (Decode16, 0x93, 0x93, 0x01, 0x0d) - IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } - }) - } - - Device (FWH) // Firmware Hub - { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Name(BUF0, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) - }) - - Method (_STA, 0) // Device Status - { - If (HPTE) { - // Note: Ancient versions of Windows don't want - // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { - Return (0xf) // Enable and show device - } Else { - Return (0xb) // Enable and don't show device - } - } - - Return (0x0) // Not enabled, don't show. - } - - Method (_CRS, 0, Serialized) // Current resources - { - If (HPTE) { - CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) - } - - If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) - } - - If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) - } - } - - Return (BUF0) - } - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(MATH) // FPU - { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO - }) - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - - #include "acpi/superio.asl" -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl deleted file mode 100644 index 50b331d61f..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Intel Cougar Point PCH support */ - -Scope(\) -{ - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - - // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) - Field(PMIO, ByteAcc, NoLock, Preserve) - { - Offset(0x20), // GPE0_STS - , 16, - GS00, 1, // GPIO00 SCI/Wake Status - GS01, 1, // GPIO01 SCI/Wake Status - GS02, 1, // GPIO02 SCI/Wake Status - GS03, 1, // GPIO03 SCI/Wake Status - GS04, 1, // GPIO04 SCI/Wake Status - GS05, 1, // GPIO05 SCI/Wake Status - GS06, 1, // GPIO06 SCI/Wake Status - GS07, 1, // GPIO07 SCI/Wake Status - GS08, 1, // GPIO08 SCI/Wake Status - GS09, 1, // GPIO09 SCI/Wake Status - GS10, 1, // GPIO10 SCI/Wake Status - GS11, 1, // GPIO11 SCI/Wake Status - GS12, 1, // GPIO12 SCI/Wake Status - GS13, 1, // GPIO13 SCI/Wake Status - GS14, 1, // GPIO14 SCI/Wake Status - GS15, 1, // GPIO15 SCI/Wake Status - Offset(0x28), // GPE0_EN - , 16, - GE00, 1, // GPIO00 SCI/Wake Enable - GE01, 1, // GPIO01 SCI/Wake Enable - GE02, 1, // GPIO02 SCI/Wake Enable - GE03, 1, // GPIO03 SCI/Wake Enable - GE04, 1, // GPIO04 SCI/Wake Enable - GE05, 1, // GPIO05 SCI/Wake Enable - GE06, 1, // GPIO06 SCI/Wake Enable - GE07, 1, // GPIO07 SCI/Wake Enable - GE08, 1, // GPIO08 SCI/Wake Enable - GE09, 1, // GPIO09 SCI/Wake Enable - GE10, 1, // GPIO10 SCI/Wake Enable - GE11, 1, // GPIO11 SCI/Wake Enable - GE12, 1, // GPIO12 SCI/Wake Enable - GE13, 1, // GPIO13 SCI/Wake Enable - GE14, 1, // GPIO14 SCI/Wake Enable - GE15, 1, // GPIO15 SCI/Wake Enable - Offset(0x42), // General Purpose Control - , 1, // skip 1 bit - GPEC, 1, // SWGPE_CTRL - } - - // GPIO IO mapped registers (0x1f.0 reg 0x48.l) - OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) - Field(GPIO, ByteAcc, NoLock, Preserve) - { - Offset(0x00), // GPIO Use Select - GU00, 8, - GU01, 8, - GU02, 8, - GU03, 8, - Offset(0x04), // GPIO IO Select - GIO0, 8, - GIO1, 8, - GIO2, 8, - GIO3, 8, - Offset(0x0c), // GPIO Level - GL00, 1, - GP01, 1, - GP02, 1, - GP03, 1, - GP04, 1, - GP05, 1, - GP06, 1, - GP07, 1, - GP08, 1, - GP09, 1, - GP10, 1, - GP11, 1, - GP12, 1, - GP13, 1, - GP14, 1, - GP15, 1, - GP16, 1, - GP17, 1, - GP18, 1, - GP19, 1, - GP20, 1, - GP21, 1, - GP22, 1, - GP23, 1, - GP24, 1, - GP25, 1, - GP26, 1, - GP27, 1, - GP28, 1, - GP29, 1, - GP30, 1, - GP31, 1, - Offset(0x18), // GPIO Blink - GB00, 8, - GB01, 8, - GB02, 8, - GB03, 8, - Offset(0x2c), // GPIO Invert - GIV0, 8, - GIV1, 8, - GIV2, 8, - GIV3, 8, - Offset(0x30), // GPIO Use Select 2 - GU04, 8, - GU05, 8, - GU06, 8, - GU07, 8, - Offset(0x34), // GPIO IO Select 2 - GIO4, 8, - GIO5, 8, - GIO6, 8, - GIO7, 8, - Offset(0x38), // GPIO Level 2 - GP32, 1, - GP33, 1, - GP34, 1, - GP35, 1, - GP36, 1, - GP37, 1, - GP38, 1, - GP39, 1, - GP40, 1, - GP41, 1, - GP42, 1, - GP43, 1, - GP44, 1, - GP45, 1, - GP46, 1, - GP47, 1, - GP48, 1, - GP49, 1, - GP50, 1, - GP51, 1, - GP52, 1, - GP53, 1, - GP54, 1, - GP55, 1, - GP56, 1, - GP57, 1, - GP58, 1, - GP59, 1, - GP60, 1, - GP61, 1, - GP62, 1, - GP63, 1, - Offset(0x40), // GPIO Use Select 3 - GU08, 8, - GU09, 4, - Offset(0x44), // GPIO IO Select 3 - GIO8, 8, - GIO9, 4, - Offset(0x48), // GPIO Level 3 - GP64, 1, - GP65, 1, - GP66, 1, - GP67, 1, - GP68, 1, - GP69, 1, - GP70, 1, - GP71, 1, - GP72, 1, - GP73, 1, - GP74, 1, - GP75, 1, - } - - - // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) - { - Offset(0x0000), // Backbone - Offset(0x1000), // Chipset - Offset(0x3000), // Legacy Configuration Registers - Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select - , 5, - HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) - , 1, // Reserved - PCID, 1, // PCI bridge disable - SA1D, 1, // SATA1 disable - SMBD, 1, // SMBUS disable - HDAD, 1, // Azalia disable - , 8, // Reserved - EH2D, 1, // EHCI #2 disable - LPBD, 1, // LPC bridge disable - EH1D, 1, // EHCI #1 disable - RP1D, 1, // Root Port 1 disable - RP2D, 1, // Root Port 2 disable - RP3D, 1, // Root Port 3 disable - RP4D, 1, // Root Port 4 disable - RP5D, 1, // Root Port 5 disable - RP6D, 1, // Root Port 6 disable - RP7D, 1, // Root Port 7 disable - RP8D, 1, // Root Port 8 disable - TTRD, 1, // Thermal sensor registers disable - SA2D, 1, // SATA2 disable - Offset(0x3428), // FD2 (Function Disable 2) - BDFD, 1, // Display BDF - ME1D, 1, // ME Interface 1 disable - ME2D, 1, // ME Interface 2 disable - IDRD, 1, // IDE redirect disable - KTCT, 1, // Keyboard Text redirect disable - } -} - -// High Definition Audio (Azalia) 0:1b.0 -#include "audio.asl" - -// PCI Express Ports 0:1c.x -#include "pcie.asl" - -// USB 0:1d.0 and 0:1a.0 -#include "usb.asl" - -// LPC Bridge 0:1f.0 -#include "lpc.asl" - -// SATA 0:1f.2, 0:1f.5 -#include "sata.asl" - -// SMBus 0:1f.3 -#include "smbus.asl" - -Method (_OSC, 4) -{ - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pcie.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pcie.asl deleted file mode 100644 index 33440c3bba..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/pcie.asl +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl deleted file mode 100644 index 276227bb50..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/sata.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/sata.asl deleted file mode 100644 index fb685a38fb..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/sata.asl +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -// Intel SATA Controller 0:1f.2 - -// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily -// pluggable - -Device (SATA) -{ - Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/sleepstates.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/sleepstates.asl deleted file mode 100644 index aabb397144..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/sleepstates.asl +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) - -/* - * S1 and S3 sleep states are not supported - * Name(\_S1, Package(){0x1,0x1,0x0,0x0}) - * Name(\_S3, Package(){0x5,0x5,0x0,0x0}) - */ - -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/smbus.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/smbus.asl deleted file mode 100644 index efd323dea5..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/smbus.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/usb.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/usb.asl deleted file mode 100644 index 9ff6d9083c..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/usb.asl +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Intel Cougar Point USB support */ - -// EHCI Controller 0:1d.0 - -Device (EHC1) -{ - Name(_ADR, 0x001d0000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - // How many are there? - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - -// EHCI #2 Controller 0:1a.0 - -Device (EHC2) -{ - Name(_ADR, 0x001a0000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - // How many are there? - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c deleted file mode 100644 index b6f728c4a8..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/azalia_device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> -#include <delay.h> -#include "pch.h" - -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - -typedef struct southbridge_intel_bd82x6x_config config_t; - -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to - * match what was just written to it - */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - -static int codec_detect(u8 *base) -{ - u8 reg8; - - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) - goto no_codec; - - /* Write back the value once reset bit is set. */ - write16(base + 0x0, - read16(base + 0x0)); - - /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg8 = read8(base + 0xe); - reg8 &= 0x0f; - if (!reg8) - goto no_codec; - - return reg8; - -no_codec: - /* Codec Not found */ - /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); - printk(BIOS_DEBUG, "Azalia: No codec!\n"); - return 0; -} - -static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) -{ - int idx=0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header - continue; - } - *verb = &cim_verb_data[idx+3]; - return verb_size; - } - - /* Not all codecs need to load another verb */ - return 0; -} - -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative - */ - -static int wait_for_ready(u8 *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; - - while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative - */ - -static int wait_for_valid(u8 *base) -{ - u32 reg32; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; - while(timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32; - const u32 *verb; - u32 verb_size; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) == -1) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); - - if (wait_for_valid(base) == -1) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return; - } - - reg32 = read32(base + 0x64); - - /* 2 */ - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) - return; - - write32(base + 0x60, verb[i]); - - if (wait_for_valid(base) == -1) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } - - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) - return; - - write32(base + 0x60, pc_beep_verbs[i]); - - if (wait_for_valid(base) == -1) - return; - } -} - -static void azalia_init(struct device *dev) -{ - u8 *base; - struct resource *res; - u32 codec_mask; - u8 reg8; - u16 reg16; - u32 reg32; - - /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); - - if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_mmio_read_config32(dev, 0x120); - reg32 &= 0xf8ffff01; - reg32 |= (1 << 24); // 25 for server - reg32 |= RCBA32(0x2030) & 0xfe; - pci_mmio_write_config32(dev, 0x120, reg32); - - reg16 = pci_mmio_read_config16(dev, 0x78); - reg16 &= ~(1 << 11); - pci_mmio_write_config16(dev, 0x78, reg16); - } else - printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - - reg32 = pci_mmio_read_config32(dev, 0x114); - reg32 &= ~0xfe; - pci_mmio_write_config32(dev, 0x114, reg32); - - // Set VCi enable bit - if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { - reg32 = pci_mmio_read_config32(dev, 0x120); - reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); - } - - // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); - - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); - - /* Additional programming steps */ - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13) | (1 << 10); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0xd0, reg32); - - /* Additional programming steps */ - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 10); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0xd0, reg32); - - /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - - pci_write_config8(dev, 0x3c, 0x0a); // unused? - - /* Codec Initialization Programming Sequence */ - reg32 = read32(base + 0x08); - reg32 |= (1 << 0); - write32(base + 0x08, reg32); - - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); - - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); - - codec_mask = codec_detect(base); - - if (codec_mask) { - printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); - } - - /* Enable dynamic clock gating */ - reg8 = pci_read_config8(dev, 0x43); - reg8 &= ~0x7; - reg8 |= (1 << 2) | (1 << 0); - pci_write_config8(dev, 0x43, reg8); -} - -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, -}; - -static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = azalia_init, - .scan_bus = 0, - .ops_pci = &azalia_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; - -static const struct pci_driver pch_azalia __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c deleted file mode 100644 index 8f6ddbc67f..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <cpu/x86/tsc.h> -#include "pch.h" - -static void store_initial_timestamp(void) -{ - /* On Cougar Point / Panther Point, there are two 32bit scratchpad registers: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - /* - * The scratchpad register at D0F0DC is used by the FSP. The system will - * not boot if the scratchpad register is not 0. Because of this we're - * only storing the low nibble of the high dword of the tsc. Even this - * is probably 0 by the time we get here, so storing 64 bits is overkill.S - */ - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); -} - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); -} - -static void enable_port80_on_lpc(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); - u32 reg32 = *gcs; - reg32 = reg32 & ~0x04; - *gcs = reg32; -} - -static void set_spi_speed(void) -{ - u32 fdod; - u8 ssfc; - - /* Observe SPI Descriptor Component Section 0 */ - RCBA32(0x38b0) = 0x1000; - - /* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = RCBA32(0x38b4); - fdod >>= 24; - fdod &= 7; - - /* Set Software Sequence frequency to match */ - ssfc = RCBA8(0x3893); - ssfc &= ~7; - ssfc |= fdod; - RCBA8(0x3893) = ssfc; -} - -static void bootblock_southbridge_init(void) -{ - store_initial_timestamp(); - - enable_spi_prefetch(); - enable_port80_on_lpc(); - set_spi_speed(); - - /* Enable upper 128bytes of CMOS */ - RCBA32(RC) = (1 << 2); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h deleted file mode 100644 index 040a35f8c7..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H -#define SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H - -struct southbridge_intel_fsp_bd82x6x_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - - /** - * GPI Routing configuration - * - * Only the lower two bits have a meaning: - * 00: No effect - * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - * 10: SCI (if corresponding GPIO_EN bit is also set) - * 11: reserved - */ - uint8_t gpi0_routing; - uint8_t gpi1_routing; - uint8_t gpi2_routing; - uint8_t gpi3_routing; - uint8_t gpi4_routing; - uint8_t gpi5_routing; - uint8_t gpi6_routing; - uint8_t gpi7_routing; - uint8_t gpi8_routing; - uint8_t gpi9_routing; - uint8_t gpi10_routing; - uint8_t gpi11_routing; - uint8_t gpi12_routing; - uint8_t gpi13_routing; - uint8_t gpi14_routing; - uint8_t gpi15_routing; - - uint32_t gpe0_en; - uint16_t alt_gp_smi_en; - - /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; - - int p_cnt_throttling_supported; - int c2_latency; -}; - -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c deleted file mode 100644 index b830027edc..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <console/console.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <elog.h> -#include "pch.h" - -#define FD_ENTRIES 32 -#define FD2_ENTRIES 5 - -const static char *fd_set_strings[FD_ENTRIES] = { - "", - "PCI Bridge (D30:F0) Disabled\n", - "SATA 1(D31:F2) Disabled\n", - "SMBus Config space Disabled\n", - "High Definition Audio Disabled\n", - "Reserved bit 5 set\n", - "Reserved bit 6 set\n", - "Reserved bit 7 set\n", - "Reserved bit 8 set\n", - "Reserved bit 9 set\n", - "Reserved bit 10 set\n", - "Reserved bit 11 set\n", - "Reserved bit 12 set\n", - "EHCI #2 Disabled\n", - "LPC Bridge Disabled\n", - "EHCI #1 Disabled\n", - "PCIe bridge 1 Disabled\n", - "PCIe bridge 2 Disabled\n", - "PCIe bridge 3 Disabled\n", - "PCIe bridge 4 Disabled\n", - "PCIe bridge 5 Disabled\n", - "PCIe bridge 6 Disabled\n", - "PCIe bridge 7 Disabled\n", - "PCIe bridge 8 Disabled\n", - "Thermal Sensor (D31:F6) Registers Disabled\n", - "SATA 2 (D31:F5) Disabled\n", - "Reserved bit 26 set\n", - "Reserved bit 27 set\n", - "Reserved bit 28 set\n", - "Reserved bit 29 set\n", - "Reserved bit 30 set\n", - "Reserved bit 31 set\n", -}; - -const static char *fd_notset_strings[FD_ENTRIES] = { - "ERROR: Required field NOT programmed\n", - "PCI Bridge (D30:F0) enabled\n", - "SATA 1(D31:F2) enabled\n", - "SMBus Config space enabled\n", - "High Definition Audio enabled\n", - "", - "", - "", - "", - "", - "", - "", - "", - "EHCI #2 Enabled\n", - "LPC Bridge Enabled\n", - "EHCI #1 Enabled\n", - "PCIe bridge 1 Enabled\n", - "PCIe bridge 2 Enabled\n", - "PCIe bridge 3 Enabled\n", - "PCIe bridge 4 Enabled\n", - "PCIe bridge 5 Enabled\n", - "PCIe bridge 6 Enabled\n", - "PCIe bridge 7 Enabled\n", - "PCIe bridge 8 Enabled\n", - "Thermal Sensor (D31:F6) Registers Enabled\n", - "SATA 2 (D31:F5) Enabled\n", - "", - "", - "", - "", - "", - "", -}; - -const static char *fd2_set_strings[FD2_ENTRIES] = { - "Display BDF Enabled\n", - "MEI #1 (D22:F0) Disabled\n", - "MEI #2 (D22:F1) Disabled\n", - "IDE-R (D22:F2) Disabled\n", - "KT (D22:F3) Disabled\n" -}; - -const static char *fd2_notset_strings[FD2_ENTRIES] = { - "Display BDF Disabled\n", - "MEI #1 (D22:F0) Enabled\n", - "MEI #2 (D22:F1) Enabled\n", - "IDE-R (D22:F2) Enabled\n", - "KT (D22:F3) Enabled\n" -}; - -void display_fd_settings(void) -{ - u32 reg32; - int i; - - reg32 = RCBA32(FD); - for (i = 0; i < FD_ENTRIES; i++) { - if (reg32 & (1 << i)) { - printk(BIOS_SPEW, "%s", fd_set_strings[i]); - } else { - printk(BIOS_SPEW, "%s", fd_notset_strings[i]); - } - } - - reg32 = RCBA32(FD2); - for (i = 0; i < FD2_ENTRIES; i++) { - if (reg32 & (1 << i)) { - printk(BIOS_SPEW, "%s", fd2_set_strings[i]); - } else { - printk(BIOS_SPEW, "%s", fd2_notset_strings[i]); - } - } -} - -static void sandybridge_setup_bars(void) -{ - /* Setting up Southbridge. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif -} - -void sandybridge_sb_early_initialization(void) -{ - /* Setup all BARs required for early PCIe and raminit */ - sandybridge_setup_bars(); -} - -void early_pch_init(void) -{ - u8 reg8; - - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/early_me.c b/src/southbridge/intel/fsp_bd82x6x/early_me.c deleted file mode 100644 index b7dbf3439f..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/early_me.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <device/pci_ids.h> -#include <halt.h> -#include <string.h> -#include "me.h" -#include "pch.h" - -static const char *me_ack_values[] = { - [ME_HFS_ACK_NO_DID] = "No DID Ack received", - [ME_HFS_ACK_RESET] = "Non-power cycle reset", - [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", - [ME_HFS_ACK_S3] = "Go to S3", - [ME_HFS_ACK_S4] = "Go to S4", - [ME_HFS_ACK_S5] = "Go to S5", - [ME_HFS_ACK_GBL_RESET] = "Global Reset", - [ME_HFS_ACK_CONTINUE] = "Continue to boot" -}; - -static inline void pci_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_ME_DEV, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -static inline void pci_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - pci_write_config32(PCH_ME_DEV, offset, dword); -} - -void intel_early_me_status(void) -{ - struct me_hfs hfs; - struct me_gmes gmes; - - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); - - intel_me_status(&hfs, &gmes); -} - -int intel_early_me_init(void) -{ - int count; - struct me_uma uma; - struct me_hfs hfs; - - printk(BIOS_INFO, "Intel ME early init\n"); - - /* Wait for ME UMA SIZE VALID bit to be set */ - for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); - if (uma.valid) - break; - udelay(ME_DELAY); - } - if (!count) { - printk(BIOS_ERR, "ERROR: ME is not ready!\n"); - return -1; - } - - /* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - if (hfs.fpt_bad) { - printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); - return -1; - } - - printk(BIOS_INFO, "Intel ME firmware is ready\n"); - return 0; -} - -int intel_early_me_uma_size(void) -{ - struct me_uma uma; - - pci_read_dword_ptr(&uma, PCI_ME_UMA); - if (uma.valid) { - printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); - return uma.size; - } - - printk(BIOS_DEBUG, "ME: Invalid UMA size\n"); - return 0; -} - -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - -int intel_early_me_init_done(u8 status) -{ - u8 reset; - int count; - u32 mebase_l, mebase_h; - struct me_hfs hfs; - struct me_did did = { - .init_done = ME_INIT_DONE, - .status = status - }; - - /* MEBASE from MESEG_BASE[35:20] */ - mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L); - mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf; - did.uma_base = (mebase_l >> 20) | (mebase_h << 12); - - /* Send message to ME */ - printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " - "UMA base: 0x%04x\n", status, did.uma_base); - - pci_write_dword_ptr(&did, PCI_ME_H_GS); - - /* Must wait for ME acknowledgement */ - for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - if (hfs.bios_msg_ack) - break; - udelay(ME_DELAY); - } - if (!count) { - printk(BIOS_ERR, "ERROR: ME failed to respond\n"); - return -1; - } - - /* Return the requested BIOS action */ - printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", - me_ack_values[hfs.ack_data]); - - /* Check status after acknowledgement */ - intel_early_me_status(); - - reset = 0; - switch (hfs.ack_data) { - case ME_HFS_ACK_CONTINUE: - /* Continue to boot */ - return 0; - case ME_HFS_ACK_RESET: - /* Non-power cycle reset */ - set_global_reset(0); - reset = 0x06; - break; - case ME_HFS_ACK_PWR_CYCLE: - /* Power cycle reset */ - set_global_reset(0); - reset = 0x0e; - break; - case ME_HFS_ACK_GBL_RESET: - /* Global reset */ - set_global_reset(1); - reset = 0x0e; - break; - case ME_HFS_ACK_S3: - case ME_HFS_ACK_S4: - case ME_HFS_ACK_S5: - break; - } - - /* Perform the requested reset */ - if (reset) { - outb(reset, 0xcf9); - halt(); - } - return -1; -} diff --git a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c deleted file mode 100644 index 930c3b437a..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <device/smbus_def.h> -#include "pch.h" - -#define FULL_RW 0x48 -#define QUICK_RW 0x44 - -static void smbus_delay(void) -{ - inb(0xeb); -} - -/** \brief block until the SMBus is no longer busy, or it times out - * - * \param smbus_base IO base address of the SMBus - */ -static int smbus_wait_until_ready(u16 smbus_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while (byte & HSTSTS_HOST_BUSY); - return loops ? 0 : -1; -} - -/** \brief block until the SMBus is no longer busy or in use, or it times out - * - * \param smbus_base IO base address of the SMBus - */ -static int smbus_wait_until_done(u16 smbus_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while ((byte & HSTSTS_HOST_BUSY) || - (byte & ~(HSTSTS_INUSE_STS | HSTSTS_HOST_BUSY)) == 0); - return loops ? 0 : -1; -} -/** \brief Sets the SMBus BAR, and configures it to run - * - */ -void enable_smbus(void) -{ - device_t dev; - - /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); -} - -/** \brief generic smbus helper function to read & write to the smbus - * - * \details Configures the SMBus for the transaction, sets up the address - * and data bytes, starts the command, waits for the command to - * finish, and returns data if the command is a read. - * - * \param device The 8-bit device address, with the read / write bit set-up. - * - * \param addr_dat For full reads/writes, this contains the address within - * the device of the byte being read/written. For quick writes, - * this contains the data to write. - * - * \param data For full writes, this contains the Data to write to the - * device. For all other transactions, this is ignored. - * - * \param command Contains the command for a full read/write (0x48) or the - * command for a quick read/write (0x44) - * - * \return Data read from the device, or -1 if there was an error - */ -static s16 smbus_rw_byte(u8 device, u8 addr_dat, u8 data, u8 command) -{ - u8 global_status_register; - - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /*** Set up transaction ***/ - - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* Set the device being talked to using supplied device address*/ - outb(device, SMBUS_IO_BASE + SMBXMITADD); - - /* Set the address and data byte */ - outb(addr_dat, SMBUS_IO_BASE + SMBHSTCMD); - outb(data, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* Start the command */ - outb(command, SMBUS_IO_BASE + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(SMBUS_IO_BASE) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(HSTSTS_SMBALERT_STS | HSTSTS_INUSE_STS); - - /* Read results - INTR gets set when a command is completed successfully */ - data = inb(SMBUS_IO_BASE + SMBHSTDAT0); - if (global_status_register != HSTSTS_INTR) - return SMBUS_ERROR; - - return data; -} - -/** \brief Sends an address and writes one byte of data - * - * \param device The 7-bit address of the device being written to - * - * \param address The address within the device to write the data to - * - * \param data The data value to write to the device - * - * \return -1 if there was an error - */ -s16 smbus_write_single_byte(u8 device, u8 address, u8 data) -{ - return (smbus_rw_byte(device << 1, address, data, FULL_RW)); -} - -/** \brief Sends an address and reads one byte of data - * - * \param device The 7-bit address of the device being written to - * - * \param address The address within the device to write the data to - * - * \return Data read from the device, or -1 if there was an error - */ -int smbus_read_byte(unsigned device, unsigned address) -{ - return (smbus_rw_byte((device << 1) | 1, address, 0, FULL_RW)); -} - -/** \brief Sends one byte of data with no address byte - * - * \param device The 7-bit address of the device being written to - * - * \param data The data value to write to the device - * - * \return -1 if there was an error - */ -s16 smbus_quick_write(u8 device, u8 data) -{ - return (smbus_rw_byte(device << 1, data, 0, QUICK_RW)); -} - -/** \brief Reads one byte of data without sending an address byte - * - * \param device The 7-bit address of the device being written to - * - * \return Data read from the device, or -1 if there was an error - */ -s16 smbus_quick_read(u8 device) -{ - return (smbus_rw_byte((device << 1) | 1, 0, 0, QUICK_RW)); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/early_spi.c b/src/southbridge/intel/fsp_bd82x6x/early_spi.c deleted file mode 100644 index 1ebe044810..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/early_spi.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <delay.h> -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/fsp_bd82x6x/early_usb.c b/src/southbridge/intel/fsp_bd82x6x/early_usb.c deleted file mode 100644 index 0533ae7477..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/early_usb.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include "pch.h" - -#define PCH_EHCI1_TEMP_BAR0 0xe8000000 -#define PCH_EHCI2_TEMP_BAR0 0xe8000400 - -/* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. - * - * The BAR will be re-assigned during device - * enumeration so these are only temporary. - */ -void enable_usb_bar(void) -{ - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; - u32 cmd; - - /* USB Controller 1 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); - - /* USB Controller 2 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI2_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/elog.c b/src/southbridge/intel/fsp_bd82x6x/elog.c deleted file mode 100644 index c93d3ec6c1..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/elog.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <stdint.h> -#include <string.h> -#include <elog.h> -#include "pch.h" - -void pch_log_state(void) -{ - u16 pm1_sts, gen_pmcon_3, tco2_sts; - u32 gpe0_sts, gpe0_en; - u8 gen_pmcon_2; - int i; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); - if (!lpc) - return; - - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); - tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); - gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); - gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); - - /* PWR_FLR Power Failure */ - if (gen_pmcon_2 & (1 << 0)) - elog_add_event(ELOG_TYPE_POWER_FAIL); - - /* SUS Well Power Failure */ - if (gen_pmcon_3 & (1 << 14)) - elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - - /* SYS_PWROK Failure */ - if (gen_pmcon_2 & (1 << 1)) - elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); - - /* PWROK Failure */ - if (gen_pmcon_2 & (1 << 0)) - elog_add_event(ELOG_TYPE_PWROK_FAIL); - - /* Second TCO Timeout */ - if (tco2_sts & (1 << 1)) - elog_add_event(ELOG_TYPE_TCO_RESET); - - /* Power Button Override */ - if (pm1_sts & (1 << 11)) - elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - - /* System Reset Status (reset button pushed) */ - if (gen_pmcon_2 & (1 << 4)) - elog_add_event(ELOG_TYPE_RESET_BUTTON); - - /* General Reset Status */ - if (gen_pmcon_3 & (1 << 9)) - elog_add_event(ELOG_TYPE_SYSTEM_RESET); - - /* ACPI Wake */ - if (pm1_sts & (1 << 15)) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - - /* - * Wake sources - */ - - /* RTC */ - if (pm1_sts & (1 << 10)) - elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - - /* PCI Express (TODO: determine wake device) */ - if (pm1_sts & (1 << 14)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - - /* PME (TODO: determine wake device) */ - if (gpe0_sts & (1 << 13)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - - /* Internal PME (TODO: determine wake device) */ - if (gpe0_sts & (1 << 13)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - - /* GPIO 0-15 */ - for (i = 0; i < 16; i++) { - if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } - - /* SMBUS Wake */ - if (gpe0_sts & (1 << 7)) - elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c deleted file mode 100644 index 99fa4c23ac..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/post_codes.h> -#include "pch.h" -#include <spi-generic.h> - -void intel_pch_finalize_smm(void) -{ - /* Set SPI opcode menu */ - RCBA16(0x3894) = SPI_OPPREFIX; - RCBA16(0x3896) = SPI_OPTYPE; - RCBA32(0x3898) = SPI_OPMENU_LOWER; - RCBA32(0x389c) = SPI_OPMENU_UPPER; - - /* Lock SPIBAR */ - RCBA32_OR(0x3804, (1 << 15)); - -#if CONFIG_SPI_FLASH_SMM - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif - - /* TCLOCKDN: TC Lockdown */ - RCBA32_OR(0x0050, (1 << 31)); - - /* BIOS Interface Lockdown */ - RCBA32_OR(0x3410, (1 << 0)); - - /* Function Disable SUS Well Lockdown */ - RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); - - /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); - - /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); - - /* R/WO registers */ - RCBA32(0x21a4) = RCBA32(0x21a4); - pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, - pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); - - /* Indicate finalize step with post code */ - outb(POST_OS_BOOT, 0x80); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/gpio.c b/src/southbridge/intel/fsp_bd82x6x/gpio.c deleted file mode 100644 index f725282ea8..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/gpio.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> - -#include "pch.h" -#include "gpio.h" - -#define MAX_GPIO_NUMBER 75 /* zero based */ -static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3}; - -void setup_pch_gpios(const struct pch_gpio_map *gpio) -{ - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); -} - -int get_gpio(int gpio_num) -{ - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - int index, bit; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; /* Just ignore wrong gpio numbers. */ - - index = gpio_num / 32; - bit = gpio_num % 32; - - return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; -} - -void set_gpio(int gpio_num) -{ - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - u32 index, bit, level; - - if (gpio_num <= MAX_GPIO_NUMBER){ - - index = gpio_num / 32; - bit = gpio_num % 32; - level = inl(gpio_base + gpio_reg_offsets[index]); - - outl((gpio_base + gpio_reg_offsets[index]), level | (1UL << bit)); - - } - - return; -} -void clear_gpio(int gpio_num) -{ - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - u32 index, bit, level; - - if (gpio_num <= MAX_GPIO_NUMBER){ - index = gpio_num / 32; - bit = gpio_num % 32; - level = inl(gpio_base + gpio_reg_offsets[index]); - - outl((gpio_base + gpio_reg_offsets[index]), level & (~(1UL << bit))); - } - - return; -} - - -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array) -{ - int gpio; - unsigned bitmask = 1; - unsigned vector = 0; - - while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { - if (get_gpio(gpio)) - vector |= bitmask; - bitmask <<= 1; - } - return vector; -} diff --git a/src/southbridge/intel/fsp_bd82x6x/gpio.h b/src/southbridge/intel/fsp_bd82x6x/gpio.h deleted file mode 100644 index c6f49d6ae9..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/gpio.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef INTEL_BD82X6X_GPIO_H -#define INTEL_BD82X6X_GPIO_H - -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -#define GPIO_MODE_NONE 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_NO_INVERT 0 -#define GPIO_INVERT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_NO_BLINK 0 -#define GPIO_BLINK 1 - -#define GPIO_RESET_PWROK 0 -#define GPIO_RESET_RSMRST 1 - -struct pch_gpio_set1 { - u32 gpio0 : 1; - u32 gpio1 : 1; - u32 gpio2 : 1; - u32 gpio3 : 1; - u32 gpio4 : 1; - u32 gpio5 : 1; - u32 gpio6 : 1; - u32 gpio7 : 1; - u32 gpio8 : 1; - u32 gpio9 : 1; - u32 gpio10 : 1; - u32 gpio11 : 1; - u32 gpio12 : 1; - u32 gpio13 : 1; - u32 gpio14 : 1; - u32 gpio15 : 1; - u32 gpio16 : 1; - u32 gpio17 : 1; - u32 gpio18 : 1; - u32 gpio19 : 1; - u32 gpio20 : 1; - u32 gpio21 : 1; - u32 gpio22 : 1; - u32 gpio23 : 1; - u32 gpio24 : 1; - u32 gpio25 : 1; - u32 gpio26 : 1; - u32 gpio27 : 1; - u32 gpio28 : 1; - u32 gpio29 : 1; - u32 gpio30 : 1; - u32 gpio31 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set2 { - u32 gpio32 : 1; - u32 gpio33 : 1; - u32 gpio34 : 1; - u32 gpio35 : 1; - u32 gpio36 : 1; - u32 gpio37 : 1; - u32 gpio38 : 1; - u32 gpio39 : 1; - u32 gpio40 : 1; - u32 gpio41 : 1; - u32 gpio42 : 1; - u32 gpio43 : 1; - u32 gpio44 : 1; - u32 gpio45 : 1; - u32 gpio46 : 1; - u32 gpio47 : 1; - u32 gpio48 : 1; - u32 gpio49 : 1; - u32 gpio50 : 1; - u32 gpio51 : 1; - u32 gpio52 : 1; - u32 gpio53 : 1; - u32 gpio54 : 1; - u32 gpio55 : 1; - u32 gpio56 : 1; - u32 gpio57 : 1; - u32 gpio58 : 1; - u32 gpio59 : 1; - u32 gpio60 : 1; - u32 gpio61 : 1; - u32 gpio62 : 1; - u32 gpio63 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set3 { - u32 gpio64 : 1; - u32 gpio65 : 1; - u32 gpio66 : 1; - u32 gpio67 : 1; - u32 gpio68 : 1; - u32 gpio69 : 1; - u32 gpio70 : 1; - u32 gpio71 : 1; - u32 gpio72 : 1; - u32 gpio73 : 1; - u32 gpio74 : 1; - u32 gpio75 : 1; - u32 fill_bitfield : 20; -} __attribute__ ((packed)); - -struct pch_gpio_map { - union { - struct { - const struct pch_gpio_set1 *mode; - const struct pch_gpio_set1 *direction; - const struct pch_gpio_set1 *level; - const struct pch_gpio_set1 *reset; - const struct pch_gpio_set1 *invert; - const struct pch_gpio_set1 *blink; - } set1; - struct { - const u32 *mode; - const u32 *direction; - const u32 *level; - const u32 *reset; - const u32 *invert; - const u32 *blink; - } set1_vals; - }; - - union { - struct { - const struct pch_gpio_set2 *mode; - const struct pch_gpio_set2 *direction; - const struct pch_gpio_set2 *level; - const struct pch_gpio_set2 *reset; - } set2; - struct { - const u32 *mode; - const u32 *direction; - const u32 *level; - const u32 *reset; - } set2_vals; - }; - - union { - struct { - const struct pch_gpio_set3 *mode; - const struct pch_gpio_set3 *direction; - const struct pch_gpio_set3 *level; - const struct pch_gpio_set3 *reset; - } set3; - struct { - const u32 *mode; - const u32 *direction; - const u32 *level; - const u32 *reset; - } set3_vals; - }; -}; - -/* Configure GPIOs with mainboard provided settings */ -void setup_pch_gpios(const struct pch_gpio_map *gpio); - -/* get GPIO and set pin values */ -int get_gpio(int gpio_num); -void set_gpio(int gpio_num); -void clear_gpio(int gpio_num); - -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array); - -#endif diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c deleted file mode 100644 index 3f4343d183..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ /dev/null @@ -1,784 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <pc80/i8259.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/acpi.h> -#include <cpu/cpu.h> -#include <elog.h> -#include <arch/acpigen.h> -#include <drivers/intel/gma/i915.h> -#include <cpu/x86/smm.h> -#include <cbmem.h> -#include <string.h> -#include "pch.h" -#include "nvs.h" - -#define NMI_OFF 0 - -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - -typedef struct southbridge_intel_fsp_bd82x6x_config config_t; - -static void pch_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - -static void pch_enable_serial_irqs(struct device *dev) -{ - /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); -#endif -} - -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -static void pch_pirq_init(device_t dev) -{ - device_t irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; - - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); - - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); - - /* Eric Biederman once said we should let the OS do this. - * I am not so sure anymore he was right. - */ - - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_gpi_routing(device_t dev) -{ - /* Get the chip configuration */ - config_t *config = dev->chip_info; - u32 reg32 = 0; - - /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; - reg32 |= (config->gpi10_routing & 0x03) << 20; - reg32 |= (config->gpi11_routing & 0x03) << 22; - reg32 |= (config->gpi12_routing & 0x03) << 24; - reg32 |= (config->gpi13_routing & 0x03) << 26; - reg32 |= (config->gpi14_routing & 0x03) << 28; - reg32 |= (config->gpi15_routing & 0x03) << 30; - - pci_write_config32(dev, GPIO_ROUT, reg32); -} - -static void pch_power_options(device_t dev) -{ - u8 reg8; - u16 reg16, pmbase; - u32 reg32; - const char *state; - /* Get the chip configuration */ - config_t *config = dev->chip_info; - - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; - - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - * - * If the option is not existent (Laptops), use Kconfig setting. - */ - get_option(&pwr_on, "power_on_after_fail"); - - reg16 = pci_read_config16(dev, GEN_PMCON_3); - reg16 &= 0xfffe; - switch (pwr_on) { - case MAINBOARD_POWER_OFF: - reg16 |= 1; - state = "off"; - break; - case MAINBOARD_POWER_ON: - reg16 &= ~1; - state = "on"; - break; - case MAINBOARD_POWER_KEEP: - reg16 &= ~1; - state = "state keep"; - break; - default: - state = "undefined"; - } - - reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ - - reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ - - pci_write_config16(dev, GEN_PMCON_3, reg16); - printk(BIOS_INFO, "Set power %s after power failure.\n", state); - - /* Set up NMI on errors. */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ - } else { - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ - } - outb(reg8, 0x70); - - /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~(3 << 0); // SMI# rate 1 minute - reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - reg16 |= (3 << 0); // Periodic SMI every 8s -#endif - pci_write_config16(dev, GEN_PMCON_1, reg16); - - // Set the board's GPI routing. - pch_gpi_routing(dev); - - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); - - /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); - - /* Clear magic status bits to prevent unexpected wake */ - reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); - RCBA32(0x3310) = reg32; -} - -static void pch_rtc_init(struct device *dev) -{ - u8 reg8; - int rtc_failed; - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG - elog_add_event(ELOG_TYPE_RTC_RESET); -#endif - } - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - - cmos_init(rtc_failed); -} - -/* CougarPoint PCH Power Management init */ -static void cpt_pm_init(struct device *dev) -{ - printk(BIOS_DEBUG, "CougarPoint PM init\n"); - pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); - RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); - RCBA32(0x2304) = 0xc0388400; - RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); - RCBA32_AND_OR(0x3314, ~0x1f, 0xf); - RCBA32(0x3318) = 0x050f0000; - RCBA32(0x3324) = 0x04000000; - RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); - RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); - RCBA32(0x3360) = 0x0001c000; - RCBA32(0x3368) = 0x00061100; - RCBA32(0x3378) = 0x7f8fdfff; - RCBA32(0x337c) = 0x000003fc; - RCBA32(0x3388) = 0x00001000; - RCBA32(0x3390) = 0x0001c000; - RCBA32(0x33a0) = 0x00000800; - RCBA32(0x33b0) = 0x00001000; - RCBA32(0x33c0) = 0x00093900; - RCBA32(0x33cc) = 0x24653002; - RCBA32(0x33d0) = 0x062108fe; - RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); - RCBA32(0x3a28) = 0x01010000; - RCBA32(0x3a2c) = 0x01010404; - RCBA32(0x3a80) = 0x01041041; - RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); - RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ - RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ - RCBA32(0x3a6c) = 0x00000001; - RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); - RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); - RCBA32(0x33c8) = 0; - RCBA32_AND_OR(0x21b0, ~0UL, 0xf); -} - -/* PantherPoint PCH Power Management init */ -static void ppt_pm_init(struct device *dev) -{ - printk(BIOS_DEBUG, "PantherPoint PM init\n"); - pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(0x2238, ~0UL, (1 << 0)); - RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); - RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); - RCBA32(0x2304) = 0xc03b8400; - RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); - RCBA32_AND_OR(0x3314, ~0x1f, 0xf); - RCBA32(0x3318) = 0x054f0000; - RCBA32(0x3324) = 0x04000000; - RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); - RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0)); - RCBA32(0x3360) = 0x0001c000; - RCBA32(0x3368) = 0x00061100; - RCBA32(0x3378) = 0x7f8fdfff; - RCBA32(0x337c) = 0x000003fd; - RCBA32(0x3388) = 0x00001000; - RCBA32(0x3390) = 0x0001c000; - RCBA32(0x33a0) = 0x00000800; - RCBA32(0x33b0) = 0x00001000; - RCBA32(0x33c0) = 0x00093900; - RCBA32(0x33cc) = 0x24653002; - RCBA32(0x33d0) = 0x067388fe; - RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); - RCBA32(0x3a28) = 0x01010000; - RCBA32(0x3a2c) = 0x01010404; - RCBA32(0x3a80) = 0x01040000; - RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); - RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ - RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ - RCBA32(0x3a6c) = 0x00000001; - RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); - RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); - RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0)); - RCBA32(0x33c8) = 0; - RCBA32_AND_OR(0x21b0, ~0UL, 0xf); -} - -static void enable_hpet(void) -{ - u32 reg32; - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; -} - -static void pch_set_acpi_mode(void) -{ - if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#else - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#endif - } -} - -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); -} - -static void pch_fixups(struct device *dev) -{ - u8 gen_pmcon_2; - - /* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); - gen_pmcon_2 |= (1 << 7); - pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); - -} - -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - -static void lpc_init(struct device *dev) -{ - printk(BIOS_DEBUG, "pch: lpc_init\n"); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - - /* IO APIC initialization. */ - pch_enable_apic(dev); - - pch_enable_serial_irqs(dev); - - /* Setup the PIRQ. */ - pch_pirq_init(dev); - - /* Setup power options. */ - pch_power_options(dev); - - /* Initialize power management */ - switch (pch_silicon_type()) { - case PCH_TYPE_CPT: /* CougarPoint */ - cpt_pm_init(dev); - break; - case PCH_TYPE_PPT: /* PantherPoint */ - ppt_pm_init(dev); - break; - default: - printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); - } - - /* Set the state of the GPIO lines. */ - //gpio_init(dev); - - /* Initialize the real time clock. */ - pch_rtc_init(dev); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); - - setup_i8259(); - - /* The OS should do this? */ - /* Interrupt 9 should be level triggered (SCI) */ - i8259_configure_irq_trigger(9, 1); - - pch_disable_smm_only_flashing(dev); - - pch_set_acpi_mode(); - - pch_fixups(dev); -} - -static void pch_lpc_read_resources(device_t dev) -{ - struct resource *res; - config_t *config = dev->chip_info; - u8 io_index = 0; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Set PCH IO decode ranges if required.*/ - if ((config->gen1_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen1_dec & 0xFFFC; - res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - if ((config->gen2_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen2_dec & 0xFFFC; - res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - if ((config->gen3_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen3_dec & 0xFFFC; - res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - if ((config->gen4_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen4_dec & 0xFFFC; - res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } -} - -static void pch_lpc_enable_resources(device_t dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - -static void pch_lpc_enable(device_t dev) -{ - pch_enable(dev); -} - -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static void southbridge_inject_dsdt(device_t dev) -{ - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); - void *opregion; - - /* Calling northbridge code as gnvs contains opregion address. */ - opregion = igd_make_opregion(); - - if (gnvs) { - const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - - memset(gnvs, 0, sizeof (*gnvs)); - - acpi_create_gnvs(gnvs); - /* IGD OpRegion Base Address */ - gnvs->aslb = (u32)opregion; - - gnvs->ndid = gfx->ndid; - memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - - /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} - -void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - config_t *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; - - fadt->model = 1; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) { - fadt->duty_width = 3; - } else { - fadt->duty_width = 0; - } - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; -} - -static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, -}; - -static struct device_operations device_ops = { - .read_resources = pch_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, - .write_acpi_tables = acpi_write_hpet, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, - .init = lpc_init, - .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, - .ops_pci = &pci_ops, -}; - - -/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and - * Intel C200 Series Chipset - */ - -static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, - 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, - 0x1c4f, 0x1c50, 0x1c52, 0x1c54, - 0x1e55, 0x1c56, 0x1e57, 0x1c5c, - 0x1e5d, 0x1e5e, 0x1e5f, 0x2310, - 0 }; - -static const struct pci_driver pch_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c deleted file mode 100644 index 8f65da3abf..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ /dev/null @@ -1,773 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* - * This is a ramstage driver for the Intel Management Engine found in the - * 6-series chipset. It handles the required boot-time messages over the - * MMIO-based Management Engine Interface to tell the ME that the BIOS is - * finished with POST. Additional messages are defined for debug but are - * not used unless the console loglevel is high enough. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <string.h> -#include <delay.h> -#include <elog.h> -#include <halt.h> - -#ifndef __SMM__ -# include <device/device.h> -# include <device/pci.h> -#endif - -#include "me.h" -#include "pch.h" - -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/gnvs.h> -#endif - -#ifndef __SMM__ -/* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { - [ME_NORMAL_BIOS_PATH] = "Normal", - [ME_S3WAKE_BIOS_PATH] = "S3 Wake", - [ME_ERROR_BIOS_PATH] = "Error", - [ME_RECOVERY_BIOS_PATH] = "Recovery", - [ME_DISABLE_BIOS_PATH] = "Disable", - [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", -}; -#endif - -/* MMIO base address for MEI interface */ -static u32 *mei_base_address; - -#if CONFIG_DEBUG_INTEL_ME -static void mei_dump(void *ptr, int dword, int offset, const char *type) -{ - struct mei_csr *csr; - - printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); - - switch (offset) { - case MEI_H_CSR: - case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } - printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); - break; - case MEI_ME_CB_RW: - case MEI_H_CB_WW: - printk(BIOS_SPEW, "CB: 0x%08x\n", dword); - break; - default: - printk(BIOS_SPEW, "0x%08x\n", offset); - break; - } -} -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif - -/* - * ME/MEI access helpers using memcpy to avoid aliasing. - */ - -static inline void mei_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = read32(mei_base_address + (offset/sizeof(u32))); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); -} - -static inline void mei_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + (offset/sizeof(u32)), dword); - mei_dump(ptr, dword, offset, "WRITE"); -} - -#ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} -#endif - -static inline void read_host_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); -} - -static inline void write_cb(u32 dword) -{ - write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); -} - -static inline u32 read_cb(void) -{ - u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); - return dword; -} - -/* Wait for ME ready bit to be asserted */ -static int mei_wait_for_me_ready(void) -{ - struct mei_csr me; - unsigned try = ME_RETRY; - - while (try--) { - read_me_csr(&me); - if (me.ready) - return 0; - udelay(ME_DELAY); - } - - printk(BIOS_ERR, "ME: failed to become ready\n"); - return -1; -} - -static void mei_reset(void) -{ - struct mei_csr host; - - if (mei_wait_for_me_ready() < 0) - return; - - /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); - host.reset = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - if (mei_wait_for_me_ready() < 0) - return; - - /* Re-init and indicate host is ready */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); -} - -static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data) -{ - struct mei_csr host; - unsigned ndata, n; - u32 *data; - - /* Number of dwords to write, ignoring MKHI */ - ndata = mei->length >> 2; - - /* Pad non-dword aligned request message length */ - if (mei->length & 3) - ndata++; - if (!ndata) { - printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); - return -1; - } - ndata++; /* Add MEI header */ - - /* - * Make sure there is still room left in the circular buffer. - * Reset the buffer pointers if the requested message will not fit. - */ - read_host_csr(&host); - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); - mei_reset(); - read_host_csr(&host); - } - - /* - * This implementation does not handle splitting large messages - * across multiple transactions. Ensure the requested length - * will fit in the available circular buffer depth. - */ - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); - return -1; - } - - /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); - ndata--; - - /* Write MKHI header */ - mei_write_dword_ptr(mkhi, MEI_H_CB_WW); - ndata--; - - /* Write message data */ - data = req_data; - for (n = 0; n < ndata; ++n) - write_cb(*data++); - - /* Generate interrupt to the ME */ - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); -} - -static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) -{ - struct mei_header mei_rsp; - struct mkhi_header mkhi_rsp; - struct mei_csr me, host; - unsigned ndata, n; - unsigned expected; - u32 *data; - - /* Total number of dwords to read from circular buffer */ - expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; - if (rsp_bytes & 3) - expected++; - - /* - * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the - * expected number of dwords are present in the circular buffer. - */ - for (n = ME_RETRY; n; --n) { - read_me_csr(&me); - if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) - break; - udelay(ME_DELAY); - } - if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); - return -1; - } - - /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); - if (!mei_rsp.is_complete) { - printk(BIOS_ERR, "ME: response is not complete\n"); - return -1; - } - - /* Handle non-dword responses and expect at least MKHI header */ - ndata = mei_rsp.length >> 2; - if (mei_rsp.length & 3) - ndata++; - if (ndata != (expected - 1)) { - printk(BIOS_ERR, "ME: response is missing data\n"); - return -1; - } - - /* Read and verify MKHI response header from the ME */ - mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || - mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); - return -1; - } - ndata--; /* MKHI header has been read */ - - /* Make sure caller passed a buffer with enough space */ - if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); - return -1; - } - - /* Read response data from the circular buffer */ - data = rsp_data; - for (n = 0; n < ndata; ++n) - *data++ = read_cb(); - - /* Tell the ME that we have consumed the response */ - read_host_csr(&host); - host.interrupt_status = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - return mei_wait_for_me_ready(); -} - -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) -{ - if (mei_send_msg(mei, mkhi, req_data) < 0) - return -1; - if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) - return -1; - return 0; -} - -#ifdef __SMM__ -/* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful\n"); - return 0; -} -#endif - -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) -/* Get ME firmware version */ -static int mkhi_get_fw_version(void) -{ - struct me_fw_version version; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_GET_FW_VERSION, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, NULL, &version, sizeof(version)) < 0) { - printk(BIOS_ERR, "ME: GET FW VERSION message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) " - "%u.%u.%u.%u (recovery)\n", - version.code_major, version.code_minor, - version.code_build_number, version.code_hot_fix, - version.recovery_major, version.recovery_minor, - version.recovery_build_number, version.recovery_hot_fix); - - return 0; -} - -static inline void print_cap(const char *name, int state) -{ - printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); -} - -/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) -{ - u32 rule_id = 0; - struct me_fwcaps cap; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - - print_cap("Full Network manageability", cap.caps_sku.full_net); - print_cap("Regular Network manageability", cap.caps_sku.std_net); - print_cap("Manageability", cap.caps_sku.manageability); - print_cap("Small business technology", cap.caps_sku.small_business); - print_cap("Level III manageability", cap.caps_sku.l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", - cap.caps_sku.intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", - cap.caps_sku.intel_mpc); - print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); - print_cap("IPV6", cap.caps_sku.ipv6); - print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); - print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); - print_cap("TLS", cap.caps_sku.tls); - print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); - - return 0; -} -#endif - -#if CONFIG_CHROMEOS && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - printk(BIOS_NOTICE, "ME: Requesting global reset\n"); - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - -#ifdef __SMM__ -static void intel_me7_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - - mei_base_address = (u32 *) - (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); - - /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, ®32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -void intel_me_finalize_smm(void) -{ - u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); - switch (did) { - case 0x1c3a8086: - intel_me7_finalize_smm(); - break; - case 0x1e3a8086: - intel_me8_finalize_smm(); - break; - default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); - } -} -#else /* !__SMM__ */ - -/* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) -{ - me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_gmes gmes; - - /* S3 wake skips all MKHI messages */ - if (acpi_is_wakeup_s3()) - return ME_S3WAKE_BIOS_PATH; - - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); - - /* Check and dump status */ - intel_me_status(&hfs, &gmes); - - /* Check Current Working State */ - switch (hfs.working_state) { - case ME_HFS_CWS_NORMAL: - path = ME_NORMAL_BIOS_PATH; - break; - case ME_HFS_CWS_REC: - path = ME_RECOVERY_BIOS_PATH; - break; - default: - path = ME_DISABLE_BIOS_PATH; - break; - } - - /* Check Current Operation Mode */ - switch (hfs.operation_mode) { - case ME_HFS_MODE_NORMAL: - break; - case ME_HFS_MODE_DEBUG: - case ME_HFS_MODE_DIS: - case ME_HFS_MODE_OVER_JMPR: - case ME_HFS_MODE_OVER_MEI: - default: - path = ME_DISABLE_BIOS_PATH; - break; - } - - /* Check for any error code and valid firmware */ - if (hfs.error_code || hfs.fpt_bad) - path = ME_ERROR_BIOS_PATH; - -#if CONFIG_ELOG - if (path != ME_NORMAL_BIOS_PATH) { - struct elog_event_data_me_extended data = { - .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = gmes.progress_code, - .current_pmevent = gmes.current_pmevent, - .current_state = gmes.current_state, - }; - elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); - } -#endif - - return path; -} - -/* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) -{ - struct resource *res; - struct mei_csr host; - u32 reg32; - - /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res || res->base == 0 || res->size == 0) { - printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); - return -1; - } - mei_base_address = res2mmio(res, 0, 0); - - /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Clean up status for next message */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); - - return 0; -} - -/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) -{ - struct me_heres status; - u32 extend[8] = {0}; - int i, count = 0; - - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); - if (!status.extend_feature_present) { - printk(BIOS_ERR, "ME: Extend Feature not present\n"); - return -1; - } - - if (!status.extend_reg_valid) { - printk(BIOS_ERR, "ME: Extend Register not valid\n"); - return -1; - } - - switch (status.extend_reg_algorithm) { - case PCI_ME_EXT_SHA1: - count = 5; - printk(BIOS_DEBUG, "ME: Extend SHA-1: "); - break; - case PCI_ME_EXT_SHA256: - count = 8; - printk(BIOS_DEBUG, "ME: Extend SHA-256: "); - break; - default: - printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); - return -1; - } - - for (i = 0; i < count; ++i) { - extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend[i]); - } - printk(BIOS_DEBUG, "\n"); - -#if CONFIG_CHROMEOS - /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif - - return 0; -} - -/* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) -{ - dev->enabled = 0; - pch_enable(dev); -} - -/* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) -{ - me_bios_path path = intel_me_path(dev); - - /* Do initial setup and determine the BIOS path */ - printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); - - switch (path) { - case ME_S3WAKE_BIOS_PATH: - intel_me_hide(dev); - break; - - case ME_NORMAL_BIOS_PATH: - /* Validate the extend register */ - if (intel_me_extend_valid(dev) < 0) - break; /* TODO: force recovery mode */ - - /* Prepare MEI MMIO interface */ - if (intel_mei_setup(dev) < 0) - break; - -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); -#endif - - /* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. - */ - break; - - case ME_ERROR_BIOS_PATH: - case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: - case ME_FIRMWARE_UPDATE_BIOS_PATH: - break; - } -} - -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, -}; - -static struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = intel_me_init, - .ops_pci = &pci_ops, -}; - -static const unsigned short pci_device_ids[] = { 0x1c3a, 0x2304, 0 }; - -static const struct pci_driver intel_me __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h deleted file mode 100644 index 967d46bb67..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/me.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _INTEL_ME_H -#define _INTEL_ME_H - -#define ME_RETRY 100000 /* 1 second */ -#define ME_DELAY 10 /* 10 us */ - -/* - * Management Engine PCI registers - */ - -#define PCI_CPU_DEVICE PCI_DEV(0,0,0) -#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ -#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ - -#define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 - -struct me_hfs { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reserved: 4; - u32 boot_options_present: 1; - u32 ack_data: 3; - u32 bios_msg_ack: 4; -} __attribute__ ((packed)); - -#define PCI_ME_UMA 0x44 - -struct me_uma { - u32 size: 6; - u32 reserved_1: 10; - u32 valid: 1; - u32 reserved_0: 14; - u32 set_to_one: 1; -} __attribute__ ((packed)); - -#define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 - -struct me_did { - u32 uma_base: 16; - u32 reserved: 8; - u32 status: 4; - u32 init_done: 4; -} __attribute__ ((packed)); - -#define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 - -struct me_gmes { - u32 bist_in_prog : 1; - u32 icc_prog_sts : 2; - u32 invoke_mebx : 1; - u32 cpu_replaced_sts : 1; - u32 mbp_rdy : 1; - u32 mfs_failure : 1; - u32 warm_rst_req_for_df : 1; - u32 cpu_replaced_valid : 1; - u32 reserved_1 : 2; - u32 fw_upd_ipu : 1; - u32 reserved_2 : 4; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; -} __attribute__ ((packed)); - -#define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 -#define PCI_ME_HER(x) (0xc0+(4*(x))) - -struct me_heres { - u32 extend_reg_algorithm: 4; - u32 reserved: 26; - u32 extend_feature_present: 1; - u32 extend_reg_valid: 1; -} __attribute__ ((packed)); - -/* - * Management Engine MEI registers - */ - -#define MEI_H_CB_WW 0x00 -#define MEI_H_CSR 0x04 -#define MEI_ME_CB_RW 0x08 -#define MEI_ME_CSR_HA 0x0c - -struct mei_csr { - u32 interrupt_enable: 1; - u32 interrupt_status: 1; - u32 interrupt_generate: 1; - u32 ready: 1; - u32 reset: 1; - u32 reserved: 3; - u32 buffer_read_ptr: 8; - u32 buffer_write_ptr: 8; - u32 buffer_depth: 8; -} __attribute__ ((packed)); - -#define MEI_ADDRESS_CORE 0x01 -#define MEI_ADDRESS_AMT 0x02 -#define MEI_ADDRESS_RESERVED 0x03 -#define MEI_ADDRESS_WDT 0x04 -#define MEI_ADDRESS_MKHI 0x07 -#define MEI_ADDRESS_ICC 0x08 -#define MEI_ADDRESS_THERMAL 0x09 - -#define MEI_HOST_ADDRESS 0 - -struct mei_header { - u32 client_address: 8; - u32 host_address: 8; - u32 length: 9; - u32 reserved: 6; - u32 is_complete: 1; -} __attribute__ ((packed)); - -#define MKHI_GROUP_ID_CBM 0x00 -#define MKHI_GROUP_ID_FWCAPS 0x03 -#define MKHI_GROUP_ID_MDES 0x08 -#define MKHI_GROUP_ID_GEN 0xff - -#define MKHI_GLOBAL_RESET 0x0b - -#define MKHI_FWCAPS_GET_RULE 0x02 - -#define MKHI_MDES_ENABLE 0x09 - -#define MKHI_GET_FW_VERSION 0x02 -#define MKHI_END_OF_POST 0x0c -#define MKHI_FEATURE_OVERRIDE 0x14 - -struct mkhi_header { - u32 group_id: 8; - u32 command: 7; - u32 is_response: 1; - u32 reserved: 8; - u32 result: 8; -} __attribute__ ((packed)); - -struct me_fw_version { - u16 code_minor; - u16 code_major; - u16 code_build_number; - u16 code_hot_fix; - u16 recovery_minor; - u16 recovery_major; - u16 recovery_build_number; - u16 recovery_hot_fix; -} __attribute__ ((packed)); - - -#define HECI_EOP_STATUS_SUCCESS 0x0 -#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 - -#define CBM_RR_GLOBAL_RESET 0x01 - -#define GLOBAL_RESET_BIOS_MRC 0x01 -#define GLOBAL_RESET_BIOS_POST 0x02 -#define GLOBAL_RESET_MEBX 0x03 - -struct me_global_reset { - u8 request_origin; - u8 reset_type; -} __attribute__ ((packed)); - -typedef enum { - ME_NORMAL_BIOS_PATH, - ME_S3WAKE_BIOS_PATH, - ME_ERROR_BIOS_PATH, - ME_RECOVERY_BIOS_PATH, - ME_DISABLE_BIOS_PATH, - ME_FIRMWARE_UPDATE_BIOS_PATH, -} me_bios_path; - -/* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); - -#ifdef __PRE_RAM__ -void intel_early_me_status(void); -int intel_early_me_init(void); -int intel_early_me_uma_size(void); -int intel_early_me_init_done(u8 status); -#endif - -#ifdef __SMM__ -void intel_me_finalize_smm(void); -void intel_me8_finalize_smm(void); -#endif -typedef struct { - u32 major_version : 16; - u32 minor_version : 16; - u32 hotfix_version : 16; - u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; - -typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; - -typedef struct { - u32 full_net : 1; - u32 std_net : 1; - u32 manageability : 1; - u32 small_business : 1; - u32 l3manageability : 1; - u32 intel_at : 1; - u32 intel_cls : 1; - u32 reserved : 3; - u32 intel_mpc : 1; - u32 icc_over_clocking : 1; - u32 pavp : 1; - u32 reserved_1 : 4; - u32 ipv6 : 1; - u32 kvm : 1; - u32 och : 1; - u32 vlan : 1; - u32 tls : 1; - u32 reserved_4 : 1; - u32 wlan : 1; - u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; - -typedef struct { - u16 lock_state : 1; - u16 authenticate_module : 1; - u16 s3authentication : 1; - u16 flash_wear_out : 1; - u16 flash_variable_security : 1; - u16 wwan3gpresent : 1; - u16 wwan3goob : 1; - u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; - -typedef struct { - u8 state; - u8 last_theft_trigger; - tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; - -typedef struct { - u32 platform_target_usage_type : 4; - u32 platform_target_market_type : 2; - u32 super_sku : 1; - u32 reserved : 1; - u32 intel_me_fw_image_type : 4; - u32 platform_brand : 4; - u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; - -typedef struct { - mefwcaps_sku fw_capabilities; - u8 available; -} mbp_fw_caps; - -typedef struct { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; - -typedef struct { - u32 key[8]; -} mbp_platform_key; - -typedef struct { - platform_type_rule_data rule_data; - u8 available; -} mbp_plat_type; - -typedef struct { - mbp_fw_version_name fw_version_name; - mbp_fw_caps fw_caps_sku; - mbp_rom_bist_data rom_bist_data; - mbp_platform_key platform_key; - mbp_plat_type fw_plat_type; - mbp_icc_profile icc_profile; - tdt_state_info at_state; - u32 mfsintegrity; -} me_bios_payload; - -typedef struct { - u32 mbp_size : 8; - u32 num_entries : 8; - u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; - -typedef struct { - u32 app_id : 8; - u32 item_id : 8; - u32 length : 8; - u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; - -struct me_fwcaps { - u32 id; - u8 length; - mefwcaps_sku caps_sku; - u8 reserved[3]; -} __attribute__ ((packed)); - -#endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c deleted file mode 100644 index 292dbba96b..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ /dev/null @@ -1,928 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* - * This is a ramstage driver for the Intel Management Engine found in the - * 6-series chipset. It handles the required boot-time messages over the - * MMIO-based Management Engine Interface to tell the ME that the BIOS is - * finished with POST. Additional messages are defined for debug but are - * not used unless the console loglevel is high enough. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <string.h> -#include <delay.h> -#include <elog.h> -#include <halt.h> - -#ifndef __SMM__ -# include <device/device.h> -# include <device/pci.h> -#endif - -#include "me.h" -#include "pch.h" - -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif - -#ifndef __SMM__ -/* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { - [ME_NORMAL_BIOS_PATH] = "Normal", - [ME_S3WAKE_BIOS_PATH] = "S3 Wake", - [ME_ERROR_BIOS_PATH] = "Error", - [ME_RECOVERY_BIOS_PATH] = "Recovery", - [ME_DISABLE_BIOS_PATH] = "Disable", - [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", -}; -static int intel_me_read_mbp(me_bios_payload *mbp_data); -#endif - -/* MMIO base address for MEI interface */ -static u32 *mei_base_address; - -#if CONFIG_DEBUG_INTEL_ME -static void mei_dump(void *ptr, int dword, int offset, const char *type) -{ - struct mei_csr *csr; - - printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); - - switch (offset) { - case MEI_H_CSR: - case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } - printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); - break; - case MEI_ME_CB_RW: - case MEI_H_CB_WW: - printk(BIOS_SPEW, "CB: 0x%08x\n", dword); - break; - default: - printk(BIOS_SPEW, "0x%08x\n", offset); - break; - } -} -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif - -/* - * ME/MEI access helpers using memcpy to avoid aliasing. - */ - -static inline void mei_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = read32(mei_base_address + (offset/sizeof(u32))); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); -} - -static inline void mei_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + (offset/sizeof(u32)), dword); - mei_dump(ptr, dword, offset, "WRITE"); -} - -#ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} -#endif - -static inline void read_host_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); -} - -static inline void write_cb(u32 dword) -{ - write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); -} - -static inline u32 read_cb(void) -{ - u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); - return dword; -} - -/* Wait for ME ready bit to be asserted */ -static int mei_wait_for_me_ready(void) -{ - struct mei_csr me; - unsigned try = ME_RETRY; - - while (try--) { - read_me_csr(&me); - if (me.ready) - return 0; - udelay(ME_DELAY); - } - - printk(BIOS_ERR, "ME: failed to become ready\n"); - return -1; -} - -static void mei_reset(void) -{ - struct mei_csr host; - - if (mei_wait_for_me_ready() < 0) - return; - - /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); - host.reset = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - if (mei_wait_for_me_ready() < 0) - return; - - /* Re-init and indicate host is ready */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); -} - -static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data) -{ - struct mei_csr host; - unsigned ndata, n; - u32 *data; - - /* Number of dwords to write, ignoring MKHI */ - ndata = mei->length >> 2; - - /* Pad non-dword aligned request message length */ - if (mei->length & 3) - ndata++; - if (!ndata) { - printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); - return -1; - } - ndata++; /* Add MEI header */ - - /* - * Make sure there is still room left in the circular buffer. - * Reset the buffer pointers if the requested message will not fit. - */ - read_host_csr(&host); - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); - mei_reset(); - read_host_csr(&host); - } - - /* - * This implementation does not handle splitting large messages - * across multiple transactions. Ensure the requested length - * will fit in the available circular buffer depth. - */ - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); - return -1; - } - - /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); - ndata--; - - /* Write MKHI header */ - mei_write_dword_ptr(mkhi, MEI_H_CB_WW); - ndata--; - - /* Write message data */ - data = req_data; - for (n = 0; n < ndata; ++n) - write_cb(*data++); - - /* Generate interrupt to the ME */ - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); -} - -static int mei_recv_msg(struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) -{ - struct mei_header mei_rsp; - struct mkhi_header mkhi_rsp; - struct mei_csr me, host; - unsigned ndata, n/*, me_data_len*/; - unsigned expected; - u32 *data; - - /* Total number of dwords to read from circular buffer */ - expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; - if (rsp_bytes & 3) - expected++; - - /* - * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the - * expected number of dwords are present in the circular buffer. - */ - for (n = ME_RETRY; n; --n) { - read_me_csr(&me); - if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) - break; - udelay(ME_DELAY); - } - if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); - return -1; - } - - /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); - if (!mei_rsp.is_complete) { - printk(BIOS_ERR, "ME: response is not complete\n"); - return -1; - } - - /* Handle non-dword responses and expect at least MKHI header */ - ndata = mei_rsp.length >> 2; - if (mei_rsp.length & 3) - ndata++; - if (ndata != (expected - 1)) { - printk(BIOS_ERR, "ME: response is missing data %d != %d\n", - ndata, (expected - 1)); - return -1; - } - - /* Read and verify MKHI response header from the ME */ - mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || - mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); - return -1; - } - ndata--; /* MKHI header has been read */ - - /* Make sure caller passed a buffer with enough space */ - if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); - return -1; - } - - /* Read response data from the circular buffer */ - data = rsp_data; - for (n = 0; n < ndata; ++n) - *data++ = read_cb(); - - /* Tell the ME that we have consumed the response */ - read_host_csr(&host); - host.interrupt_status = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - return mei_wait_for_me_ready(); -} - -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) -{ - if (mei_send_msg(mei, mkhi, req_data) < 0) - return -1; - if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) - return -1; - return 0; -} - -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) -static inline void print_cap(const char *name, int state) -{ - printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); -} - -static void me_print_fw_version(mbp_fw_version_name *vers_name) -{ - if (!vers_name->major_version) { - printk(BIOS_ERR, "ME: mbp missing version report\n"); - return; - } - - printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", - vers_name->major_version, vers_name->minor_version, - vers_name->hotfix_version, vers_name->build_version); -} - -/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mefwcaps_sku *cap) -{ - u32 rule_id = 0; - struct me_fwcaps cap_msg; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) - < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - *cap = cap_msg.caps_sku; - return 0; -} - -/* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_fw_caps *caps_section) -{ - mefwcaps_sku *cap = &caps_section->fw_capabilities; - if (!caps_section->available) { - printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); - if (mkhi_get_fwcaps(cap)) - return; - } - - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("Small business technology", cap->small_business); - print_cap("Level III manageability", cap->l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); -} -#endif - -#if CONFIG_CHROMEOS && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -static int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - -#ifdef __SMM__ - -/* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - u32 eop_ack; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); - if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - -void intel_me8_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - - mei_base_address = (u32 *) - (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); - - /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, ®32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -#else /* !__SMM__ */ - -/* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) -{ - me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_gmes gmes; - - /* S3 wake skips all MKHI messages */ - if (acpi_is_wakeup_s3()) - return ME_S3WAKE_BIOS_PATH; - - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); - - /* Check and dump status */ - intel_me_status(&hfs, &gmes); - - /* Check Current Working State */ - switch (hfs.working_state) { - case ME_HFS_CWS_NORMAL: - path = ME_NORMAL_BIOS_PATH; - break; - case ME_HFS_CWS_REC: - path = ME_RECOVERY_BIOS_PATH; - break; - default: - path = ME_DISABLE_BIOS_PATH; - break; - } - - /* Check Current Operation Mode */ - switch (hfs.operation_mode) { - case ME_HFS_MODE_NORMAL: - break; - case ME_HFS_MODE_DEBUG: - case ME_HFS_MODE_DIS: - case ME_HFS_MODE_OVER_JMPR: - case ME_HFS_MODE_OVER_MEI: - default: - path = ME_DISABLE_BIOS_PATH; - break; - } - - /* Check for any error code and valid firmware and MBP */ - if (hfs.error_code || hfs.fpt_bad) - path = ME_ERROR_BIOS_PATH; - - /* Check if the MBP is ready */ - if (!gmes.mbp_rdy) { - printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); - path = ME_ERROR_BIOS_PATH; - } - -#if CONFIG_ELOG - if (path != ME_NORMAL_BIOS_PATH) { - struct elog_event_data_me_extended data = { - .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = gmes.progress_code, - .current_pmevent = gmes.current_pmevent, - .current_state = gmes.current_state, - }; - elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); - } -#endif - - return path; -} - -/* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) -{ - struct resource *res; - struct mei_csr host; - u32 reg32; - - /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res || res->base == 0 || res->size == 0) { - printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); - return -1; - } - mei_base_address = (u32 *)(uintptr_t)res->base; - - /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Clean up status for next message */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); - - return 0; -} - -/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) -{ - struct me_heres status; - u32 extend[8] = {0}; - int i, count = 0; - - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); - if (!status.extend_feature_present) { - printk(BIOS_ERR, "ME: Extend Feature not present\n"); - return -1; - } - - if (!status.extend_reg_valid) { - printk(BIOS_ERR, "ME: Extend Register not valid\n"); - return -1; - } - - switch (status.extend_reg_algorithm) { - case PCI_ME_EXT_SHA1: - count = 5; - printk(BIOS_DEBUG, "ME: Extend SHA-1: "); - break; - case PCI_ME_EXT_SHA256: - count = 8; - printk(BIOS_DEBUG, "ME: Extend SHA-256: "); - break; - default: - printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); - return -1; - } - - for (i = 0; i < count; ++i) { - extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend[i]); - } - printk(BIOS_DEBUG, "\n"); - -#if CONFIG_CHROMEOS - /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif - - return 0; -} - -/* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) -{ - dev->enabled = 0; - pch_enable(dev); -} - -/* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) -{ - me_bios_path path = intel_me_path(dev); - me_bios_payload mbp_data; - - /* Do initial setup and determine the BIOS path */ - printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); - - switch (path) { - case ME_S3WAKE_BIOS_PATH: - intel_me_hide(dev); - break; - - case ME_NORMAL_BIOS_PATH: - /* Validate the extend register */ - if (intel_me_extend_valid(dev) < 0) - break; /* TODO: force recovery mode */ - - /* Prepare MEI MMIO interface */ - if (intel_mei_setup(dev) < 0) - break; - - if(intel_me_read_mbp(&mbp_data)) - break; - -#if CONFIG_CHROMEOS && 0 /* DISABLED */ - /* - * Unlock ME in recovery mode. - */ - if (recovery_mode_enabled()) { - /* Unlock ME flash region */ - mkhi_hmrfpo_enable(); - - /* Issue global reset */ - mkhi_global_reset(); - return; - } -#endif - -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); -#endif - - /* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. - */ - break; - - case ME_ERROR_BIOS_PATH: - case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: - case ME_FIRMWARE_UPDATE_BIOS_PATH: - break; - } -} - -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, -}; - -static struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = intel_me_init, - .ops_pci = &pci_ops, -}; - -static const struct pci_driver intel_me __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e3a, -}; - -/****************************************************************************** - * */ -static u32 me_to_host_words_pending(void) -{ - struct mei_csr me; - read_me_csr(&me); - if (!me.ready) - return 0; - return (me.buffer_write_ptr - me.buffer_read_ptr) & - (me.buffer_depth - 1); -} - -#if 0 -/* This function is not yet being used, keep it in for the future. */ -static u32 host_to_me_words_room(void) -{ - struct mei_csr csr; - - read_me_csr(&csr); - if (!csr.ready) - return 0; - - read_host_csr(&csr); - return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & - (csr.buffer_depth - 1); -} -#endif -/* - * mbp seems to be following its own flow, let's retrieve it in a dedicated - * function. - */ -static int intel_me_read_mbp(me_bios_payload *mbp_data) -{ - mbp_header mbp_hdr; - mbp_item_header mbp_item_hdr; - u32 me2host_pending; - u32 mbp_item_id; - struct mei_csr host; - - me2host_pending = me_to_host_words_pending(); - if (!me2host_pending) { - printk(BIOS_ERR, "ME: no mbp data!\n"); - return -1; - } - - /* we know for sure that at least the header is there */ - mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); - - if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || - (me2host_pending < mbp_hdr.mbp_size)) { - printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" - " buffer contains %d words\n", - mbp_hdr.num_entries, mbp_hdr.mbp_size, - me2host_pending); - return -1; - } - - me2host_pending--; - memset(mbp_data, 0, sizeof(*mbp_data)); - - while (mbp_hdr.num_entries--) { - u32* copy_addr; - u32 copy_size, buffer_room; - void *p; - - if (!me2host_pending) { - printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", - mbp_hdr.num_entries + 1); - return -1; - } - - mei_read_dword_ptr(&mbp_item_hdr, MEI_ME_CB_RW); - - if (mbp_item_hdr.length > me2host_pending) { - printk(BIOS_ERR, "ME: insufficient mbp data %d " - "entries to go!\n", - mbp_hdr.num_entries + 1); - return -1; - } - - me2host_pending -= mbp_item_hdr.length; - - mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) + - mbp_item_hdr.app_id; - - copy_size = mbp_item_hdr.length - 1; - -#define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ - buffer_room = sizeof(mbp_data->field) / sizeof(u32); \ - break; \ - } - - p = &mbp_item_hdr; - printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); - - switch(mbp_item_id) { - case 0x101: - SET_UP_COPY(fw_version_name); - - case 0x102: - SET_UP_COPY(icc_profile); - - case 0x103: - SET_UP_COPY(at_state); - - case 0x201: - mbp_data->fw_caps_sku.available = 1; - SET_UP_COPY(fw_caps_sku.fw_capabilities); - - case 0x301: - SET_UP_COPY(rom_bist_data); - - case 0x401: - SET_UP_COPY(platform_key); - - case 0x501: - mbp_data->fw_plat_type.available = 1; - SET_UP_COPY(fw_plat_type.rule_data); - - case 0x601: - SET_UP_COPY(mfsintegrity); - - default: - printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n", - mbp_item_id); - return -1; - } - - if (buffer_room != copy_size) { - printk(BIOS_ERR, "ME: buffer room %d != %d copy size" - " for item 0x%x!!!\n", - buffer_room, copy_size, mbp_item_id); - return -1; - } - while(copy_size--) - *copy_addr++ = read_cb(); - } - - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - { - int cntr = 0; - while(host.interrupt_generate) { - read_host_csr(&host); - cntr++; - } - printk(BIOS_SPEW, "ME: mbp read OK after %d cycles\n", cntr); - } - - return 0; -} - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me_status.c b/src/southbridge/intel/fsp_bd82x6x/me_status.c deleted file mode 100644 index 37fcf57677..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/me_status.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdlib.h> -#include <console/console.h> -#include "me.h" - -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) -/* HFS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { - [ME_HFS_CWS_RESET] = "Reset", - [ME_HFS_CWS_INIT] = "Initializing", - [ME_HFS_CWS_REC] = "Recovery", - [ME_HFS_CWS_NORMAL] = "Normal", - [ME_HFS_CWS_WAIT] = "Platform Disable Wait", - [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" -}; - -/* HFS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { - [ME_HFS_STATE_PREBOOT] = "Preboot", - [ME_HFS_STATE_M0_UMA] = "M0 with UMA", - [ME_HFS_STATE_M3] = "M3 without UMA", - [ME_HFS_STATE_M0] = "M0 without UMA", - [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" -}; - -/* HFS[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { - [ME_HFS_MODE_NORMAL] = "Normal", - [ME_HFS_MODE_DEBUG] = "Debug", - [ME_HFS_MODE_DIS] = "Soft Temporary Disable", - [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" -}; - -/* HFS[15:12] Error Code Values */ -static const char *me_error_values[] = { - [ME_HFS_ERROR_NONE] = "No Error", - [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", - [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" -}; - -/* GMES[31:28] ME Progress Code */ -static const char *me_progress_values[] = { - [ME_GMES_PHASE_ROM] = "ROM Phase", - [ME_GMES_PHASE_BUP] = "BUP Phase", - [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", - [ME_GMES_PHASE_POLICY] = "Policy Module", - [ME_GMES_PHASE_MODULE] = "Module Loading", - [ME_GMES_PHASE_UNKNOWN] = "Unknown", - [ME_GMES_PHASE_HOST] = "Host Communication" -}; - -/* GMES[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { - [0x00] = "Clean Moff->Mx wake", - [0x01] = "Moff->Mx wake after an error", - [0x02] = "Clean global reset", - [0x03] = "Global reset after an error", - [0x04] = "Clean Intel ME reset", - [0x05] = "Intel ME reset due to exception", - [0x06] = "Pseudo-global reset", - [0x07] = "S0/M0->Sx/M3", - [0x08] = "Sx/M3->S0/M0", - [0x09] = "Non-power cycle reset", - [0x0a] = "Power cycle reset through M3", - [0x0b] = "Power cycle reset through Moff", - [0x0c] = "Sx/Mx->Sx/Moff" -}; - -/* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { - [0x00] = "BEGIN", - [0x06] = "DISABLE" -}; - -/* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { - [0x00] = "Initialization starts", - [0x01] = "Disable the host wake event", - [0x04] = "Flow determination start process", - [0x08] = "Error reading/matching the VSCC table in the descriptor", - [0x0a] = "Check to see if straps say ME DISABLED", - [0x0b] = "Timeout waiting for PWROK", - [0x0d] = "Possibly handle BUP manufacturing override strap", - [0x11] = "Bringup in M3", - [0x12] = "Bringup in M0", - [0x13] = "Flow detection error", - [0x15] = "M3 clock switching error", - [0x18] = "M3 kernel load", - [0x1c] = "T34 missing - cannot program ICC", - [0x1f] = "Waiting for DID BIOS message", - [0x20] = "Waiting for DID BIOS message failure", - [0x21] = "DID reported an error", - [0x22] = "Enabling UMA", - [0x23] = "Enabling UMA error", - [0x24] = "Sending DID Ack to BIOS", - [0x25] = "Sending DID Ack to BIOS error", - [0x26] = "Switching clocks in M0", - [0x27] = "Switching clocks in M0 error", - [0x28] = "ME in temp disable", - [0x32] = "M0 kernel load", -}; - -/* Progress Code 3 states */ -static const char *me_progress_policy_values[] = { - [0x00] = "Entery into Policy Module", - [0x03] = "Received S3 entry", - [0x04] = "Received S4 entry", - [0x05] = "Received S5 entry", - [0x06] = "Received UPD entry", - [0x07] = "Received PCR entry", - [0x08] = "Received NPCR entry", - [0x09] = "Received host wake", - [0x0a] = "Received AC<>DC switch", - [0x0b] = "Received DRAM Init Done", - [0x0c] = "VSCC Data not found for flash device", - [0x0d] = "VSCC Table is not valid", - [0x0e] = "Flash Partition Boundary is outside address space", - [0x0f] = "ME cannot access the chipset descriptor region", - [0x10] = "Required VSCC values for flash parts do not match", -}; -#endif - -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) -{ -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[gmes->progress_code]); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[gmes->current_pmevent]); - - printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (gmes->progress_code) { - case ME_GMES_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[gmes->current_state]); - break; - - case ME_GMES_PHASE_BUP: /* Bringup Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[gmes->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_bup_values[gmes->current_state]); - else - printk(BIOS_DEBUG, "0x%02x", gmes->current_state); - break; - - case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[gmes->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_policy_values[gmes->current_state]); - else - printk(BIOS_DEBUG, "0x%02x", gmes->current_state); - break; - - case ME_GMES_PHASE_HOST: /* Host Communication Phase */ - if (!gmes->current_state) - printk(BIOS_DEBUG, "Host communication established"); - else - printk(BIOS_DEBUG, "0x%02x", gmes->current_state); - break; - - default: - printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); - } - printk(BIOS_DEBUG, "\n"); -#endif -} diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h deleted file mode 100644 index 7eb487a0af..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include "vendorcode/google/chromeos/gnvs.h" -typedef struct { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - /* Thermal policy */ - u8 tlvl; /* 0x11 - Throttle Level Limit */ - u8 flvl; /* 0x12 - Current FAN Level */ - u8 tcrt; /* 0x13 - Critical Threshold */ - u8 tpsv; /* 0x14 - Passive Threshold */ - u8 tmax; /* 0x15 - CPU Tj_max */ - u8 f0of; /* 0x16 - FAN 0 OFF Threshold */ - u8 f0on; /* 0x17 - FAN 0 ON Threshold */ - u8 f0pw; /* 0x18 - FAN 0 PWM value */ - u8 f1of; /* 0x19 - FAN 1 OFF Threshold */ - u8 f1on; /* 0x1a - FAN 1 ON Threshold */ - u8 f1pw; /* 0x1b - FAN 1 PWM value */ - u8 f2of; /* 0x1c - FAN 2 OFF Threshold */ - u8 f2on; /* 0x1d - FAN 2 ON Threshold */ - u8 f2pw; /* 0x1e - FAN 2 PWM value */ - u8 f3of; /* 0x1f - FAN 3 OFF Threshold */ - u8 f3on; /* 0x20 - FAN 3 ON Threshold */ - u8 f3pw; /* 0x21 - FAN 3 PWM value */ - u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ - u8 f4on; /* 0x23 - FAN 4 ON Threshold */ - u8 f4pw; /* 0x24 - FAN 4 PWM value */ - u8 tmps; /* 0x25 - Temperature Sensor ID */ - u8 rsvd3[2]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ - u8 rsvd4[4]; - /* Super I/O & CMOS config */ - u8 natp; /* 0x32 - SIO type */ - u8 s5u0; /* 0x33 - Enable USB0 in S5 */ - u8 s5u1; /* 0x34 - Enable USB1 in S5 */ - u8 s3u0; /* 0x35 - Enable USB0 in S3 */ - u8 s3u1; /* 0x36 - Enable USB1 in S3 */ - u8 s33g; /* 0x37 - Enable S3 in 3G */ - u32 obsolete_cmem; /* 0x38 - CBMEM TOC */ - /* Integrated Graphics Device */ - u8 igds; /* 0x3c - IGD state */ - u8 tlst; /* 0x3d - Display Toggle List Pointer */ - u8 cadl; /* 0x3e - currently attached devices */ - u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; - /* Backlight Control */ - u8 blcs; /* 0x64 - Backlight Control possible */ - u8 brtl; - u8 odds; - u8 rsvd6[0x7]; - /* Ambient Light Sensors*/ - u8 alse; /* 0x6e - ALS enable */ - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd7[0x6]; - /* Extended Mobile Access */ - u8 emae; /* 0x78 - EMA enable */ - u16 emap; /* 0x79 - EMA pointer */ - u16 emal; /* 0x7a - EMA Length */ - u8 rsvd8[0x5]; - /* MEF */ - u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; - /* TPM support */ - u8 tpmp; /* 0x8c - TPM */ - u8 tpme; - u8 rsvd10[8]; - /* SATA */ - u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ - u8 gtf1[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ - - /* ChromeOS specific (starts at 0x100)*/ - chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; - -#ifdef __SMM__ -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); -#endif -void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.c b/src/southbridge/intel/fsp_bd82x6x/pch.c deleted file mode 100644 index c14d12919c..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/pch.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include "pch.h" - -static int pch_revision_id = -1; -static int pch_type = -1; - -int pch_silicon_revision(void) -{ - if (pch_revision_id < 0) - pch_revision_id = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PCI_REVISION_ID); - return pch_revision_id; -} - -int pch_silicon_type(void) -{ - if (pch_type < 0) - pch_type = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PCI_DEVICE_ID + 1); - return pch_type; -} - -int pch_silicon_supported(int type, int rev) -{ - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -/* Set bit in Function Disble register to hide this device */ -static void pch_hide_devfn(unsigned devfn) -{ - switch (devfn) { - case PCI_DEVFN(22, 0): /* MEI #1 */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); - break; - case PCI_DEVFN(22, 1): /* MEI #2 */ - RCBA32_OR(FD2, PCH_DISABLE_MEI2); - break; - case PCI_DEVFN(22, 2): /* IDE-R */ - RCBA32_OR(FD2, PCH_DISABLE_IDER); - break; - case PCI_DEVFN(22, 3): /* KT */ - RCBA32_OR(FD2, PCH_DISABLE_KT); - break; - case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ - RCBA32_OR(BUC, PCH_DISABLE_GBE); - break; - case PCI_DEVFN(26, 0): /* EHCI #2 */ - RCBA32_OR(FD, PCH_DISABLE_EHCI2); - break; - case PCI_DEVFN(27, 0): /* HD Audio Controller */ - RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); - break; - case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ - case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ - case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ - case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ - case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ - case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ - case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ - case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ - RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); - break; - case PCI_DEVFN(29, 0): /* EHCI #1 */ - RCBA32_OR(FD, PCH_DISABLE_EHCI1); - break; - case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ - RCBA32_OR(FD, PCH_DISABLE_P2P); - break; - case PCI_DEVFN(31, 0): /* LPC */ - RCBA32_OR(FD, PCH_DISABLE_LPC); - break; - case PCI_DEVFN(31, 2): /* SATA #1 */ - RCBA32_OR(FD, PCH_DISABLE_SATA1); - break; - case PCI_DEVFN(31, 3): /* SMBUS */ - RCBA32_OR(FD, PCH_DISABLE_SMBUS); - break; - case PCI_DEVFN(31, 5): /* SATA #22 */ - RCBA32_OR(FD, PCH_DISABLE_SATA2); - break; - case PCI_DEVFN(31, 6): /* Thermal Subsystem */ - RCBA32_OR(FD, PCH_DISABLE_THERMAL); - break; - } -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned try = IOBP_RETRY; - u32 data; - - while (try--) { - data = RCBA32(IOBPS); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_READ_AX; - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = RCBA32(IOBPD); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((RCBA32(IOBPS) & 0x6) != 0) { - printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_WRITE_AX; - if (!iobp_poll()) - return; - - /* Write IOBP data */ - RCBA32(IOBPD) = data; - if (!iobp_poll()) - return; -} - -/* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) -{ - device_t port; - int port_func; - int dev_func = PCI_FUNC(dev->path.pci.devfn); - - printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); - - /* Go through static device tree list of devices - * because enumeration is still in progress */ - for (port = all_devices; port; port = port->next) { - /* Only care about PCIe root ports */ - if (PCI_SLOT(port->path.pci.devfn) != - PCI_SLOT(dev->path.pci.devfn)) - continue; - - /* Check if port is in range and enabled */ - port_func = PCI_FUNC(port->path.pci.devfn); - if (port_func >= dev_func && - port_func < (dev_func + 4) && - port->enabled) - return 1; - } - - /* None of the ports in this set are enabled */ - return 0; -} - -/* RPFN is a write-once register so keep a copy until it is written */ -static u32 new_rpfn; - -/* Swap function numbers assigned to two PCIe Root Ports */ -static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) -{ - u32 old_rpfn = new_rpfn; - - printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); - - new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); - - /* Old function set to new function and disabled */ - new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); - new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); -} - -/* Update devicetree with new Root Port function number assignment */ -static void pch_pcie_devicetree_update(void) -{ - device_t dev; - - /* Update the function numbers in the static devicetree */ - for (dev = all_devices; dev; dev = dev->next) { - u8 new_devfn; - - /* Only care about PCH PCIe root ports */ - if (PCI_SLOT(dev->path.pci.devfn) != - PCH_PCIE_DEV_SLOT) - continue; - - /* Determine the new devfn for this port */ - new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, - PCI_FUNC(dev->path.pci.devfn))); - - if (dev->path.pci.devfn != new_devfn) { - printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), - PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); - - dev->path.pci.devfn = new_devfn; - } - } -} - -/* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) -{ - struct southbridge_intel_fsp_bd82x6x_config *config = dev->chip_info; - u32 reg32; - - /* - * Save a copy of the Root Port Function Number map when - * starting to walk the list of PCIe Root Ports so it can - * be updated locally and written out when the last port - * has been processed. - */ - if (PCI_FUNC(dev->path.pci.devfn) == 0) { - new_rpfn = RCBA32(RPFN); - - /* - * Enable Root Port coalescing if the first port is disabled - * or the other devices will not be enumerated by the OS. - */ - if (!dev->enabled) - config->pcie_port_coalesce = 1; - - if (config->pcie_port_coalesce) - printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); - } - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* - * PCIE Power Savings for PantherPoint and CougarPoint/B1+ - * - * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 - * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 - * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not - * called unless the device is enabled. - */ - if ((PCI_FUNC(dev->path.pci.devfn) == 0 || - PCI_FUNC(dev->path.pci.devfn) == 4)) { - /* Handle workaround for PPT and CPT/B1+ */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && - !pch_pcie_check_set_enabled(dev)) { - u8 reg8 = pci_read_config8(dev, 0xe2); - reg8 |= 1; - pci_write_config8(dev, 0xe2, reg8); - } - - /* - * Enable Clock Gating for shared PCIe resources - * before disabling this particular port. - */ - pci_write_config8(dev, 0xe1, 0x3c); - } - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Do not claim downstream transactions for PCIe ports */ - new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); - - /* Hide this device if possible */ - pch_hide_devfn(dev->path.pci.devfn); - } else { - int fn; - - /* - * Check if there is a lower disabled port to swap with this - * port in order to maintain linear order starting at zero. - */ - if (config->pcie_port_coalesce) { - for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { - if (!(new_rpfn & RPFN_HIDE(fn))) - continue; - - /* Swap places with this function */ - pch_pcie_function_swap( - PCI_FUNC(dev->path.pci.devfn), fn); - break; - } - } - - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } - - /* - * When processing the last PCIe root port we can now - * update the Root Port Function Number and Hide register. - */ - if (PCI_FUNC(dev->path.pci.devfn) == 7) { - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); - RCBA32(RPFN) = new_rpfn; - - /* Update static devictree with new function numbers */ - if (config->pcie_port_coalesce) - pch_pcie_devicetree_update(); - } -} - -void pch_enable(device_t dev) -{ - u32 reg32; - - /* PCH PCIe Root Ports get special handling */ - if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) - return pch_pcie_enable(dev); - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Hide this device if possible */ - pch_hide_devfn(dev->path.pci.devfn); - } else { - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } -} - -struct chip_operations southbridge_intel_fsp_bd82x6x_ops = { - CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") - .enable_dev = pch_enable, -}; diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h deleted file mode 100644 index 9e3b4da1e9..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H -#define SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H - -/* PCH types */ -#define PCH_TYPE_CPT 0x1c /* CougarPoint */ -#define PCH_TYPE_PPT 0x1e /* IvyBridge */ - -/* PCH stepping values for LPC device */ -#define PCH_STEP_A0 0 -#define PCH_STEP_A1 1 -#define PCH_STEP_B0 2 -#define PCH_STEP_B1 3 -#define PCH_STEP_B2 4 -#define PCH_STEP_B3 5 - -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ -#define SMBUS_IO_BASE 0x0500 -#define SMBUS_SLAVE_ADDR 0x24 -/* TODO Make sure these don't get changed by stage2 */ -#define DEFAULT_GPIOBASE 0x0480 -#define DEFAULT_PMBASE 0x0400 - -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#ifndef __ACPI__ -#define DEBUG_PERIODIC_SMIS 0 - -#if defined (__SMM__) && !defined(__ASSEMBLER__) -void intel_pch_finalize_smm(void); -#endif - -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include "chip.h" -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_enable(device_t dev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG -void pch_log_state(void); -#endif -#else -/* writes an address and one byte of data */ -s16 smbus_write_single_byte(u8 device, u8 address, u8 data); - -/* Sends an address and reads one byte of data */ -int smbus_read_byte(unsigned device, unsigned address); - -/* writes a single byte of data to smbus without an address byte */ -s16 smbus_quick_write(u8 device, u8 data); - -/* gets one byte of data from smbus without writing an address. */ -s16 smbus_quick_read(u8 device); - -void enable_smbus(void); -void enable_usb_bar(void); -int early_spi_read(u32 offset, u32 size, u8 *buffer); -void sandybridge_sb_early_initialization(void); -void early_pch_init(void); -void display_fd_settings(void); -#endif -#endif - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_KEEP 2 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -/* PCI Configuration Space (D30:F0): PCI2PCI */ -#define PSTS 0x06 -#define SMLT 0x1b -#define SECSTS 0x1e -#define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) - -#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) -#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) -#define PCH_ME_DEV PCI_DEV(0, 0x16, 0) -#define PCH_PCIE_DEV_SLOT 28 - -/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) -#define SERIRQ_CNTL 0x64 - -#define GEN_PMCON_1 0xa0 -#define GEN_PMCON_2 0xa2 -#define GEN_PMCON_3 0xa4 -#define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) - -/* GEN_PMCON_3 bits */ -#define RTC_BATTERY_DEAD (1 << 2) -#define RTC_POWER_FAILED (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - -#define PMBASE 0x40 -#define ACPI_CNTL 0x44 -#define BIOS_CNTL 0xDC -#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ -#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ -#define GPIO_ROUT 0xb8 - -#define PIRQA_ROUT 0x60 -#define PIRQB_ROUT 0x61 -#define PIRQC_ROUT 0x62 -#define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B - -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ - -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) -#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) -#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) -#define INTR_LN 0x3c -#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) -#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ - -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - -#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ -#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ -#define SATA_SP 0xd0 /* Scratchpad */ - -/* SATA IOBP Registers */ -#define SATA_IOBP_SP0G3IR 0xea000151 -#define SATA_IOBP_SP1G3IR 0xea000051 - -/* PCI Configuration Space (D31:F3): SMBus */ -#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define SMB_RCV_SLVA 0x09 - -/* HOSTC bits */ -#define I2C_EN (1 << 2) -#define SMB_SMI_EN (1 << 1) -#define HST_EN (1 << 0) - -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define HSTSTS_HOST_BUSY (1 << 0) -#define HSTSTS_INTR (1 << 1) -#define HSTSTS_DEV_ERR (1 << 2) -#define HSTSTS_BUS_ERR (1 << 3) -#define HSTSTS_FAILED (1 << 4) -#define HSTSTS_SMBALERT_STS (1 << 5) -#define HSTSTS_INUSE_STS (1 << 6) -#define HSTSTS_BYTE_DONE_STS (1 << 7) - -#define SMBUS_TIMEOUT (10 * 1000 * 100) - - -/* Southbridge IO BARs */ - -#define GPIOBASE 0x48 - -#define PMBASE 0x40 - -/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ -#define RPFN 0x0404 /* 32bit */ - -/* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) -/* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) -/* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) -/* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) - -#define TRSR 0x1e00 /* 8bit */ -#define TRCR 0x1e10 /* 64bit */ -#define TWDR 0x1e18 /* 64bit */ - -#define IOTR0 0x1e80 /* 64bit */ -#define IOTR1 0x1e88 /* 64bit */ -#define IOTR2 0x1e90 /* 64bit */ -#define IOTR3 0x1e98 /* 64bit */ - -#define TCTL 0x3000 /* 8bit */ - -#define NOINT 0 -#define INTA 1 -#define INTB 2 -#define INTC 3 -#define INTD 4 - -#define DIR_IDR 12 /* Interrupt D Pin Offset */ -#define DIR_ICR 8 /* Interrupt C Pin Offset */ -#define DIR_IBR 4 /* Interrupt B Pin Offset */ -#define DIR_IAR 0 /* Interrupt A Pin Offset */ - -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -/* IO Buffer Programming */ -#define IOBPIRI 0x2330 -#define IOBPD 0x2334 -#define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) - -#define D31IP 0x3100 /* 32bit */ -#define D31IP_TTIP 24 /* Thermal Throttle Pin */ -#define D31IP_SIP2 20 /* SATA Pin 2 */ -#define D31IP_SMIP 12 /* SMBUS Pin */ -#define D31IP_SIP 8 /* SATA Pin */ -#define D30IP 0x3104 /* 32bit */ -#define D30IP_PIP 0 /* PCI Bridge Pin */ -#define D29IP 0x3108 /* 32bit */ -#define D29IP_E1P 0 /* EHCI #1 Pin */ -#define D28IP 0x310c /* 32bit */ -#define D28IP_P8IP 28 /* PCI Express Port 8 */ -#define D28IP_P7IP 24 /* PCI Express Port 7 */ -#define D28IP_P6IP 20 /* PCI Express Port 6 */ -#define D28IP_P5IP 16 /* PCI Express Port 5 */ -#define D28IP_P4IP 12 /* PCI Express Port 4 */ -#define D28IP_P3IP 8 /* PCI Express Port 3 */ -#define D28IP_P2IP 4 /* PCI Express Port 2 */ -#define D28IP_P1IP 0 /* PCI Express Port 1 */ -#define D27IP 0x3110 /* 32bit */ -#define D27IP_ZIP 0 /* HD Audio Pin */ -#define D26IP 0x3114 /* 32bit */ -#define D26IP_E2P 0 /* EHCI #2 Pin */ -#define D25IP 0x3118 /* 32bit */ -#define D25IP_LIP 0 /* GbE LAN Pin */ -#define D22IP 0x3124 /* 32bit */ -#define D22IP_KTIP 12 /* KT Pin */ -#define D22IP_IDERIP 8 /* IDE-R Pin */ -#define D22IP_MEI2IP 4 /* MEI #2 Pin */ -#define D22IP_MEI1IP 0 /* MEI #1 Pin */ -#define D20IP 0x3128 /* 32bit */ -#define D20IP_XHCIIP 0 -#define D31IR 0x3140 /* 16bit */ -#define D30IR 0x3142 /* 16bit */ -#define D29IR 0x3144 /* 16bit */ -#define D28IR 0x3146 /* 16bit */ -#define D27IR 0x3148 /* 16bit */ -#define D26IR 0x314c /* 16bit */ -#define D25IR 0x3150 /* 16bit */ -#define D22IR 0x315c /* 16bit */ -#define D20IR 0x3160 /* 16bit */ -#define OIC 0x31fe /* 16bit */ -#define SOFT_RESET_CTRL 0x38f4 -#define SOFT_RESET_DATA 0x38f8 - -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) - -#define RC 0x3400 /* 32bit */ -#define HPTC 0x3404 /* 32bit */ -#define GCS 0x3410 /* 32bit */ -#define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) -#define FD 0x3418 /* 32bit */ -#define DISPBDF 0x3424 /* 16bit */ -#define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ - -/* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS (1 << 0) -#define PCH_DISABLE_P2P (1 << 1) -#define PCH_DISABLE_SATA1 (1 << 2) -#define PCH_DISABLE_SMBUS (1 << 3) -#define PCH_DISABLE_HD_AUDIO (1 << 4) -#define PCH_DISABLE_EHCI2 (1 << 13) -#define PCH_DISABLE_LPC (1 << 14) -#define PCH_DISABLE_EHCI1 (1 << 15) -#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) -#define PCH_DISABLE_THERMAL (1 << 24) -#define PCH_DISABLE_SATA2 (1 << 25) - -/* Function Disable 2 RCBA 0x3428 */ -#define PCH_DISABLE_KT (1 << 4) -#define PCH_DISABLE_IDER (1 << 3) -#define PCH_DISABLE_MEI2 (1 << 2) -#define PCH_DISABLE_MEI1 (1 << 1) -#define PCH_ENABLE_DBDF (1 << 0) - -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - -/* ICH7 PMBASE */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define PROC_CNT 0x10 -#define LV2 0x14 -#define LV3 0x15 -#define LV4 0x16 -#define PM2_CNT 0x50 // mobile only -#define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GP_SMI_EN 0x38 -#define ALT_GP_SMI_STS 0x3a -#define GPE_CNTL 0x42 -#define DEVACT_STS 0x44 -#define SS_CNT 0x50 -#define C3_RES 0x54 -#define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 - -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - -#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x3808 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ - -#endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c deleted file mode 100644 index 886c4a5b7e..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/reset.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <reset.h> - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c deleted file mode 100644 index fba5953538..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "pch.h" - -typedef struct southbridge_intel_fsp_bd82x6x_config config_t; - -static void sata_init(struct device *dev) -{ - u32 reg32; - u16 reg16; - /* Get the chip configuration */ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "SATA: Initializing...\n"); - - if (config == NULL) { - printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); - return; - } - - /* SATA configuration is handled by the FSP */ - - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); - - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { - u32 *abar; - - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); - - /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* Enable AHCI Mode */ - reg32 = read32(abar + 0x01); - reg32 |= (1 << 31); - write32(abar + 0x01, reg32); - } else { - printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0xff); - } - -} - -static void sata_enable(device_t dev) -{ -} - -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .enable = sata_enable, - .scan_bus = 0, - .ops_pci = &sata_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, - 0x1e00, 0x1e01, 0x1e02, 0x1e03, 0x2323, - 0 }; - -static const struct pci_driver pch_sata __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c deleted file mode 100644 index 2b4d4ec8fd..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <string.h> -#include <cpu/intel/smm/gen1/smi.h> -#include "pch.h" - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_DEBUG, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i>= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear ALT_GP_SMI_STS - * @return ALT_GP_SMI_STS register - */ -static u16 reset_alt_gp_smi_status(void) -{ - u16 reg16; - - reg16 = inl(pmbase + ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg16, pmbase + ALT_GP_SMI_STS); - - return reg16; -} - -static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) -{ - int i; - printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i>= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i); - } - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -void southbridge_smm_init(void) -{ - u32 smi_en; - u16 pm1_en; - u32 gpe0_en; - -#if CONFIG_ELOG - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - printk(BIOS_DEBUG, "Initializing southbridge SMI..."); - - pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Disable GPE0 PME_B0 */ - gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~PME_B0_EN; - outl(gpe0_en, pmbase + GPE0_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif - smi_en |= TCO_EN; - smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif - smi_en |= SLP_SMI_EN; -#if 0 - smi_en |= BIOS_EN; -#endif - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); -} - -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c deleted file mode 100644 index 96de4570df..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ /dev/null @@ -1,760 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/cache.h> -#include <device/pci_def.h> -#include <cpu/x86/smm.h> -#include <elog.h> -#include <halt.h> -#include <pc80/mc146818rtc.h> -#include "pch.h" - -#include "nvs.h" - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include <northbridge/intel/fsp_sandybridge/northbridge.h> - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; -u16 smm_get_pmbase(void) -{ - return pmbase; -} - -static u8 smm_initialized = 0; - -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ -static global_nvs_t *gnvs; -global_nvs_t *smm_get_gnvs(void) -{ - return gnvs; -} - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_SPEW, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); - printk(BIOS_SPEW, "\n"); - int reg16 = inw(pmbase + PM1_EN); - printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i >= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); - if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - -int southbridge_io_trap_handler(int smif) -{ - switch (smif) { - case 0x32: - printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - */ - gnvs->smif = 0; - return 1; /* IO trap handled */ - } - - /* Not handled */ - return 0; -} - -/** - * @brief Set the EOS bit - */ -void southbridge_smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -static void busmaster_disable_on_bus(int bus) -{ - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } -} - -/* - * Drive GPIO 60 low to gate memory reset in S3. - * - * Intel reference designs all use GPIO 60 but it is - * not a requirement and boards could use a different pin. - */ -static void southbridge_gate_memory_reset(void) -{ - u32 reg32; - u16 gpiobase; - - gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; - if (!gpiobase) - return; - - /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); - } - - /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); - } - - /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); -} - -static void southbridge_smi_sleep(void) -{ - u8 reg8; - u32 reg32; - u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - - // save and recover RTC port values - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); - get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); - - /* First, disable further SMIs */ - reg8 = inb(pmbase + SMI_EN); - reg8 &= ~SLP_SMI_EN; - outb(reg8, pmbase + SMI_EN); - - /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = (reg32 >> 10) & 7; - - /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ-2); - -#if CONFIG_ELOG_GSMI - /* Log S3, S4, and S5 entry */ - if (slp_typ >= 5) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); -#endif - - /* Next, do the deed. - */ - - switch (slp_typ) { - case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case 5: - printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - /* Gate memory reset */ - southbridge_gate_memory_reset(); - - /* Invalidate the cache before going to S3 */ - wbinvd(); - break; - case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case 7: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - - outl(0, pmbase + GPE0_EN); - - /* Always set the flag in case CMOS was changed on runtime. For - * "KEEP", switch to "OFF" - KEEP is software emulated - */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* also iterates over all bridges on bus 0 */ - busmaster_disable_on_bus(0); - break; - default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; - } - - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. - */ - outl(reg32 | SLP_EN, pmbase + PM1_CNT); - - /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ > 1) - halt(); - - /* In most sleep states, the code flow of this function ends at - * the line above. However, if we entered sleep state S1 and wake - * up again, we will continue to execute code in this function. - */ - reg32 = inl(pmbase + PM1_CNT); - if (reg32 & SCI_EN) { - /* The OS is not an ACPI OS, so we set the state to S0 */ - reg32 &= ~(SLP_EN | SLP_TYP); - outl(reg32, pmbase + PM1_CNT); - } -} - -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -#if CONFIG_ELOG_GSMI -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} -#endif - -static void southbridge_smi_apmc(void) -{ - u32 pmctrl; - u8 reg8; - em64t101_smm_state_save_area_t *state; - - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; -#if CONFIG_ELOG_GSMI - case ELOG_GSMI_APM_CNT: - southbridge_smi_gsmi(); - break; -#endif - } - - mainboard_smi_apmc(reg8); -} - -static void southbridge_smi_pm1(void) -{ - u16 pm1_sts; - - pm1_sts = reset_pm1_status(); - dump_pm1_status(pm1_sts); - - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ - if (pm1_sts & PWRBTN_STS) { - // power button pressed - u32 reg32; - reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif - outl(reg32, pmbase + PM1_CNT); - } -} - -static void southbridge_smi_gpe0(void) -{ - u32 gpe0_sts; - - gpe0_sts = reset_gpe0_status(); - dump_gpe0_status(gpe0_sts); -} - -static void southbridge_smi_gpi(void) -{ - u16 reg16; - reg16 = inw(pmbase + ALT_GP_SMI_STS); - outw(reg16, pmbase + ALT_GP_SMI_STS); - - reg16 &= inw(pmbase + ALT_GP_SMI_EN); - - mainboard_smi_gpi(reg16); - - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - - outw(reg16, pmbase + ALT_GP_SMI_STS); -} - -static void southbridge_smi_mc(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & MCSMI_EN) == 0) - return; - - printk(BIOS_DEBUG, "Microcontroller SMI.\n"); -} - - - -static void southbridge_smi_tco(void) -{ - u32 tco_sts; - - tco_sts = reset_tco_status(); - - /* Any TCO event? */ - if (!tco_sts) - return; - - if (tco_sts & (1 << 8)) { // BIOSWR - u8 bios_cntl; - - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); - - if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - */ - - /* This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); - } /* No else for now? */ - } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ - /* Handle TCO timeout */ - printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else if (!tco_sts) { - dump_tco_status(tco_sts); - } -} - -static void southbridge_smi_periodic(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -static void southbridge_smi_monitor(void) -{ -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP -} - -typedef void (*smi_handler_t)(void); - -static smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - southbridge_smi_gpi, // [10] GPI_STS - southbridge_smi_mc, // [11] MCSMI_STS - NULL, // [12] DEVMON_STS - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - southbridge_smi_monitor, // [21] MONITOR_STS - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] EL_SMI_STS - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] reserved - NULL, // [29] reserved - NULL, // [30] reserved - NULL // [31] reserved -}; - -/** - * @brief Interrupt handler for SMI# - * - * @param node - * @param state_save - */ - -void southbridge_smi_handler(void) -{ - int i, dump = 0; - u32 smi_sts; - - /* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = reset_smi_status(); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 31; i++) { - if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) { - southbridge_smi[i](); - } else { - printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " - "handler available.\n", i); - dump = 1; - } - } - } - - if(dump) { - dump_smi_status(smi_sts); - } - -} diff --git a/src/southbridge/intel/fsp_bd82x6x/southbridge_pci_devs.h b/src/southbridge/intel/fsp_bd82x6x/southbridge_pci_devs.h deleted file mode 100644 index 7e52655866..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/southbridge_pci_devs.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _INTEL_FSP_BD82X6X_PCI_DEVS_H_ -#define _INTEL_FSP_BD82X6X_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* XHCI */ -#define XHCI_DEV 0x14 -#define XHCI_FUNC 0 -# define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) - -/* Management Engine Interface */ -#define MEI_DEV 0x16 -#define MEI1_FUNC 0x0 -# define MEI1_DEVFN PCI_DEVFN(MEI_DEV, MEI1_FUNC) - -#define MEI2_FUNC 0x1 -# define MEI2_DEVFN PCI_DEVFN(MEI_DEV, MEI2_FUNC) - -/* MEI - IDE Redirection */ -#define IDE_DEV 0x16 -#define IDE_FUNC 2 -# define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) - -/* MEI - Keyboard / Text Redirection */ -#define KT_DEV 0x16 -#define KT_FUNC 0x3 -#define KT_DEVFN PCI_DEVFN(KT_DEV, KT_FUNC) - -/* Gigabit Ethernet */ -#define GBE_DEV 0x19 -#define GBE_FUNC 0x0 -#define GBE_DEVFN PCI_DEVFN(GBE_DEV, GBE_FUNC) - -/* EHCI */ -#define EHCI1_DEV 0x1D -#define EHCI1_FUNC 0 -# define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) - -#define EHCI2_DEV 0x1A -#define EHCI2_FUNC 0 -# define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x1B -#define HDA_FUNC 0 -# define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) - -/* PCIe Ports */ -#define SB_PCIE_DEV 0x1C -#define SB_PCIE_PORT1_FUNC 0 -# define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) - -#define SB_PCIE_PORT2_FUNC 1 -# define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) - -#define SB_PCIE_PORT3_FUNC 2 -# define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) - -#define SB_PCIE_PORT4_FUNC 3 -# define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) - -#define SB_PCIE_PORT5_FUNC 4 -# define SB_PCIE_PORT5_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT5_FUNC) - -#define SB_PCIE_PORT6_FUNC 5 -# define SB_PCIE_PORT6_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT6_FUNC) - -#define SB_PCIE_PORT7_FUNC 6 -# define SB_PCIE_PORT7_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT7_FUNC) - -#define SB_PCIE_PORT8_FUNC 7 -# define SB_PCIE_PORT8_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT8_FUNC) - -/* PCI Bridge */ -#define SB_PCI_DEV 0x1E -#define SB_PCI_PORT_FUNC 0 -# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) - -/* Platform Controller Hub */ -#define PCH_DEV 0x1F - -/* LPC */ -#define LPC_DEV PCH_DEV -#define LPC_FUNC 0 -# define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) - -/* SMBUS */ -#define SMBUS_DEV PCH_DEV -#define SMBUS_FUNC 3 -# define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) - -/* SATA */ -#define SATA_DEV PCH_DEV -#define SATA1_FUNC 2 -# define SATA1_DEVFN PCI_DEVFN(SATA_DEV, SATA1_FUNC) - -#define SATA2_FUNC 5 -# define SATA2_DEVFN PCI_DEVFN(SATA_DEV, SATA2_FUNC) - -/* Thermal Sensor */ -#define TS_DEV PCH_DEV -#define TS_FUNC 6 -# define TS_DEVFN PCI_DEVFN(TS_DEV, TS_FUNC) - -#endif /* _INTEL_FSP_BD82X6X_PCI_DEVS_H_ */ diff --git a/src/southbridge/intel/fsp_bd82x6x/watchdog.c b/src/southbridge/intel/fsp_bd82x6x/watchdog.c deleted file mode 100644 index 91bc615003..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/watchdog.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <watchdog.h> - - // - // Disable PCH Watchdog timer at SB_RCBA+0x3410 - // - // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; - // -void watchdog_off(void) -{ - device_t dev; - unsigned long value, base; - - /* Turn off the ICH7 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "PCH watchdog disabled\n"); -} diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 754c48716c..580089f397 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -19,7 +19,6 @@ config FSP_VENDORCODE_HEADER_PATH string - default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX |