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-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c2
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/Kconfig5
2 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 7f14b1eb8d..939990997c 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -97,7 +97,7 @@ static void post_cache_as_ram(void)
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else
- //memset((void*)CONFIG_RAMBASE, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE - 0xa0000));
+ memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
#endif
print_debug("Done\r\n");
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
index 5700581496..f74e40c577 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -64,11 +64,6 @@ config MAX_PHYSICAL_CPUS
default 8
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
-config LOGICAL_CPUS
- bool
- default n
- depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n