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-rw-r--r--src/mainboard/google/zork/Kconfig9
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c70
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c68
3 files changed, 135 insertions, 12 deletions
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig
index a226cd82ee..17c5d5147c 100644
--- a/src/mainboard/google/zork/Kconfig
+++ b/src/mainboard/google/zork/Kconfig
@@ -137,4 +137,13 @@ config VARIANT_BOARD_VER_FW_CONFIG_VALID
help
Which board version did FW_CONFIG become valid in CBI.
+config VARIANT_MIN_BOARD_ID_V3_SCHEMATICS
+ int
+ default 4 if BOARD_GOOGLE_TREMBYLE
+ default 3 if BOARD_GOOGLE_EZKINIL
+ default 3 if BOARD_GOOGLE_MORPHIUS
+ default 2 if BOARD_GOOGLE_BERKNIP
+ default 3 if BOARD_GOOGLE_DALBOZ
+ default 2 if BOARD_GOOGLE_VILBOZ
+
endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index 46c232129a..c2bac09081 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -7,7 +7,7 @@
#include <boardid.h>
#include <variant/gpio.h>
-static const struct soc_amd_gpio gpio_set_stage_rom[] = {
+static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW),
/* EC_FCH_WAKE_L */
@@ -44,7 +44,49 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
PAD_GPO(GPIO_142, HIGH),
};
-static const struct soc_amd_gpio gpio_set_wifi[] = {
+static const struct soc_amd_gpio gpio_set_wifi_pre_v3[] = {
+ /* EN_PWR_WIFI */
+ PAD_GPO(GPIO_29, HIGH),
+};
+
+static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
+ /* PEN_POWER_EN - reset */
+ PAD_GPO(GPIO_5, LOW),
+ /* EC_FCH_WAKE_L */
+ PAD_GPI(GPIO_24, PULL_UP),
+ PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
+ /* PCIE_RST0_L - Fixed timings */
+ /* TODO: Make sure this gets locked at end of post */
+ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
+ /* PCIE_RST1_L - Variable timings (May remove) */
+ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
+ /* NVME_AUX_RESET_L */
+ PAD_GPO(GPIO_40, HIGH),
+ /* WIFI_AUX_RESET_L */
+ PAD_GPO(GPIO_42, HIGH),
+ /* EN_PWR_TOUCHPAD_PS2 - reset */
+ PAD_GPO(GPIO_67, LOW),
+ /* EMMC_RESET - reset (default stuffing unused)*/
+ PAD_GPO(GPIO_68, HIGH),
+ /* EN_PWR_CAMERA - reset */
+ PAD_GPO(GPIO_76, LOW),
+ /* CLK_REQ0_L - WIFI */
+ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
+ /* CLK_REQ1_L - SD Card */
+ PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
+ /* CLK_REQ2_L - NVMe */
+ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
+ /* BIOS_FLASH_WP_ODL */
+ PAD_GPI(GPIO_137, PULL_NONE),
+ /* USI_RESET - reset */
+ PAD_GPO(GPIO_140, HIGH),
+ /* USB_HUB_RST_L - reset*/
+ PAD_GPO(GPIO_141, LOW),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_142, HIGH),
+};
+
+static const struct soc_amd_gpio gpio_set_wifi_v3[] = {
/* EN_PWR_WIFI */
PAD_GPO(GPIO_29, HIGH),
};
@@ -164,15 +206,31 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{
- *size = ARRAY_SIZE(gpio_set_stage_rom);
- return gpio_set_stage_rom;
+ uint32_t board_version;
+
+ if (!google_chromeec_cbi_get_board_version(&board_version) &&
+ (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) {
+ *size = ARRAY_SIZE(gpio_set_stage_rom_v3);
+ return gpio_set_stage_rom_v3;
+ }
+
+ *size = ARRAY_SIZE(gpio_set_stage_rom_pre_v3);
+ return gpio_set_stage_rom_pre_v3;
}
const __weak
struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size)
{
- *size = ARRAY_SIZE(gpio_set_wifi);
- return gpio_set_wifi;
+ uint32_t board_version;
+
+ if (!google_chromeec_cbi_get_board_version(&board_version) &&
+ (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) {
+ *size = ARRAY_SIZE(gpio_set_wifi_v3);
+ return gpio_set_wifi_v3;
+ }
+
+ *size = ARRAY_SIZE(gpio_set_wifi_pre_v3);
+ return gpio_set_wifi_pre_v3;
}
const __weak
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index b32312f291..2c87a0f21f 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -7,7 +7,7 @@
#include <boardid.h>
#include <variant/gpio.h>
-static const struct soc_amd_gpio gpio_set_stage_rom[] = {
+static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW),
/* EC_FCH_WAKE_L */
@@ -42,7 +42,47 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
PAD_GPO(GPIO_142, HIGH),
};
-static const struct soc_amd_gpio gpio_set_wifi[] = {
+static const struct soc_amd_gpio gpio_set_wifi_pre_v3[] = {
+ /* EN_PWR_WIFI */
+ PAD_GPO(GPIO_29, HIGH),
+};
+
+static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
+ /* PEN_POWER_EN - reset */
+ PAD_GPO(GPIO_5, LOW),
+ /* EC_FCH_WAKE_L */
+ PAD_GPI(GPIO_24, PULL_UP),
+ PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
+ /* PCIE_RST0_L - Fixed timings */
+ /* TODO: Make sure this gets locked at end of post */
+ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
+ /* PCIE_RST1_L - Variable timings (May remove) */
+ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
+ /* NVME_AUX_RESET_L */
+ PAD_GPO(GPIO_40, HIGH),
+ /* WIFI_AUX_RESET_L */
+ PAD_GPO(GPIO_42, HIGH),
+ /* EN_PWR_TOUCHPAD_PS2 - reset */
+ PAD_GPO(GPIO_67, LOW),
+ /* EMMC_RESET - reset (default stuffing unused)*/
+ PAD_GPO(GPIO_68, HIGH),
+ /* EN_PWR_CAMERA - reset */
+ PAD_GPO(GPIO_76, LOW),
+ /* CLK_REQ0_L - WIFI */
+ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
+ /* CLK_REQ1_L - SD Card */
+ PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
+ /* CLK_REQ4_L - SSD */
+ PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
+ /* BIOS_FLASH_WP_ODL */
+ PAD_GPI(GPIO_137, PULL_NONE),
+ /* USI_RESET - reset */
+ PAD_GPO(GPIO_140, HIGH),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_142, HIGH),
+};
+
+static const struct soc_amd_gpio gpio_set_wifi_v3[] = {
/* EN_PWR_WIFI */
PAD_GPO(GPIO_29, HIGH),
};
@@ -163,15 +203,31 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{
- *size = ARRAY_SIZE(gpio_set_stage_rom);
- return gpio_set_stage_rom;
+ uint32_t board_version;
+
+ if (!google_chromeec_cbi_get_board_version(&board_version) &&
+ (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) {
+ *size = ARRAY_SIZE(gpio_set_stage_rom_v3);
+ return gpio_set_stage_rom_v3;
+ }
+
+ *size = ARRAY_SIZE(gpio_set_stage_rom_pre_v3);
+ return gpio_set_stage_rom_pre_v3;
}
const __weak
struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size)
{
- *size = ARRAY_SIZE(gpio_set_wifi);
- return gpio_set_wifi;
+ uint32_t board_version;
+
+ if (!google_chromeec_cbi_get_board_version(&board_version) &&
+ (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) {
+ *size = ARRAY_SIZE(gpio_set_wifi_v3);
+ return gpio_set_wifi_v3;
+ }
+
+ *size = ARRAY_SIZE(gpio_set_wifi_pre_v3);
+ return gpio_set_wifi_pre_v3;
}
const __weak
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 06:18:07 +0000