diff options
Diffstat (limited to 'src')
111 files changed, 745 insertions, 412 deletions
diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 89194ad0be..30d11313cb 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -393,7 +393,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -407,19 +407,16 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); - if (!res) { + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_2); + if (!res) dev_err(dev->pdev, "BAR2 resource not found.\n"); - ret = -EIO; - goto out_free; - } /* * If we don't have IO space at all, use MMIO now and * assume the chip has MMIO enabled by default (rev 0x20 * and higher). */ - if (!(res->flags & IORESOURCE_IO)) { + if (!res || !(res->flags & IORESOURCE_IO)) { DRM_INFO("platform has no IO space, trying MMIO\n"); ast->ioregs = ast->regs + AST_IO_MM_OFFSET; ast->io_space_uses_mmap = true; @@ -432,8 +429,6 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ret = -EIO; goto out_free; } - /* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */ - ast->ioregs = (void *)AST_IO_MM_OFFSET; } ast_detect_chip(dev, &need_post); diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 5c11fed423..8035b94070 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -24,7 +24,7 @@ static int send_kbd_command(u8 command) { int timeout; - timeout = 0x7ff; + timeout = 100000; /* 1 second */ while ((inb(ec_cmd_port) & KBD_IBF) && --timeout) { udelay(10); if ((timeout & 0xff) == 0) @@ -44,7 +44,7 @@ static int send_kbd_data(u8 data) { int timeout; - timeout = 0x7ff; + timeout = 100000; /* 1 second */ while ((inb(ec_cmd_port) & KBD_IBF) && --timeout) { /* wait for IBF = 0 */ udelay(10); if ((timeout & 0xff) == 0) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 62524a3e20..896183fd63 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3713,11 +3713,13 @@ #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b #define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_1 0x3e90 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT1_2 0x3e93 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_4 0x3e91 -#define PCI_DEVICE_ID_INTEL_CFL_U_GT2 0x3e96 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_5 0x3e96 #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 diff --git a/src/lib/metadata_hash.c b/src/lib/metadata_hash.c index f296cf58a5..a823c5f26f 100644 --- a/src/lib/metadata_hash.c +++ b/src/lib/metadata_hash.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include <assert.h> -#include <cbmem.h> #include <metadata_hash.h> #include <symbols.h> diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c index b1a99e0ee8..9d537e6428 100644 --- a/src/mainboard/biostar/th61-itx/early_init.c +++ b/src/mainboard/biostar/th61-itx/early_init.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootblock_common.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <stdbool.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 384e44bb57..ceba219ecf 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index b9f2830541..5ea04856bf 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index ab7bc8cf48..7d29df87f4 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -4,7 +4,6 @@ #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> -#include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) { diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index cd55c93a40..39a342810a 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <gpio.h> diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 7cc920d7ee..b4f3609ba0 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -213,15 +213,14 @@ chip soc/intel/cannonlake ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1, - .thresholds={TEMP_PCT(70, 100), - TEMP_PCT(66, 90), - TEMP_PCT(62, 80), - TEMP_PCT(58, 70), - TEMP_PCT(53, 60), - TEMP_PCT(48, 50), - TEMP_PCT(43, 40), - TEMP_PCT(38, 30),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(72, 90), + TEMP_PCT(68, 80), + TEMP_PCT(64, 70), + TEMP_PCT(58, 60), + TEMP_PCT(51, 50), + TEMP_PCT(42, 40), + TEMP_PCT(35, 30),}}" ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index 5b802033b6..f2a3a78aa7 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -2,7 +2,6 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> -#include <boardid.h> #include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index ec9ae3af86..349fe34068 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -2,7 +2,6 @@ #include <chip.h> #include <amdblocks/agesawrapper.h> -#include <boardid.h> #include <gpio.h> #include <console/console.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 4b50d4909d..79fd4784af 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,6 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> -#include <boardid.h> #include <chip.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 8628074837..22d8bb8448 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <boardid.h> #include <variant/gpio.h> /* diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index d01c51373e..599907e1da 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index d01c51373e..599907e1da 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 9c8e2a6abb..ea488ad90d 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 1a8a37164a..635d721110 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <sar.h> #include <baseboard/variants.h> #include <delay.h> diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 8148dcef2d..6dbc74a303 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c index e813fb122e..089b28a4cd 100644 --- a/src/mainboard/google/octopus/variants/lick/gpio.c +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 12e08be4c0..6bc69efbc9 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -12,7 +12,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c diff --git a/src/mainboard/google/sarien/hda_verb.c b/src/mainboard/google/sarien/hda_verb.c deleted file mode 100644 index c26029774e..0000000000 --- a/src/mainboard/google/sarien/hda_verb.c +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "variant/hda_verb.h" diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/arcada/hda_verb.c index 83acbc2857..b447e9f25b 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/arcada/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - #include <device/azalia_device.h> const u32 cim_verb_data[] = { @@ -192,5 +189,3 @@ const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/hda_verb.c index 5ec53ed112..316b110137 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - #include <device/azalia_device.h> const u32 cim_verb_data[] = { @@ -135,5 +132,3 @@ const u32 pc_beep_verbs[] = { }; AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 66440227e2..26a7e90d5e 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index d74476af16..ccde132176 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -58,6 +58,10 @@ fw_config option BOOT_SATA_DISABLED 0 option BOOT_SATA_ENABLED 1 end + field TOUCHPAD 25 + option REGULAR_TOUCHPAD 0 + option NUMPAD_TOUCHPAD 1 + end end chip soc/intel/tigerlake diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index d4e07460a2..1192129238 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -97,14 +97,26 @@ chip soc/intel/tigerlake end end device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on + probe TOUCHPAD REGULAR_TOUCHPAD + end + end chip drivers/i2c/hid - register "generic.hid" = ""ELAN0000"" + register "generic.hid" = ""ELAN2701"" register "generic.desc" = ""ELAN Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" register "generic.wake" = "GPE0_DW2_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end + device i2c 15 on + probe TOUCHPAD NUMPAD_TOUCHPAD + end end end device ref pch_espi on diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 96c109fbb5..608535e834 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -21,6 +21,9 @@ chip soc/intel/tigerlake .tdp_pl4 = 105, }" + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # Type-C port 0 + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -56,10 +59,24 @@ chip soc/intel/tigerlake }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 155, + .scl_hcnt = 80, + .sda_hold = 36, + }, }, }" device domain 0 on + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN3 + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -164,7 +181,7 @@ chip soc/intel/tigerlake device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref tcss_usb3_port2 on @@ -178,13 +195,13 @@ chip soc/intel/tigerlake chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port4 on @@ -209,7 +226,7 @@ chip soc/intel/tigerlake device ref usb2_port10 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb3_port1 on end diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl index 53f5d03783..4ef83fd33d 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -271,4 +271,70 @@ Scope (\_SB.PCI0.I2C2) } }) } + Device (NVM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_DDN, "AT24 EEPROM") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0050, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM1 + }) + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x06) + { + Package (0x02) + { + "size", + 0x2000 + }, + Package (0x02) + { + "pagesize", + One + }, + Package (0x02) + { + "read-only", + One + }, + Package (0x02) + { + "address-width", + 0x10 + }, + Package (0x02) + { + "compatible", + "atmel,24c64" + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } + } + }) + } } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 0b658a4129..948ce8f9d4 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio early_gpio_table[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 12d2890ce2..473ffb10cb 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a2ad51755f..341357e8cd 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -8,7 +8,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index ae2d02a48d..2452a1defe 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 2b46938e9b..a71aa78f02 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 7f9582c9b6..aeebd0707b 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index f86d926e2e..295fb21de2 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/gumboz/gpio.c b/src/mainboard/google/zork/variants/gumboz/gpio.c index aac25bb353..501c14402e 100644 --- a/src/mainboard/google/zork/variants/gumboz/gpio.c +++ b/src/mainboard/google/zork/variants/gumboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 9b36e3747e..778c6e4407 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c index 0fd867e8d4..db20e44699 100644 --- a/src/mainboard/google/zork/variants/shuboz/gpio.c +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 4d73ea0122..0546df4ae2 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index c6ef161647..5c918fddde 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index c3afe1372a..ad5cc7e511 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -24,7 +24,17 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "168" # eDP phy tuning settings - register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + register "edp_phy_override" = "ENABLE_EDP_TUNINGSET" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .margin_deemph = 0x004b, + .deemph_6db4 = 0x0, + .boostadj = 0x80, + }" # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, # and "0" as default value @@ -38,13 +48,6 @@ chip soc/amd/picasso register "pwrdown_bloff_to_varybloff" = "5" register "min_allowed_bl_level" = "0" - register "edp_tuningset" = "{ - .dp_vs_pemph_level = 0x0, - .deemph_6db4 = 0x004b, - .boostadj = 0x0, - .margin_deemph = 0x80, - }" - # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index f1e544cfa8..868a4c6757 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> #include <baseboard/variants.h> -#include <boardid.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a600d0a15b..9f8187fcf2 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -8,7 +8,6 @@ #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/device_nvs.h> -#include <boardid.h> #include "onboard.h" void mainboard_fill_gnvs(struct global_nvs *gnvs) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index d3d6168d15..0e7f88c2ef 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -2,7 +2,6 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <boardid.h> #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index eac843d903..e7ed500497 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include <boardid.h> #include "onboard.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0bb4476075..331db041f3 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -2,7 +2,6 @@ #include <soc/romstage.h> #include "onboard.h" -#include <boardid.h> void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default index 979f132863..681c40e78b 100644 --- a/src/mainboard/lenovo/l520/cmos.default +++ b/src/mainboard/lenovo/l520/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable backlight=Both usb_always_on=Disable +me_state=Normal diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index e96915d2d1..a3f5308aa4 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 10 backlight -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 13 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -89,6 +91,8 @@ enumerations 12 0 Disable 12 1 AC and battery 12 2 AC only +13 0 Normal +13 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 467f965829..8244071b8a 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable hybrid_graphics_mode=Integrated Only usb_always_on=Disable +me_state=Normal diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index e1d15be56b..daf569c0af 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 13 usb_always_on -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -97,6 +99,8 @@ enumerations 13 0 Disable 13 1 AC and battery 13 2 AC only +14 0 Normal +14 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 467f965829..8244071b8a 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable hybrid_graphics_mode=Integrated Only usb_always_on=Disable +me_state=Normal diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index e1d15be56b..daf569c0af 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 13 usb_always_on -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -97,6 +99,8 @@ enumerations 13 0 Disable 13 1 AC and battery 13 2 AC only +14 0 Normal +14 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default index e65869b332..26795fe5cf 100644 --- a/src/mainboard/lenovo/t430/cmos.default +++ b/src/mainboard/lenovo/t430/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable hybrid_graphics_mode=Integrated Only +me_state=Normal diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index dd51c36854..3e48df5584 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 10 backlight -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -96,6 +98,8 @@ enumerations 13 0 Disable 13 1 AC and battery 13 2 AC only +14 0 Normal +14 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index a30c90dc1f..52dbf70377 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -16,3 +16,4 @@ backlight=Both enable_dual_graphics=Disable usb_always_on=Disable f1_to_f12_as_primary=Enable +me_state=Normal diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 02c1ea78df..14a21eb84e 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -35,7 +35,9 @@ entries 422 2 e 10 backlight 424 1 e 1 f1_to_f12_as_primary -# coreboot config options: cpu +# coreboot config options: ME +425 1 e 13 me_state +426 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -94,6 +96,8 @@ enumerations 12 0 Disable 12 1 AC and battery 12 2 AC only +13 0 Normal +13 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 6e61dae340..cf79b391e2 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only usb_always_on=Disable +me_state=Normal diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index dd51c36854..3e48df5584 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 10 backlight -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -96,6 +98,8 @@ enumerations 13 0 Disable 13 1 AC and battery 13 2 AC only +14 0 Normal +14 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 6e61dae340..cf79b391e2 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both hybrid_graphics_mode=Integrated Only usb_always_on=Disable +me_state=Normal diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 6cd8ac066b..d109a61b4e 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 10 backlight -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -97,6 +99,8 @@ enumerations 13 0 Disable 13 1 AC and battery 13 2 AC only +14 0 Normal +14 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 42720a27bd..6d1d57a795 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -13,3 +13,4 @@ usb_always_on=Disable fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable +me_state=Normal diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index f152b2982a..c63ed8c22c 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -34,7 +34,9 @@ entries 421 1 e 9 sata_mode 422 2 e 12 usb_always_on -# coreboot config options: cpu +# coreboot config options: ME +424 1 e 13 me_state +425 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -92,6 +94,8 @@ enumerations 12 0 Disable 12 1 AC and battery 12 2 AC only +13 0 Normal +13 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 5c19d0f4a5..7314066c2b 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable f1_to_f12_as_primary=Enable +me_state=Normal diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 89891bf0b0..914e8ff5f6 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -35,7 +35,9 @@ entries 422 2 e 10 backlight 424 1 e 1 f1_to_f12_as_primary -# coreboot config options: cpu +# coreboot config options: ME +425 1 e 13 me_state +426 2 h 0 me_state_prev # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -94,6 +96,8 @@ enumerations 12 0 Disable 12 1 AC and battery 12 2 AC only +13 0 Normal +13 1 Disabled # ----------------------------------------------------------------- checksums diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 56a0664328..234ae8f4ad 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -2,7 +2,6 @@ #include <boot_device.h> #include <cbfs.h> -#include <cbmem.h> #include <commonlib/bsd/cbfs_private.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 189bc9d0d6..277707de1c 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -29,6 +29,7 @@ KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 6949fa57b3..a38d706f23 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -22,9 +22,7 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 /* IO 0xf0 NCP Error */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index e0c0e42190..7f3bea0da7 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 274291de56..9fc73d4e59 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <cbfs.h> -#include <cbmem.h> #include <console/console.h> #include <rmodule.h> #include <stage_cache.h> diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 244d7831ec..9a7d2a5bfc 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -253,7 +253,9 @@ struct soc_amd_picasso_config { bool acp_i2s_use_external_48mhz_osc; /* eDP phy tuning settings */ - uint8_t dp_phy_override; + uint16_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; struct { uint8_t dp_vs_pemph_level; diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index fa99db8334..e6cd51acc0 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -115,7 +115,7 @@ static void sb_rfmux_config_override(void) } } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -220,7 +220,7 @@ static void gpp_clk_setup(void) void fch_init(void *chip_info) { i2c_soc_init(); - sb_init_acpi_ports(); + fch_init_acpi_ports(); acpi_pm_gpe_add_events_print_events(); gpio_add_events(); diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 731a564416..df5e1e61b4 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -145,12 +145,13 @@ static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) { - if (cfg->dp_phy_override & ENABLE_EDP_TUNINGSET) { - scfg->DpPhyOverride = cfg->dp_phy_override; - scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level; - scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph; - scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; - scfg->BoostAdj = cfg->edp_tuningset.boostadj; + if (cfg->edp_phy_override & ENABLE_EDP_TUNINGSET) { + scfg->edp_phy_override = cfg->edp_phy_override; + scfg->edp_physel = cfg->edp_physel; + scfg->edp_dp_vs_pemph_level = cfg->edp_tuningset.dp_vs_pemph_level; + scfg->edp_margin_deemph = cfg->edp_tuningset.margin_deemph; + scfg->edp_deemph_6db_4 = cfg->edp_tuningset.deemph_6db4; + scfg->edp_boost_adj = cfg->edp_tuningset.boostadj; } if (cfg->edp_pwr_adjust_enable) { scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2a915965bb..2a78ff9650 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -356,7 +356,7 @@ void sb_enable(struct device *dev) printk(BIOS_DEBUG, "%s\n", __func__); } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -406,7 +406,7 @@ void fch_init(void *chip_info) { struct chipset_power_state *state; - sb_init_acpi_ports(); + fch_init_acpi_ports(); state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); if (state) { diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 55ecc006ba..9800563d81 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 773f56eff2..2c271d26ec 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -9,7 +9,6 @@ #include <arch/smp/mpspec.h> #include <assert.h> #include <device/pci_ops.h> -#include <cbmem.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 5433fdc4c5..153ef04073 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -6,7 +6,6 @@ #include <arch/ioapic.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 8cd7336a62..d8623ae06e 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/tsc.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index b9b3424597..f60ebd8462 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <cpu/intel/haswell/haswell.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 38f057e129..48a83df7b2 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <device/pci_ops.h> #include <console/console.h> #include <types.h> diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 31d6ad8482..5d3ccce7d9 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -2,7 +2,6 @@ #include <string.h> #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <program_loading.h> diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 943c15e70b..37fe21672d 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 87b4be7844..9c393e5cec 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -122,11 +122,13 @@ static struct { { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, "Coffeelake-S GT1" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, "Coffeelake-S GT1" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_U_GT2, "Coffeelake-U GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7150babc83..ca96f35d20 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -221,11 +221,13 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, + PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, - PCI_DEVICE_ID_INTEL_CFL_U_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index cf5613853e..d70706256e 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -18,10 +18,10 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ /* MCHBAR */ -#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR64(x) (*(volatile u64 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR32(x) (*(volatile u32 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR64(x) (*(volatile u64 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) /* Perform System Agent Initialization during Bootblock phase */ void bootblock_systemagent_early_init(void); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index ff7457c166..ba64c0436c 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 6a8e329035..67b7ca513f 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 7702bf03e4..a3c2b259d6 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> #include <intelblocks/cpulib.h> diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index cb1731f38c..f3e821f439 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d3062cc720..edc716064f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -105,6 +105,9 @@ struct soc_intel_tigerlake_config { /* Common struct containing power limits configuration information */ struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX]; + /* Configuration for boot TDP selection; */ + uint8_t ConfigTdpLevel; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 7f7135e308..49af38454f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -57,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_BLOCK_ACPI select TSC_MONOTONIC_TIMER + select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 99326ee6a4..5e1b412fd3 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> -#include <cbmem.h> #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 2d286231a6..79768d48c9 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> -#include <cbmem.h> #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index aa8079ef6b..b3a9693ea4 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <boardid.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/dramc_common.h> diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 93588904b5..daea209082 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -2,7 +2,6 @@ #include <console/cbmem_console.h> #include <cbmem.h> -#include <boardid.h> #include <bootmode.h> #include <string.h> #include <fmap.h> diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index c0a7589abd..66d7c2003e 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <commonlib/bsd/helpers.h> #include <stdint.h> #include <symbols.h> diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 21816e5136..e3ad885cb4 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -56,4 +56,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index a591aabea0..fdf9b87e64 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -31,6 +31,7 @@ smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c romstage-y += me_status.c romstage-y += early_rcba.c romstage-y += early_pch.c +romstage-y += me_common.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_thermal.c early_me.c early_usb.c diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 6320d2ea9f..b7a3b44d06 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -91,22 +91,6 @@ int intel_early_me_uma_size(void) return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset, errorcode, opmode; @@ -163,7 +147,7 @@ int intel_early_me_init_done(u8 status) if ((me_fws2 & 0x80) == 0x80) { printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n"); pci_and_config16(PCI_DEV(0, 31, 0), 0xa2, ~0x80); - set_global_reset(0); + set_global_reset(false); system_reset(); } @@ -232,17 +216,17 @@ int intel_early_me_init_done(u8 status) return 0; case ME_HFS_ACK_RESET: /* Non-power cycle reset */ - set_global_reset(0); + set_global_reset(false); reset |= 0x06; break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ - set_global_reset(0); + set_global_reset(false); reset |= 0x0e; break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ - set_global_reset(1); + set_global_reset(true); reset |= 0x0e; break; case ME_HFS_ACK_S3: diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 0b11fd0e81..847c708f42 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -96,22 +96,6 @@ int intel_early_me_uma_size(void) return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset; @@ -160,17 +144,17 @@ int intel_early_me_init_done(u8 status) return 0; case ME_HFS_ACK_RESET: /* Non-power cycle reset */ - set_global_reset(0); + set_global_reset(false); reset = 0x06; break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ - set_global_reset(0); + set_global_reset(false); reset = 0x0e; break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ - set_global_reset(1); + set_global_reset(true); reset = 0x0e; break; case ME_HFS_ACK_S3: diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 2adfbd5c98..558ee91e6a 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -9,6 +9,7 @@ */ #include <acpi/acpi.h> +#include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> @@ -19,6 +20,8 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> +#include <option.h> #include "me.h" #include "pch.h" @@ -248,12 +251,23 @@ static me_bios_path intel_me_path(struct device *dev) static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); + u8 me_state = 0, me_state_prev = 0; + bool need_reset = false; + struct me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); + get_option(&me_state, "me_state"); + get_option(&me_state_prev, "me_state_prev"); + + printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev); + switch (path) { case ME_S3WAKE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -273,18 +287,68 @@ static void intel_me_init(struct device *dev) mkhi_get_fwcaps(); } + /* Put ME in Software Temporary Disable Mode, if needed */ + if (me_state == CMOS_ME_STATE_DISABLED + && CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_NORMAL) { + printk(BIOS_INFO, "ME: disabling ME\n"); + if (enter_soft_temp_disable()) { + enter_soft_temp_disable_wait(); + need_reset = true; + } else { + printk(BIOS_ERR, "ME: failed to enter Soft Temporary Disable mode\n"); + } + + break; + } + /* * Leave the ME unlocked in this path. * It will be locked via SMI command later. */ break; + case ME_DISABLE_BIOS_PATH: + /* Bring ME out of Soft Temporary Disable mode, if needed */ + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.operation_mode == ME_HFS_MODE_DIS + && me_state == CMOS_ME_STATE_NORMAL + && (CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_DISABLED + || !CMOS_ME_CHANGED(me_state_prev))) { + printk(BIOS_INFO, "ME: re-enabling ME\n"); + + exit_soft_temp_disable(dev); + exit_soft_temp_disable_wait(dev); + + /* + * ME starts loading firmware immediately after writing to H_GS, + * but Lenovo BIOS performs a reboot after bringing ME back to + * Normal mode. Assume that global reset is needed. + */ + need_reset = true; + } else { + intel_me_hide(dev); + } + break; + +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } + + /* To avoid boot loops if ME fails to get back from disabled mode, + set the 'changed' bit here. */ + if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { + u8 new_state = me_state | CMOS_ME_STATE_CHANGED; + set_option("me_state_prev", &new_state); + } + + if (need_reset) { + set_global_reset(true); + full_reset(); + } } static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 014fc1d9ea..dfe2eb0bbf 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -171,6 +171,22 @@ struct mei_header { #define MKHI_GLOBAL_RESET 0x0b #define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_FWCAPS_SET_RULE 0x03 + +#define MKHI_DISABLE_RULE_ID 0x06 + +#define CMOS_ME_STATE(state) ((state) & 0x1) +#define CMOS_ME_CHANGED(state) (((state) & 0x2) >> 1) +#define CMOS_ME_STATE_NORMAL 0 +#define CMOS_ME_STATE_DISABLED 1 +#define CMOS_ME_STATE_CHANGED 2 + +#define ME_ENABLE_TIMEOUT 20000 + +struct me_disable { + u32 rule_id; + u32 data; +} __packed; #define MKHI_MDES_ENABLE 0x09 @@ -228,6 +244,10 @@ void mei_write_dword_ptr(void *ptr, int offset); #ifndef __SIMPLE_DEVICE__ void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); +bool enter_soft_temp_disable(void); +void enter_soft_temp_disable_wait(void); +void exit_soft_temp_disable(struct device *dev); +void exit_soft_temp_disable_wait(struct device *dev); #endif void read_host_csr(struct mei_csr *csr); @@ -247,6 +267,8 @@ int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); +void set_global_reset(bool enable); + /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b0226a6e9a..3d9ebd6026 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -9,6 +9,7 @@ */ #include <acpi/acpi.h> +#include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> @@ -19,6 +20,8 @@ #include <string.h> #include <delay.h> #include <elog.h> +#include <halt.h> +#include <option.h> #include "me.h" #include "pch.h" @@ -206,8 +209,7 @@ static me_bios_path intel_me_path(struct device *dev) /* Check if the MBP is ready */ if (!gmes.mbp_rdy) { - printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __func__); + printk(BIOS_CRIT, "%s: mbp is not ready!\n", __func__); path = ME_ERROR_BIOS_PATH; } @@ -236,12 +238,23 @@ static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; + u8 me_state = 0, me_state_prev = 0; + bool need_reset = false; + struct me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); + get_option(&me_state, "me_state"); + get_option(&me_state_prev, "me_state_prev"); + + printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev); + switch (path) { case ME_S3WAKE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -262,18 +275,68 @@ static void intel_me_init(struct device *dev) me_print_fwcaps(&mbp_data.fw_caps_sku); } + /* Put ME in Software Temporary Disable Mode, if needed */ + if (me_state == CMOS_ME_STATE_DISABLED + && CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_NORMAL) { + printk(BIOS_INFO, "ME: disabling ME\n"); + if (enter_soft_temp_disable()) { + enter_soft_temp_disable_wait(); + need_reset = true; + } else { + printk(BIOS_ERR, "ME: failed to enter Soft Temporary Disable mode\n"); + } + + break; + } + /* * Leave the ME unlocked in this path. * It will be locked via SMI command later. */ break; + case ME_DISABLE_BIOS_PATH: + /* Bring ME out of Soft Temporary Disable mode, if needed */ + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.operation_mode == ME_HFS_MODE_DIS + && me_state == CMOS_ME_STATE_NORMAL + && (CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_DISABLED + || !CMOS_ME_CHANGED(me_state_prev))) { + printk(BIOS_INFO, "ME: re-enabling ME\n"); + + exit_soft_temp_disable(dev); + exit_soft_temp_disable_wait(dev); + + /* + * ME starts loading firmware immediately after writing to H_GS, + * but Lenovo BIOS performs a reboot after bringing ME back to + * Normal mode. Assume that global reset is needed. + */ + need_reset = true; + } else { + intel_me_hide(dev); + } + break; + +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } + + /* To avoid boot loops if ME fails to get back from disabled mode, + set the 'changed' bit here. */ + if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { + u8 new_state = me_state | CMOS_ME_STATE_CHANGED; + set_option("me_state_prev", &new_state); + } + + if (need_reset) { + set_global_reset(true); + full_reset(); + } } static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 422c091001..1b25d146be 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -11,6 +11,7 @@ #include <string.h> #include <delay.h> #include <halt.h> +#include <timer.h> #include "me.h" #include "pch.h" @@ -417,4 +418,103 @@ void intel_me_hide(struct device *dev) pch_enable(dev); } +bool enter_soft_temp_disable(void) +{ + /* The binary sequence for the disable command was found by PT in some vendor BIOS */ + struct me_disable message = { + .rule_id = MKHI_DISABLE_RULE_ID, + .data = 0x01, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_SET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(message), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + u32 resp; + + if (mei_sendrecv(&mei, &mkhi, &message, &resp, sizeof(resp)) < 0 + || resp != MKHI_DISABLE_RULE_ID) { + printk(BIOS_WARNING, "ME: disable command failed\n"); + return false; + } + + return true; +} + +void enter_soft_temp_disable_wait(void) +{ + /* + * TODO: Find smarter way to determine when we're ready to reboot. + * + * There has to be some bit in some register, or something, that indicates that ME has + * finished doing its thing and we're ready to reboot. + * + * It was not found yet, though, and waiting for a response after the disable command is + * not enough. If we reboot too early, ME will not be disabled on next boot. For now, + * let's just wait for 1 second here. + */ + mdelay(1000); +} + +void exit_soft_temp_disable(struct device *dev) +{ + /* To bring ME out of Soft Temporary Disable Mode, host writes 0x20000000 to H_GS */ + pci_write_config32(dev, PCI_ME_H_GS, 0x2 << 28); +} + +void exit_soft_temp_disable_wait(struct device *dev) +{ + struct me_hfs hfs; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, ME_ENABLE_TIMEOUT); + + /** + * Wait for fw_init_complete. Check every 50 ms, give up after 20 sec. + * This is what vendor BIOS does. Usually it takes 1.5 seconds or so. + */ + do { + mdelay(50); + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.fw_init_complete) + break; + } while (!stopwatch_expired(&sw)); + + if (!hfs.fw_init_complete) + printk(BIOS_ERR, "ME: giving up on waiting for fw_init_complete\n"); + else + printk(BIOS_NOTICE, "ME: took %lums to complete initialization\n", + stopwatch_duration_msecs(&sw)); +} + +#endif + +void set_global_reset(bool enable) +{ +#ifdef __SIMPLE_DEVICE__ + u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); +#else + struct device *lpc = pcidev_on_root(0x1f, 0); + u32 etr3 = pci_read_config32(lpc, ETR3); +#endif + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + +#ifdef __SIMPLE_DEVICE__ + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +#else + pci_write_config32(lpc, ETR3, etr3); #endif +} diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f172bf1eb3..34ae2f112a 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -53,4 +53,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index c745b0a552..da33778454 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -30,6 +30,7 @@ smm-y += smihandler.c romstage-y += early_pch.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c +romstage-y +=../bd82x6x/me_common.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c romstage-y += early_cir.c diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6a45fb42eb..20b8aac94a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -476,6 +476,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -494,9 +498,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8482..aac6fdbcfb 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,26 +39,22 @@ typedef struct __packed { /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 0e9ca02d35..d0421723eb 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -595,262 +595,262 @@ typedef struct { /** Offset 0x038F - Reserved
**/
- UINT8 Reserved21[11];
+ UINT8 Reserved21[3];
-/** Offset 0x039A - BiosGuard
+/** Offset 0x0392 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x039B
+/** Offset 0x0393
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x039C - Reserved
+/** Offset 0x0394 - Reserved
**/
UINT8 Reserved22[4];
-/** Offset 0x03A0 - PrmrrSize
+/** Offset 0x0398 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x03A4 - SinitMemorySize
+/** Offset 0x039C - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x03A8 - Reserved
+/** Offset 0x03A0 - Reserved
**/
UINT8 Reserved23[8];
-/** Offset 0x03B0 - TxtHeapMemorySize
+/** Offset 0x03A8 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x03B4 - TxtDprMemorySize
+/** Offset 0x03AC - TxtDprMemorySize
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x03B8 - Reserved
+/** Offset 0x03B0 - Reserved
**/
- UINT8 Reserved24[614];
+ UINT8 Reserved24[625];
-/** Offset 0x061E - Number of RsvdSmbusAddressTable.
+/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x061F - Reserved
+/** Offset 0x0622 - Reserved
**/
- UINT8 Reserved25[4];
+ UINT8 Reserved25[3];
-/** Offset 0x0623 - Usage type for ClkSrc
+/** Offset 0x0625 - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
(free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
-/** Offset 0x0635 - Reserved
+/** Offset 0x0637 - Reserved
**/
UINT8 Reserved26[14];
-/** Offset 0x0643 - ClkReq-to-ClkSrc mapping
+/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
-/** Offset 0x0655 - Reserved
+/** Offset 0x0657 - Reserved
**/
- UINT8 Reserved27[91];
+ UINT8 Reserved27[93];
-/** Offset 0x06B0 - Enable PCIE RP Mask
+/** Offset 0x06B4 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpEnableMask;
-/** Offset 0x06B4 - Reserved
+/** Offset 0x06B8 - Reserved
**/
UINT8 Reserved28[2];
-/** Offset 0x06B6 - Enable HD Audio Link
+/** Offset 0x06BA - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
-/** Offset 0x06B7 - Reserved
+/** Offset 0x06BB - Reserved
**/
UINT8 Reserved29[3];
-/** Offset 0x06BA - Enable HD Audio DMIC_N Link
+/** Offset 0x06BE - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
-/** Offset 0x06BC - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-/** Offset 0x06C4 - DMIC<N> ClkB Pin Muxing
+/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-/** Offset 0x06CC - Enable HD Audio DSP
+/** Offset 0x06D0 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x06CD - Reserved
+/** Offset 0x06D1 - Reserved
**/
UINT8 Reserved30[3];
-/** Offset 0x06D0 - DMIC<N> Data Pin Muxing
+/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-/** Offset 0x06D8 - Enable HD Audio SSP0 Link
+/** Offset 0x06DC - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
-/** Offset 0x06DE - Enable HD Audio SoundWire#N Link
+/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
-/** Offset 0x06E2 - iDisp-Link Frequency
+/** Offset 0x06E6 - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x06E3 - iDisp-Link T-mode
+/** Offset 0x06E7 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x06E4 - iDisplay Audio Codec disconnection
+/** Offset 0x06E8 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x06E5 - Debug Interfaces
+/** Offset 0x06E9 - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
-/** Offset 0x06E6 - Serial Io Uart Debug Controller Number
+/** Offset 0x06EA - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
Core interface, it cannot be used for debug purpose.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x06E7 - Reserved
+/** Offset 0x06EB - Reserved
**/
UINT8 Reserved31[13];
-/** Offset 0x06F4 - ISA Serial Base selection
+/** Offset 0x06F8 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x06F5 - Reserved
+/** Offset 0x06F9 - Reserved
**/
UINT8 Reserved32[4];
-/** Offset 0x06F9 - MRC Safe Config
+/** Offset 0x06FD - MRC Safe Config
Enables/Disable MRC Safe Config
$EN_DIS
**/
UINT8 MrcSafeConfig;
-/** Offset 0x06FA - TCSS Thunderbolt PCIE Root Port 0 Enable
+/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
-/** Offset 0x06FB - TCSS Thunderbolt PCIE Root Port 1 Enable
+/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
-/** Offset 0x06FC - TCSS Thunderbolt PCIE Root Port 2 Enable
+/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
-/** Offset 0x06FD - TCSS Thunderbolt PCIE Root Port 3 Enable
+/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
-/** Offset 0x06FE - TCSS USB HOST (xHCI) Enable
+/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
-/** Offset 0x06FF - TCSS USB DEVICE (xDCI) Enable
+/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
-/** Offset 0x0700 - TCSS DMA0 Enable
+/** Offset 0x0704 - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
-/** Offset 0x0701 - TCSS DMA1 Enable
+/** Offset 0x0705 - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
-/** Offset 0x0702 - Reserved
+/** Offset 0x0706 - Reserved
**/
UINT8 Reserved33[2];
-/** Offset 0x0704 - Early Command Training
+/** Offset 0x0708 - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
-/** Offset 0x0705 - Reserved
+/** Offset 0x0709 - Reserved
**/
UINT8 Reserved34[65];
-/** Offset 0x0746 - Ch Hash Mask
+/** Offset 0x074A - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
-/** Offset 0x0748 - Reserved
+/** Offset 0x074C - Reserved
**/
- UINT8 Reserved35[64];
+ UINT8 Reserved35[66];
-/** Offset 0x0788 - PcdSerialDebugLevel
+/** Offset 0x078E - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -859,91 +859,91 @@ typedef struct { **/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x0789 - Reserved
+/** Offset 0x078F - Reserved
**/
UINT8 Reserved36[2];
-/** Offset 0x078B - Safe Mode Support
+/** Offset 0x0791 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
$EN_DIS
**/
UINT8 SafeMode;
-/** Offset 0x078C - Reserved
+/** Offset 0x0792 - Reserved
**/
UINT8 Reserved37[2];
-/** Offset 0x078E - TCSS USB Port Enable
+/** Offset 0x0794 - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
-/** Offset 0x078F - Reserved
+/** Offset 0x0795 - Reserved
**/
- UINT8 Reserved38[35];
+ UINT8 Reserved38[33];
-/** Offset 0x07B2 - Command Pins Mapping
+/** Offset 0x07B6 - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x07B3 - Reserved
+/** Offset 0x07B7 - Reserved
**/
- UINT8 Reserved39[14];
+ UINT8 Reserved39[12];
-/** Offset 0x07C1 - Skip external display device scanning
+/** Offset 0x07C3 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x07C2 - Reserved
+/** Offset 0x07C4 - Reserved
**/
UINT8 Reserved40;
-/** Offset 0x07C3 - Lock PCU Thermal Management registers
+/** Offset 0x07C5 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x07C4 - Reserved
+/** Offset 0x07C6 - Reserved
**/
- UINT8 Reserved41[129];
+ UINT8 Reserved41[131];
-/** Offset 0x0845 - Skip CPU replacement check
+/** Offset 0x0849 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0846 - Reserved
+/** Offset 0x084A - Reserved
**/
UINT8 Reserved42[292];
-/** Offset 0x096A - Serial Io Uart Debug Mode
+/** Offset 0x096E - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x096B - Reserved
+/** Offset 0x096F - Reserved
**/
- UINT8 Reserved43[183];
+ UINT8 Reserved43[185];
-/** Offset 0x0A22 - GPIO Override
+/** Offset 0x0A28 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
**/
UINT8 GpioOverride;
-/** Offset 0x0A23 - Reserved
+/** Offset 0x0A29 - Reserved
**/
- UINT8 Reserved44[349];
+ UINT8 Reserved44[23];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -962,11 +962,11 @@ typedef struct { **/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0B80
+/** Offset 0x0A40
**/
- UINT8 UnusedUpdSpace29[6];
+ UINT8 UnusedUpdSpace25[6];
-/** Offset 0x0B86
+/** Offset 0x0A46
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index d9cbc5b832..8a92e001af 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -377,40 +377,44 @@ typedef struct { **/
UINT8 CnviMode;
-/** Offset 0x043D - CNVi BT Core
+/** Offset 0x043D - Reserved
+**/
+ UINT8 Reserved15;
+
+/** Offset 0x043E - CNVi BT Core
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtCore;
-/** Offset 0x043E - CNVi BT Audio Offload
+/** Offset 0x043F - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
-/** Offset 0x043F - Reserved
+/** Offset 0x0440 - Reserved
**/
- UINT8 Reserved15;
+ UINT8 Reserved16[4];
-/** Offset 0x0440 - CNVi RF_RESET pin muxing
+/** Offset 0x0444 - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
-/** Offset 0x0444 - CNVi CLKREQ pin muxing
+/** Offset 0x0448 - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
in GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
-/** Offset 0x0448 - Reserved
+/** Offset 0x044C - Reserved
**/
- UINT8 Reserved16[172];
+ UINT8 Reserved17[172];
-/** Offset 0x04F4 - CdClock Frequency selection
+/** Offset 0x04F8 - CdClock Frequency selection
0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
@@ -418,293 +422,293 @@ typedef struct { **/
UINT8 CdClock;
-/** Offset 0x04F5 - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit
<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
Disable: FSP will NOT initialize the framebuffer.
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
-/** Offset 0x04F6 - Enable D3 Hot in TCSS
+/** Offset 0x04FA - Enable D3 Hot in TCSS
This policy will enable/disable D3 hot support in IOM
$EN_DIS
**/
UINT8 D3HotEnable;
-/** Offset 0x04F7 - Reserved
+/** Offset 0x04FB - Reserved
**/
- UINT8 Reserved17;
+ UINT8 Reserved18;
-/** Offset 0x04F8 - TypeC port GPIO setting
+/** Offset 0x04FC - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
= AlderLake)
**/
UINT32 IomTypeCPortPadCfg[8];
-/** Offset 0x0518 - Reserved
+/** Offset 0x051C - Reserved
**/
- UINT8 Reserved18[8];
+ UINT8 Reserved19[8];
-/** Offset 0x0520 - Enable D3 Cold in TCSS
+/** Offset 0x0524 - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
$EN_DIS
**/
UINT8 D3ColdEnable;
-/** Offset 0x0521 - Reserved
+/** Offset 0x0525 - Reserved
**/
- UINT8 Reserved19[8];
+ UINT8 Reserved20[16];
-/** Offset 0x0529 - Enable VMD controller
- Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+/** Offset 0x0535 - Enable VMD controller
+ Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
$EN_DIS
**/
UINT8 VmdEnable;
-/** Offset 0x052A - Reserved
+/** Offset 0x0536 - Reserved
**/
- UINT8 Reserved20[120];
+ UINT8 Reserved21[120];
-/** Offset 0x05A2 - TCSS Aux Orientation Override Enable
+/** Offset 0x05AE - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssAuxOri;
-/** Offset 0x05A4 - TCSS HSL Orientation Override Enable
+/** Offset 0x05B0 - TCSS HSL Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssHslOri;
-/** Offset 0x05A6 - Reserved
+/** Offset 0x05B2 - Reserved
**/
- UINT8 Reserved21;
+ UINT8 Reserved22;
-/** Offset 0x05A7 - ITBT Root Port Enable
+/** Offset 0x05B3 - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
0:Disable, 1:Enable
**/
UINT8 ITbtPcieRootPortEn[4];
-/** Offset 0x05AB - Reserved
+/** Offset 0x05B7 - Reserved
**/
- UINT8 Reserved22[3];
+ UINT8 Reserved23[3];
-/** Offset 0x05AE - ITbtConnectTopology Timeout value
+/** Offset 0x05BA - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
is 0-10000. 100 = 100 ms.
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
-/** Offset 0x05B0 - Reserved
+/** Offset 0x05BC - Reserved
**/
- UINT8 Reserved23[7];
+ UINT8 Reserved24[7];
-/** Offset 0x05B7 - Enable/Disable PTM
+/** Offset 0x05C3 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
$EN_DIS
**/
UINT8 PtmEnabled[4];
-/** Offset 0x05BB - Reserved
+/** Offset 0x05C7 - Reserved
**/
- UINT8 Reserved24[200];
+ UINT8 Reserved25[200];
-/** Offset 0x0683 - Skip Multi-Processor Initialization
+/** Offset 0x068F - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. </b>0: Initialize; <b>1: Skip
$EN_DIS
**/
UINT8 SkipMpInit;
-/** Offset 0x0684 - Reserved
+/** Offset 0x0690 - Reserved
**/
- UINT8 Reserved25[8];
+ UINT8 Reserved26[8];
-/** Offset 0x068C - CpuMpPpi
+/** Offset 0x0698 - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
If not NULL, FSP will use the boot loader's implementation of multiprocessing.
See section 5.1.4 of the FSP Integration Guide for more details.
**/
UINT32 CpuMpPpi;
-/** Offset 0x0690 - Reserved
+/** Offset 0x069C - Reserved
**/
- UINT8 Reserved26[74];
+ UINT8 Reserved27[70];
-/** Offset 0x06DA - Enable Power Optimizer
+/** Offset 0x06E2 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x06DB - Reserved
+/** Offset 0x06E3 - Reserved
**/
- UINT8 Reserved27[33];
+ UINT8 Reserved28[33];
-/** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned
+/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
-/** Offset 0x06FD - Reserved
+/** Offset 0x0705 - Reserved
**/
- UINT8 Reserved28[2];
+ UINT8 Reserved29[2];
-/** Offset 0x06FF - Enable PCH ISH SPI pins assigned
+/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiEnable[1];
-/** Offset 0x0700 - Enable PCH ISH UART pins assigned
+/** Offset 0x0708 - Enable PCH ISH UART pins assigned
Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshUartEnable[2];
-/** Offset 0x0702 - Enable PCH ISH I2C pins assigned
+/** Offset 0x070A - Enable PCH ISH I2C pins assigned
Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI2cEnable[3];
-/** Offset 0x0705 - Enable PCH ISH GP pins assigned
+/** Offset 0x070D - Enable PCH ISH GP pins assigned
Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshGpEnable[8];
-/** Offset 0x070D - Reserved
+/** Offset 0x0715 - Reserved
**/
- UINT8 Reserved29[2];
+ UINT8 Reserved30[2];
-/** Offset 0x070F - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x0710 - Reserved
+/** Offset 0x0718 - Reserved
**/
- UINT8 Reserved30[2];
+ UINT8 Reserved31[2];
-/** Offset 0x0712 - RTC Cmos Memory Lock
+/** Offset 0x071A - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
-/** Offset 0x0713 - Enable PCIE RP HotPlug
+/** Offset 0x071B - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[28];
-/** Offset 0x072F - Reserved
+/** Offset 0x0737 - Reserved
**/
- UINT8 Reserved31[56];
+ UINT8 Reserved32[56];
-/** Offset 0x0767 - Enable PCIE RP Clk Req Detect
+/** Offset 0x076F - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[28];
-/** Offset 0x0783 - PCIE RP Advanced Error Report
+/** Offset 0x078B - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[28];
-/** Offset 0x079F - Reserved
+/** Offset 0x07A7 - Reserved
**/
- UINT8 Reserved32[196];
+ UINT8 Reserved33[196];
-/** Offset 0x0863 - PCIE RP Max Payload
+/** Offset 0x086B - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[28];
-/** Offset 0x087F - Touch Host Controller Port 0 Assignment
+/** Offset 0x0887 - Touch Host Controller Port 0 Assignment
Assign THC Port 0
0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
**/
UINT8 ThcPort0Assignment;
-/** Offset 0x0880 - Reserved
+/** Offset 0x0888 - Reserved
**/
- UINT8 Reserved33[5];
+ UINT8 Reserved34[5];
-/** Offset 0x0885 - Touch Host Controller Port 1 Assignment
+/** Offset 0x088D - Touch Host Controller Port 1 Assignment
Assign THC Port 1
0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
**/
UINT8 ThcPort1Assignment;
-/** Offset 0x0886 - Reserved
+/** Offset 0x088E - Reserved
**/
- UINT8 Reserved34[91];
+ UINT8 Reserved35[91];
-/** Offset 0x08E1 - PCIE RP Aspm
+/** Offset 0x08E9 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[28];
-/** Offset 0x08FD - PCIE RP L1 Substates
+/** Offset 0x0905 - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[28];
-/** Offset 0x0919 - Reserved
+/** Offset 0x0921 - Reserved
**/
- UINT8 Reserved35[28];
+ UINT8 Reserved36[28];
-/** Offset 0x0935 - PCIE RP Ltr Enable
+/** Offset 0x093D - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[28];
-/** Offset 0x0951 - Reserved
+/** Offset 0x0959 - Reserved
**/
- UINT8 Reserved36[132];
+ UINT8 Reserved37[132];
-/** Offset 0x09D5 - PCH Sata Pwr Opt Enable
+/** Offset 0x09DD - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x09D6 - Reserved
+/** Offset 0x09DE - Reserved
**/
- UINT8 Reserved37[50];
+ UINT8 Reserved38[50];
-/** Offset 0x0A08 - Enable SATA Port DmVal
+/** Offset 0x0A10 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x0A10 - Enable SATA Port DmVal
+/** Offset 0x0A18 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x0A20 - Reserved
+/** Offset 0x0A28 - Reserved
**/
- UINT8 Reserved38[62];
+ UINT8 Reserved39[62];
-/** Offset 0x0A5E - USB2 Port Over Current Pin
+/** Offset 0x0A66 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x0A6E - USB3 Port Over Current Pin
+/** Offset 0x0A76 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x0A78 - Reserved
+/** Offset 0x0A80 - Reserved
**/
- UINT8 Reserved39[16];
+ UINT8 Reserved40[16];
-/** Offset 0x0A88 - Enable 8254 Static Clock Gating
+/** Offset 0x0A90 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -712,7 +716,7 @@ typedef struct { **/
UINT8 Enable8254ClockGating;
-/** Offset 0x0A89 - Enable 8254 Static Clock Gating On S3
+/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -720,22 +724,22 @@ typedef struct { **/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x0A8A - Reserved
+/** Offset 0x0A92 - Reserved
**/
- UINT8 Reserved40;
+ UINT8 Reserved41;
-/** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode
+/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 HybridStorageMode;
-/** Offset 0x0A8C - Reserved
+/** Offset 0x0A94 - Reserved
**/
- UINT8 Reserved41[93];
+ UINT8 Reserved42[93];
-/** Offset 0x0AE9 - Enable PS_ON.
+/** Offset 0x0AF1 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -743,29 +747,29 @@ typedef struct { **/
UINT8 PsOnEnable;
-/** Offset 0x0AEA - Reserved
+/** Offset 0x0AF2 - Reserved
**/
- UINT8 Reserved42[318];
+ UINT8 Reserved43[318];
-/** Offset 0x0C28 - RpPtmBytes
+/** Offset 0x0C30 - RpPtmBytes
**/
UINT8 RpPtmBytes[4];
-/** Offset 0x0C2C - Reserved
+/** Offset 0x0C34 - Reserved
**/
- UINT8 Reserved43[95];
+ UINT8 Reserved44[95];
-/** Offset 0x0C8B - Enable/Disable IGFX PmSupport
+/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
-/** Offset 0x0C8C - Reserved
+/** Offset 0x0C94 - Reserved
**/
- UINT8 Reserved44;
+ UINT8 Reserved45;
-/** Offset 0x0C8D - GT Frequency Limit
+/** Offset 0x0C95 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -779,22 +783,22 @@ typedef struct { **/
UINT8 GtFreqMax;
-/** Offset 0x0C8E - Reserved
+/** Offset 0x0C96 - Reserved
**/
- UINT8 Reserved45[24];
+ UINT8 Reserved46[24];
-/** Offset 0x0CA6 - Enable or Disable HWP
+/** Offset 0x0CAE - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2-3:Reserved
$EN_DIS
**/
UINT8 Hwp;
-/** Offset 0x0CA7 - Reserved
+/** Offset 0x0CAF - Reserved
**/
- UINT8 Reserved46[8];
+ UINT8 Reserved47[8];
-/** Offset 0x0CAF - TCC Activation Offset
+/** Offset 0x0CB7 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
@@ -802,63 +806,63 @@ typedef struct { **/
UINT8 TccActivationOffset;
-/** Offset 0x0CB0 - Reserved
+/** Offset 0x0CB8 - Reserved
**/
- UINT8 Reserved47[34];
+ UINT8 Reserved48[34];
-/** Offset 0x0CD2 - Enable or Disable CPU power states (C-states)
+/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x0CD3 - Reserved
+/** Offset 0x0CDB - Reserved
**/
- UINT8 Reserved48[196];
+ UINT8 Reserved49[196];
-/** Offset 0x0D97 - Enable LOCKDOWN SMI
+/** Offset 0x0D9F - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x0D98 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x0D99 - Unlock all GPIO pads
+/** Offset 0x0DA1 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x0D9A - Reserved
+/** Offset 0x0DA2 - Reserved
**/
- UINT8 Reserved49[2];
+ UINT8 Reserved50[2];
-/** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[28];
-/** Offset 0x0DD4 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[28];
-/** Offset 0x0E0C - Reserved
+/** Offset 0x0E14 - Reserved
**/
- UINT8 Reserved50[313];
+ UINT8 Reserved51[313];
-/** Offset 0x0F45 - LpmStateEnableMask
+/** Offset 0x0F4D - LpmStateEnableMask
**/
UINT8 LpmStateEnableMask;
-/** Offset 0x0F46 - Reserved
+/** Offset 0x0F4E - Reserved
**/
- UINT8 Reserved51[698];
+ UINT8 Reserved52[122];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -877,11 +881,11 @@ typedef struct { **/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x1200
+/** Offset 0x0FC8
**/
- UINT8 UnusedUpdSpace45[6];
+ UINT8 UnusedUpdSpace43[6];
-/** Offset 0x1206
+/** Offset 0x0FCE
**/
UINT16 UpdTerminator;
} FSPS_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 35cc43bcbb..909ba36708 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -1304,9 +1304,14 @@ typedef struct { **/ UINT8 IsTPMPresence; -/** Offset 0x0389 - Reserved +/** Offset 0x0389 - ConfigTdpLevel + Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ - UINT8 Reserved17[6]; + UINT8 ConfigTdpLevel; + +/** Offset 0x038A - Reserved +**/ + UINT8 Reserved17[5]; /** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. |