diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/mtcmos.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/addressmap.h | 9 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/infracfg.h | 291 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/smi.h | 118 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/spm.h | 508 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/mtcmos.c | 34 |
7 files changed, 960 insertions, 3 deletions
diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index e089fcc681..74bdda19ac 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -19,4 +19,6 @@ void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); +void mtcmos_protect_display_bus(void); + #endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */ diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 01d65171ca..74b0ae81b7 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -19,6 +19,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-y += ../common/wdt.c ramstage-y += ../common/cbmem.c emi.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += ../common/timer.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index bbb40943a1..a0d7f1c502 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -22,9 +22,12 @@ enum { }; enum { - RGU_BASE = IO_PHYS + 0x00007000, - GPT_BASE = IO_PHYS + 0x00008000, - UART0_BASE = IO_PHYS + 0x01002000, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + UART0_BASE = IO_PHYS + 0x01002000, + SMI_BASE = IO_PHYS + 0x04019000, }; #endif diff --git a/src/soc/mediatek/mt8183/include/soc/infracfg.h b/src/soc/mediatek/mt8183/include/soc/infracfg.h new file mode 100644 index 0000000000..922d977e2b --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/infracfg.h @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_INFRACFG_H +#define SOC_MEDIATEK_MT8183_INFRACFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_infracfg_regs { + u32 reserved1[20]; + u32 infra_globalcon_dcmctl; + u32 reserved2[7]; + u32 infra_bus_dcm_ctrl; + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u32 reserved3[1]; + u32 dramc_wbr; + u32 reserved4[2]; + u32 module_sw_cg_3_set; + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u32 reserved5[13]; + u32 i2c_dbtool_misc; + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u32 reserved6[5]; + u32 infra_globalcon_rst0_set; + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u32 reserved7[1]; + u32 infra_globalcon_rst1_set; + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u32 reserved8[1]; + u32 infra_globalcon_rst2_set; + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u32 reserved9[1]; + u32 infra_globalcon_rst3_set; + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u32 reserved10[41]; + u32 infra_topaxi_si0_ctl; + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u32 infra_axi_aslice_ctrl; + u32 infra_apb_async_sta; + u32 infra_topaxi_si2_ctl; + u32 reserved11[2]; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u32 reserved12[1]; + u32 infra_topaxi_aslice_ctrl; + u32 reserved13[3]; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 reserved14[1]; + u32 infra_topaxi_trans_limiter; + u32 infra_topaxi_emi_gmc_l2c_ctrl; + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_cbip_slice_ctrl_2; + u32 reserved15[3]; + u32 infra_topaxi_protecten_mcu; + u32 infra_topaxi_protecten_mcu_set; + u32 infra_topaxi_protecten_mcu_clr; + u32 reserved16[1]; + u32 infra_topaxi_protecten_mm; + u32 infra_topaxi_protecten_mm_set; + u32 infra_topaxi_protecten_mm_clr; + u32 reserved17[1]; + u32 infra_topaxi_protecten_mcu_sta0; + u32 infra_topaxi_protecten_mcu_sta1; + u32 infra_topaxi_protecten_mm_sta0; + u32 infra_topaxi_protecten_mm_sta1; + u32 reserved18[4]; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u32 reserved19[4]; + u32 md2_bank4_map0; + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u32 reserved20[1]; + u32 ap2md_dummy; + u32 reserved21[3]; + u32 conn_map0; + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 conn_map2; + u32 reserved22[26]; + u32 peri_cci_sideband_con; + u32 mfg_cci_sideband_con; + u32 reserved23[62]; + u32 infra_ao_dbg_con0; + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 infra_ao_dbg_sta; + u32 reserved24[58]; + u32 mfg_misc_con; + u32 reserved25[63]; + u32 infra_rsvd0; + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 reserved26[92]; + u32 md1_sbc_key0; + u32 md1_sbc_key1; + u32 md1_sbc_key2; + u32 md1_sbc_key3; + u32 md1_sbc_key4; + u32 md1_sbc_key5; + u32 md1_sbc_key6; + u32 md1_sbc_key7; + u32 md1_sbc_key_lock; + u32 reserved27[1]; + u32 md1_misc_lock; + u32 md1_misc; + u32 c2k_sbc_key0; + u32 c2k_sbc_key1; + u32 c2k_sbc_key2; + u32 c2k_sbc_key3; + u32 c2k_sbc_key4; + u32 c2k_sbc_key5; + u32 c2k_sbc_key6; + u32 c2k_sbc_key7; + u32 c2k_sbc_key_lock; + u32 reserved28[11]; + u32 infra_bonding; + u32 reserved29[63]; + u32 infra_ao_scpsys_apb_async_sta; + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 reserved30[59]; + u32 pll_ulposc_con0; + u32 pll_ulposc_con1; + u32 reserved31[2]; + u32 pll_auxadc_con0; + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u32 reserved32[56]; + u32 cldma_ctrl; + u32 reserved33[63]; + u32 infrabus_dbg0; + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 infrabus_dbg17; + u32 infrabus_dbg18; + u32 infrabus_dbg19; + u32 infrabus_dbg20; + u32 infrabus_dbg21; + u32 infrabus_dbg22; + u32 infrabus_dbg23; + u32 reserved34[104]; + u32 infra_misc; + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u32 reserved35[27]; + u32 infra_ao_sec_con; + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u32 reserved36[1]; + u32 infra_ao_sec_cg_con2; + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u32 reserved37[2]; + u32 infra_ao_sec_hyp; +}; + +check_member(mt8183_infracfg_regs, infra_globalcon_dcmctl, 0x0050); +check_member(mt8183_infracfg_regs, infra_bus_dcm_ctrl, 0x0070); +check_member(mt8183_infracfg_regs, module_sw_cg_3_set, 0x00c0); +check_member(mt8183_infracfg_regs, i2c_dbtool_misc, 0x0100); +check_member(mt8183_infracfg_regs, infra_globalcon_rst0_set, 0x0120); +check_member(mt8183_infracfg_regs, infra_topaxi_si0_ctl, 0x0200); +check_member(mt8183_infracfg_regs, infra_mci_trans_con_read, 0x0240); +check_member(mt8183_infracfg_regs, infra_topaxi_mi_ctrl, 0x0270); +check_member(mt8183_infracfg_regs, infra_topaxi_protecten_mcu, 0x02c0); +check_member(mt8183_infracfg_regs, md1_bank0_map0, 0x0300); +check_member(mt8183_infracfg_regs, md2_bank4_map0, 0x0350); +check_member(mt8183_infracfg_regs, conn_map0, 0x0380); +check_member(mt8183_infracfg_regs, peri_cci_sideband_con, 0x0400); +check_member(mt8183_infracfg_regs, infra_ao_dbg_con0, 0x0500); +check_member(mt8183_infracfg_regs, mfg_misc_con, 0x0600); +check_member(mt8183_infracfg_regs, infra_rsvd0, 0x0700); +check_member(mt8183_infracfg_regs, md1_sbc_key0, 0x0880); +check_member(mt8183_infracfg_regs, infra_bonding, 0x0900); +check_member(mt8183_infracfg_regs, infra_ao_scpsys_apb_async_sta, 0x0a00); +check_member(mt8183_infracfg_regs, pll_ulposc_con0, 0x0b00); +check_member(mt8183_infracfg_regs, pll_auxadc_con0, 0x0b10); +check_member(mt8183_infracfg_regs, cldma_ctrl, 0x0c00); +check_member(mt8183_infracfg_regs, infrabus_dbg0, 0x0d00); +check_member(mt8183_infracfg_regs, infra_misc, 0x0f00); +check_member(mt8183_infracfg_regs, infra_ao_sec_con, 0x0f80); +check_member(mt8183_infracfg_regs, infra_ao_sec_hyp, 0x0fb0); + +static struct mt8183_infracfg_regs *const mt8183_infracfg = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8183_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/smi.h b/src/soc/mediatek/mt8183/include/soc/smi.h new file mode 100644 index 0000000000..e9051c2f5e --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/smi.h @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SMI_H +#define SOC_MEDIATEK_MT8183_SMI_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_smi_regs { + u32 reserved1[64]; + u32 smi_l1len; + u32 smi_l1arb0; + u32 smi_l1arb1; + u32 smi_l1arb2; + u32 smi_l1arb3; + u32 smi_l1arb4; + u32 smi_l1arb5; + u32 smi_l1arb6; + u32 smi_l1arb7; + u32 reserved2[31]; + u32 smi_mon_axi_ena; + u32 smi_mon_axi_clr; + u32 reserved3[1]; + u32 smi_mon_axi_type; + u32 smi_mon_axi_con; + u32 reserved4[3]; + u32 smi_mon_axi_act_cnt; + u32 smi_mon_axi_req_cnt; + u32 smi_mon_axi_ostd_cnt; + u32 smi_mon_axi_bea_cnt; + u32 smi_mon_axi_byt_cnt; + u32 smi_mon_axi_cp_cnt; + u32 smi_mon_axi_dp_cnt; + u32 smi_mon_axi_cp_max; + u32 smi_mon_axi_cos_max; + u32 reserved5[15]; + u32 smi_bus_sel; + u32 reserved6[1]; + u32 smi_wrr_reg0; + u32 smi_wrr_reg1; + u32 smi_read_fifo_th; + u32 smi_m4u_th; + u32 smi_fifo_th1; + u32 smi_fifo_th2; + u32 smi_preultra_mask0; + u32 smi_preultra_mask1; + u32 reserved7[46]; + u32 smi_dcm; + u32 smi_ela; + u32 smi_m1_rultra_wrr0; + u32 smi_m1_rultra_wrr1; + u32 smi_m1_wultra_wrr0; + u32 smi_m1_wultra_wrr1; + u32 smi_m2_rultra_wrr0; + u32 smi_m2_rultra_wrr1; + u32 smi_m2_wultra_wrr0; + u32 smi_m2_wultra_wrr1; + u32 reserved8[38]; + u32 smi_common_clamp_en; + u32 smi_common_clamp_en_set; + u32 smi_common_clamp_en_clr; + u32 reserved9[13]; + u32 smi_debug_s0; + u32 smi_debug_s1; + u32 smi_debug_s2; + u32 smi_debug_s3; + u32 smi_debug_s4; + u32 smi_debug_s5; + u32 smi_debug_s6; + u32 smi_debug_s7; + u32 reserved10[4]; + u32 smi_debug_m0; + u32 smi_debug_m1; + u32 reserved11[2]; + u32 smi_debug_misc; + u32 smi_dummy; + u32 reserved12[46]; + u32 smi_hist_rec0; + u32 smi_hist_rec_data0; + u32 smi_hist_rec_data1; + u32 smi_hist_rec_data2; + u32 smi_hist_rec_data3; + u32 smi_hist_rec_data4; + u32 smi_hist_rec_data5; + u32 smi_hist_rec_data6; + u32 smi_hist_rec_data7; + u32 smi_hist_rec_data8; + u32 smi_hist_rec_data9; +}; + +check_member(mt8183_smi_regs, smi_l1len, 0x0100); +check_member(mt8183_smi_regs, smi_mon_axi_ena, 0x01a0); +check_member(mt8183_smi_regs, smi_mon_axi_act_cnt, 0x01c0); +check_member(mt8183_smi_regs, smi_bus_sel, 0x0220); +check_member(mt8183_smi_regs, smi_dcm, 0x0300); +check_member(mt8183_smi_regs, smi_common_clamp_en, 0x03c0); +check_member(mt8183_smi_regs, smi_debug_s0, 0x0400); +check_member(mt8183_smi_regs, smi_debug_m0, 0x0430); +check_member(mt8183_smi_regs, smi_debug_misc, 0x0440); +check_member(mt8183_smi_regs, smi_hist_rec0, 0x0500); +check_member(mt8183_smi_regs, smi_hist_rec_data9, 0x0528); + +static struct mt8183_smi_regs *const mt8183_smi = (void *)SMI_BASE; + +#endif /* SOC_MEDIATEK_MT8183_SMI_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h new file mode 100644 index 0000000000..5e7770eecb --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -0,0 +1,508 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SPM_H +#define SOC_MEDIATEK_MT8183_SPM_H + +#include <soc/addressmap.h> +#include <types.h> + +enum { + SPM_PROJECT_CODE = 0xb16 +}; + +enum { + DISP_SRAM_PDN_MASK = 0x1 << 8, + DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_SRAM_PDN_MASK = 0xf << 8, + AUDIO_SRAM_ACK_MASK = 0xf << 12, +}; + +struct mtk_spm_regs { + u32 poweron_config_set; + u32 spm_power_on_val0; + u32 spm_power_on_val1; + u32 spm_clk_con; + u32 spm_clk_settle; + u32 spm_ap_standby_con; + u32 pcm_con0; + u32 pcm_con1; + u32 pcm_im_ptr; + u32 pcm_im_len; + u32 pcm_reg_data_ini; + u32 pcm_pwr_io_en; + u32 pcm_timer_val; + u32 pcm_wdt_val; + u32 pcm_im_host_rw_ptr; + u32 pcm_im_host_rw_dat; + u32 pcm_event_vector0; + u32 pcm_event_vector1; + u32 pcm_event_vector2; + u32 pcm_event_vector3; + u32 pcm_event_vector4; + u32 pcm_event_vector5; + u32 pcm_event_vector6; + u32 pcm_event_vector7; + u32 pcm_event_vector8; + u32 pcm_event_vector9; + u32 pcm_event_vector10; + u32 pcm_event_vector11; + u32 pcm_event_vector12; + u32 pcm_event_vector13; + u32 pcm_event_vector14; + u32 pcm_event_vector15; + u32 pcm_event_vector_en; + u32 reserved1[1]; + u32 spm_sram_rsv_con; + u32 spm_swint; + u32 spm_swint_set; + u32 spm_swint_clr; + u32 spm_scp_mailbox; + u32 scp_spm_mailbox; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_scp_irq; + u32 spm_cpu_wakeup_event; + u32 spm_irq_mask; + u32 spm_src_req; + u32 spm_src_mask; + u32 spm_src2_mask; + u32 spm_wakeup_event_mask; + u32 spm_wakeup_event_ext_mask; + u32 spm_twam_event_clear; + u32 scp_clk_con; + u32 pcm_debug_con; + u32 ddr_en_dbc_len; + u32 ahb_bus_con; + u32 spm_src3_mask; + u32 ddr_en_emi_dbc_con; + u32 md32_clk_con; + u32 reserved2[5]; + u32 pcm_reg0_data; + u32 pcm_reg1_data; + u32 pcm_reg2_data; + u32 pcm_reg3_data; + u32 pcm_reg4_data; + u32 pcm_reg5_data; + u32 pcm_reg6_data; + u32 pcm_reg7_data; + u32 pcm_reg8_data; + u32 pcm_reg9_data; + u32 pcm_reg10_data; + u32 pcm_reg11_data; + u32 pcm_reg12_data; + u32 pcm_reg13_data; + u32 pcm_reg14_data; + u32 pcm_reg15_data; + u32 pcm_reg12_mask_b_sta; + u32 pcm_reg12_ext_data; + u32 pcm_reg12_ext_mask_b_sta; + u32 pcm_event_reg_sta; + u32 pcm_timer_out; + u32 pcm_wdt_out; + u32 spm_irq_sta; + u32 spm_wakeup_sta; + u32 spm_wakeup_ext_sta; + u32 spm_wakeup_misc; + u32 bus_protect_rdy; + u32 bus_protect2_rdy; + u32 subsys_idle_sta; + u32 cpu_idle_sta; + u32 pcm_fsm_sta; + u32 src_req_sta; + u32 pwr_status; + u32 pwr_status_2nd; + u32 cpu_pwr_status; + u32 cpu_pwr_status_2nd; + u32 misc_sta; + u32 spm_src_rdy_sta; + u32 reserved3[1]; + u32 dramc_dbg_latch; + u32 spm_twam_last_sta0; + u32 spm_twam_last_sta1; + u32 spm_twam_last_sta2; + u32 spm_twam_last_sta3; + u32 spm_twam_curr_sta0; + u32 spm_twam_curr_sta1; + u32 spm_twam_curr_sta2; + u32 spm_twam_curr_sta3; + u32 spm_twam_timer_out; + u32 reserved4[1]; + u32 spm_dvfs_sta; + u32 bus_protect3_rdy; + u32 reserved5[4]; + u32 src_ddren_sta; + u32 reserved6[7]; + u32 mcu_pwr_con; + u32 mp0_cputop_pwr_con; + u32 mp0_cpu0_pwr_con; + u32 mp0_cpu1_pwr_con; + u32 mp0_cpu2_pwr_con; + u32 mp0_cpu3_pwr_con; + u32 mp1_cputop_pwr_con; + u32 mp1_cpu0_pwr_con; + u32 mp1_cpu1_pwr_con; + u32 mp1_cpu2_pwr_con; + u32 mp1_cpu3_pwr_con; + u32 reserved7[5]; + u32 mp0_cputop_l2_pdn; + u32 mp0_cputop_l2_sleep_b; + u32 mp0_cpu0_l1_pdn; + u32 mp0_cpu1_l1_pdn; + u32 mp0_cpu2_l1_pdn; + u32 mp0_cpu3_l1_pdn; + u32 mp1_cputop_l2_pdn; + u32 mp1_cputop_l2_sleep_b; + u32 mp1_cpu0_l1_pdn; + u32 mp1_cpu1_l1_pdn; + u32 mp1_cpu2_l1_pdn; + u32 mp1_cpu3_l1_pdn; + u32 reserved8[8]; + u32 cpu_ext_buck_iso; + u32 reserved9[7]; + u32 dummy1_pwr_con; + u32 bypass_spmc; + u32 spmc_dormant_enable; + u32 armpll_clk_con; + u32 spmc_in_ret; + u32 reserved10[15]; + u32 vde_pwr_con; + u32 ven_pwr_con; + u32 isp_pwr_con; + u32 dis_pwr_con; + u32 mfg_core1_pwr_con; + u32 audio_pwr_con; + u32 ifr_pwr_con; + u32 dpy_pwr_con; + u32 md1_pwr_con; + u32 vpu_top_pwr_con; + u32 reserved11[1]; + u32 conn_pwr_con; + u32 vpu_core2_pwr_con; + u32 mfg_async_pwr_con; + u32 mfg_pwr_con; + u32 vpu_core0_pwr_con; + u32 vpu_core1_pwr_con; + u32 cam_pwr_con; + u32 mfg_2d_pwr_con; + u32 mfg_core0_pwr_con; + u32 sysram_con; + u32 sysrom_con; + u32 sspm_sram_con; + u32 scp_sram_con; + u32 reserved12[3]; + u32 ufs_sram_con; + u32 reserved13[4]; + u32 dummy_sram_con; + u32 reserved14[3]; + u32 md_ext_buck_iso_con; + u32 md_sram_iso_con; + u32 md_extra_pwr_con; + u32 reserved15[1]; + u32 ext_buck_con; + u32 reserved16[11]; + u32 mbist_efuse_repair_ack_sta; + u32 reserved17[11]; + u32 spm_dvfs_con; + u32 spm_mdbsi_con; + u32 spm_mas_pause_mask_b; + u32 spm_mas_pause2_mask_b; + u32 spm_bsi_gen; + u32 spm_bsi_en_sr; + u32 spm_bsi_clk_sr; + u32 spm_bsi_d0_sr; + u32 spm_bsi_d1_sr; + u32 spm_bsi_d2_sr; + u32 spm_ap_sema; + u32 spm_spm_sema; + u32 ap_mdsrc_req; + u32 reserved18[1]; + u32 spm2md_dvfs_con; + u32 md2spm_dvfs_con; + u32 dramc_dpy_clk_sw_con_rsv; + u32 dpy_lp_con; + u32 cpu_dvfs_req; + u32 spm_pll_con; + u32 spm_emi_bw_mode; + u32 ap2md_peer_wakeup; + u32 ulposc_con; + u32 spm2mm_con; + u32 dramc_dpy_clk_sw_con_sel; + u32 dramc_dpy_clk_sw_con; + u32 spm_s1_mode_ch; + u32 emi_self_refresh_ch_sta; + u32 dramc_dpy_clk_sw_con_sel2; + u32 dramc_dpy_clk_sw_con2; + u32 dramc_dmyrd_con; + u32 spm_drs_con; + u32 spm_sema_m0; + u32 spm_sema_m1; + u32 spm_sema_m2; + u32 spm_sema_m3; + u32 spm_sema_m4; + u32 spm_sema_m5; + u32 spm_sema_m6; + u32 spm_sema_m7; + u32 spm_mas_pause_mm_mask_b; + u32 spm_mas_pause_mcu_mask_b; + u32 reserved19[1]; + u32 sram_dreq_ack; + u32 sram_dreq_con; + u32 sram_dreq_con_set; + u32 sram_dreq_con_clr; + u32 spm2emi_enter_ulpm; + u32 spm_md32_irq; + u32 spm2pmcu_int; + u32 spm2pmcu_int_set; + u32 spm2pmcu_int_clr; + u32 spm2pmcu_mailbox_0; + u32 spm2pmcu_mailbox_1; + u32 spm2pmcu_mailbox_2; + u32 spm2pmcu_mailbox_3; + u32 pmcu2spm_int; + u32 pmcu2spm_int_set; + u32 pmcu2spm_int_clr; + u32 pmcu2spm_mailbox_0; + u32 pmcu2spm_mailbox_1; + u32 pmcu2spm_mailbox_2; + u32 pmcu2spm_mailbox_3; + u32 pmcu2spm_cfg; + u32 mp0_cpu0_irq_mask; + u32 mp0_cpu1_irq_mask; + u32 mp0_cpu2_irq_mask; + u32 mp0_cpu3_irq_mask; + u32 mp1_cpu0_irq_mask; + u32 mp1_cpu1_irq_mask; + u32 mp1_cpu2_irq_mask; + u32 mp1_cpu3_irq_mask; + u32 reserved20[4]; + u32 mp0_cpu0_wfi_en; + u32 mp0_cpu1_wfi_en; + u32 mp0_cpu2_wfi_en; + u32 mp0_cpu3_wfi_en; + u32 mp1_cpu0_wfi_en; + u32 mp1_cpu1_wfi_en; + u32 mp1_cpu2_wfi_en; + u32 mp1_cpu3_wfi_en; + u32 reserved21[1]; + u32 mp0_l2cflush; + u32 mp1_l2cflush; + u32 reserved22[1]; + u32 cpu_ptpod2_con; + u32 reserved23[3]; + u32 root_cputop_addr; + u32 root_core_addr; + u32 reserved24[2]; + u32 cpu_spare_con; + u32 cpu_spare_con_set; + u32 cpu_spare_con_clr; + u32 reserved25[17]; + u32 spm2sw_mailbox_0; + u32 spm2sw_mailbox_1; + u32 spm2sw_mailbox_2; + u32 spm2sw_mailbox_3; + u32 sw2spm_int; + u32 sw2spm_int_set; + u32 sw2spm_int_clr; + u32 sw2spm_mailbox_0; + u32 sw2spm_mailbox_1; + u32 sw2spm_mailbox_2; + u32 sw2spm_mailbox_3; + u32 sw2spm_cfg; + u32 spm_sw_flag; + u32 spm_sw_debug; + u32 spm_sw_rsv_0; + u32 spm_sw_rsv_1; + u32 spm_sw_rsv_2; + u32 spm_sw_rsv_3; + u32 spm_sw_rsv_4; + u32 spm_sw_rsv_5; + u32 spm_rsv_con; + u32 spm_rsv_sta; + u32 spm_rsv_con1; + u32 spm_rsv_sta1; + u32 spm_pasr_dpd_0; + u32 spm_pasr_dpd_1; + u32 spm_pasr_dpd_2; + u32 spm_pasr_dpd_3; + u32 spm_spare_con; + u32 spm_spare_con_set; + u32 spm_spare_con_clr; + u32 spm_sw_rsv_6; + u32 spm_sw_rsv_7; + u32 spm_sw_rsv_8; + u32 spm_sw_rsv_9; + u32 spm_sw_rsv_10; + u32 reserved26[7]; + u32 spm_sw_rsv_18; + u32 spm_sw_rsv_19; + u32 reserved27[3]; + u32 dvfsrc_event_mask_con; + u32 dvfsrc_event_force_on; + u32 dvfsrc_event_sel; + u32 spm_dvfs_event_sta; + u32 spm_dvfs_event_sta1; + u32 spm_dvfs_level; + u32 dvfs_abort_sta; + u32 dvfs_abort_others_mask; + u32 spm_dfs_level; + u32 spm_dvs_level; + u32 spm_dvfs_misc; + u32 reserved28[1]; + u32 spare_src_req_mask; + u32 scp_vcore_level; + u32 sc_mm_ck_sel_con; + u32 reserved29[9]; + u32 spare_ack_sta; + u32 spare_ack_mask; + u32 reserved30[2]; + u32 spm_dvfs_con1; + u32 spm_dvfs_con1_sta; + u32 reserved31[2]; + u32 spm_dvfs_cmd0; + u32 spm_dvfs_cmd1; + u32 spm_dvfs_cmd2; + u32 spm_dvfs_cmd3; + u32 spm_dvfs_cmd4; + u32 spm_dvfs_cmd5; + u32 spm_dvfs_cmd6; + u32 spm_dvfs_cmd7; + u32 spm_dvfs_cmd8; + u32 spm_dvfs_cmd9; + u32 spm_dvfs_cmd10; + u32 spm_dvfs_cmd11; + u32 spm_dvfs_cmd12; + u32 spm_dvfs_cmd13; + u32 spm_dvfs_cmd14; + u32 spm_dvfs_cmd15; + u32 reserved32[12]; + u32 wdt_latch_spare0_fix; + u32 wdt_latch_spare1_fix; + u32 wdt_latch_spare2_fix; + u32 wdt_latch_spare3_fix; + u32 spare_ack_in_fix; + u32 dcha_latch_rsv0_fix; + u32 dchb_latch_rsv0_fix; + u32 reserved33[25]; + u32 pcm_wdt_latch_0; + u32 pcm_wdt_latch_1; + u32 pcm_wdt_latch_2; + u32 pcm_wdt_latch_3; + u32 pcm_wdt_latch_4; + u32 pcm_wdt_latch_5; + u32 pcm_wdt_latch_6; + u32 pcm_wdt_latch_7; + u32 pcm_wdt_latch_8; + u32 pcm_wdt_latch_9; + u32 wdt_latch_spare0; + u32 wdt_latch_spare1; + u32 wdt_latch_spare2; + u32 wdt_latch_spare3; + u32 pcm_wdt_latch_10; + u32 pcm_wdt_latch_11; + u32 dcha_gating_latch_0; + u32 dcha_gating_latch_1; + u32 dcha_gating_latch_2; + u32 dcha_gating_latch_3; + u32 dcha_gating_latch_4; + u32 dcha_gating_latch_5; + u32 dcha_gating_latch_6; + u32 dcha_gating_latch_7; + u32 dchb_gating_latch_0; + u32 dchb_gating_latch_1; + u32 dchb_gating_latch_2; + u32 dchb_gating_latch_3; + u32 dchb_gating_latch_4; + u32 dchb_gating_latch_5; + u32 dchb_gating_latch_6; + u32 dchb_gating_latch_7; + u32 dcha_latch_rsv0; + u32 dchb_latch_rsv0; + u32 pcm_wdt_latch_12; + u32 pcm_wdt_latch_13; + u32 reserved34[12]; + u32 spm_pc_trace_con; + u32 spm_pc_trace_g0; + u32 spm_pc_trace_g1; + u32 spm_pc_trace_g2; + u32 spm_pc_trace_g3; + u32 spm_pc_trace_g4; + u32 spm_pc_trace_g5; + u32 spm_pc_trace_g6; + u32 spm_pc_trace_g7; + u32 reserved35[7]; + u32 spm_ack_chk_con; + u32 spm_ack_chk_pc; + u32 spm_ack_chk_sel; + u32 spm_ack_chk_timer; + u32 spm_ack_chk_sta; + u32 spm_ack_chk_latch; + u32 reserved36[2]; + u32 spm_ack_chk_con2; + u32 spm_ack_chk_pc2; + u32 spm_ack_chk_sel2; + u32 spm_ack_chk_timer2; + u32 spm_ack_chk_sta2; + u32 spm_ack_chk_latch2; + u32 reserved37[2]; + u32 spm_ack_chk_con3; + u32 spm_ack_chk_pc3; + u32 spm_ack_chk_sel3; + u32 spm_ack_chk_timer3; + u32 spm_ack_chk_sta3; + u32 spm_ack_chk_latch3; + u32 reserved38[2]; + u32 spm_ack_chk_con4; + u32 spm_ack_chk_pc4; + u32 spm_ack_chk_sel4; + u32 spm_ack_chk_timer4; + u32 spm_ack_chk_sta4; + u32 spm_ack_chk_latch4; +}; + +check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); +check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); +check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); +check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); +check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); +check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); +check_member(mtk_spm_regs, vde_pwr_con, 0x0300); +check_member(mtk_spm_regs, ufs_sram_con, 0x036c); +check_member(mtk_spm_regs, dummy_sram_con, 0x0380); +check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); +check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); +check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); +check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); +check_member(mtk_spm_regs, root_cputop_addr, 0x0570); +check_member(mtk_spm_regs, cpu_spare_con, 0x0580); +check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); +check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); +check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); +check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); +check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); +check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); +check_member(mtk_spm_regs, wdt_latch_spare0_fix, 0x0780); +check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x0800); +check_member(mtk_spm_regs, spm_pc_trace_con, 0x08c0); +check_member(mtk_spm_regs, spm_ack_chk_con, 0x0900); +check_member(mtk_spm_regs, spm_ack_chk_con2, 0x0920); +check_member(mtk_spm_regs, spm_ack_chk_con3, 0x0940); +check_member(mtk_spm_regs, spm_ack_chk_con4, 0x0960); +check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +#endif /* SOC_MEDIATEK_MT8183_SPM_H */ diff --git a/src/soc/mediatek/mt8183/mtcmos.c b/src/soc/mediatek/mt8183/mtcmos.c new file mode 100644 index 0000000000..1c0d7aba7d --- /dev/null +++ b/src/soc/mediatek/mt8183/mtcmos.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/infracfg.h> +#include <soc/smi.h> +#include <soc/mtcmos.h> + +enum { + DISP_PROT_STEP1_0_MASK = 0x3 << 16, + DISP_PROT_STEP2_0_MASK = 0x3 << 10, + DISP_PROT_STEP2_1_MASK = 0xff, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8183_infracfg->infra_topaxi_protecten_clr, + DISP_PROT_STEP2_0_MASK); + write32(&mt8183_smi->smi_common_clamp_en_clr, DISP_PROT_STEP2_1_MASK); + write32(&mt8183_infracfg->infra_topaxi_protecten_1_clr, + DISP_PROT_STEP1_0_MASK); +} |