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-rw-r--r--src/soc/intel/alderlake/espi.c15
-rw-r--r--src/soc/intel/apollolake/lpc.c19
-rw-r--r--src/soc/intel/cannonlake/lpc.c15
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpc_lib.h9
-rw-r--r--src/soc/intel/common/block/lpc/lpc.c8
-rw-r--r--src/soc/intel/common/block/lpc/lpc_lib.c22
-rw-r--r--src/soc/intel/elkhartlake/espi.c14
-rw-r--r--src/soc/intel/icelake/espi.c15
-rw-r--r--src/soc/intel/jasperlake/espi.c15
-rw-r--r--src/soc/intel/skylake/lpc.c14
-rw-r--r--src/soc/intel/tigerlake/espi.c15
-rw-r--r--src/soc/intel/xeon_sp/lpc.c9
12 files changed, 0 insertions, 170 deletions
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
index b2377274e5..b489ef6a15 100644
--- a/src/soc/intel/alderlake/espi.c
+++ b/src/soc/intel/alderlake/espi.c
@@ -20,21 +20,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index ad9211b9c2..e37ab2070f 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -8,25 +8,6 @@
#include <soc/pm.h>
#include "chip.h"
-static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {
- { 0xfed40000, 0x8000 },
- { 0xfedc0000, 0x4000 },
- { 0xfed20800, 16 },
- { 0xfed20880, 8 },
- { 0xfed208e0, 16 },
- { 0xfed208f0, 8 },
- { 0xfed30800, 16 },
- { 0xfed30880, 8 },
- { 0xfed308e0, 16 },
- { 0xfed308f0, 8 },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
-{
- return apl_lpc_fixed_mmio_ranges;
-}
-
static const struct pad_config lpc_gpios[] = {
#if CONFIG(SOC_INTEL_GEMINILAKE)
#if !CONFIG(SOC_ESPI)
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c8e35c4d55..26bda70845 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -18,21 +18,6 @@
#include "chip.h"
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return cnl_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 82cba8ec7f..542281ed43 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -45,11 +45,6 @@ enum serirq_mode {
SERIRQ_OFF,
};
-struct lpc_mmio_range {
- uintptr_t base;
- size_t size;
-};
-
/*
* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together.
* Output:I/O Enable Bits
@@ -65,8 +60,6 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size);
void lpc_close_pmio_windows(void);
/* Open a generic MMIO window to the LPC bus. One window is available. */
void lpc_open_mmio_window(uintptr_t base, size_t size);
-/* Returns true if given window is decoded to LPC via a fixed range. */
-bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
/* Init SoC Specific LPC features. Common definition will be weak and
each soc will need to define the init. */
void lpc_soc_init(struct device *dev);
@@ -74,8 +67,6 @@ void lpc_soc_init(struct device *dev);
void pch_lpc_soc_fill_io_resources(struct device *dev);
/* Init LPC GPIO pads */
void lpc_configure_pads(void);
-/* Get SoC specific MMIO ranges */
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);
/* Set LPC BIOS Control BILD bit. */
void lpc_set_bios_interface_lock_down(void);
/* Set LPC BIOS Control LE bit. */
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index e754237ffa..0bffaf62e6 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -59,14 +59,6 @@ static void pch_lpc_loop_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_IO)
lpc_open_pmio_window(res->base, res->size);
-
- if (res->flags & IORESOURCE_MEM) {
- /* Check if this is already decoded. */
- if (lpc_fits_fixed_mmio_window(res->base, res->size))
- continue;
-
- lpc_open_mmio_window(res->base, res->size);
- }
}
pch_lpc_set_child_resources(dev);
}
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index d050ee36e5..6c300a2d52 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -148,28 +148,6 @@ void lpc_open_mmio_window(uintptr_t base, size_t size)
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
}
-bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)
-{
- resource_t res_end, range_end;
- const struct lpc_mmio_range *range;
- const struct lpc_mmio_range *lpc_fixed_mmio_ranges =
- soc_get_fixed_mmio_ranges();
-
- for (range = lpc_fixed_mmio_ranges; range->size; range++) {
- range_end = range->base + range->size;
- res_end = base + size;
-
- if ((base >= range->base) && (res_end <= range_end)) {
- printk(BIOS_DEBUG,
- "Resource %lx size %zx fits in fixed window"
- " %lx size %zx\n",
- base, size, range->base, range->size);
- return true;
- }
- }
- return false;
-}
-
/*
* Set FAST_SPIBAR BIOS Control register based on input bit field.
*/
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
index 8f82755e55..f33eca52c6 100644
--- a/src/soc/intel/elkhartlake/espi.c
+++ b/src/soc/intel/elkhartlake/espi.c
@@ -17,20 +17,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
-/*
-* To reserve certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return ehl_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
index 4107d7e274..d2de406c60 100644
--- a/src/soc/intel/icelake/espi.c
+++ b/src/soc/intel/icelake/espi.c
@@ -17,21 +17,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return icl_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index 11299a9552..3911c81c3d 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -17,21 +17,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return jsl_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index b83fadd223..6a22af8216 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -15,20 +15,6 @@
#include "chip.h"
-/**
- PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF
-**/
-
-static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
-{
- return skl_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index 8602b0dc59..34847e8b78 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -23,21 +23,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return tgl_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index dee99b70ac..268db92f9a 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -9,15 +9,6 @@
#include <chip.h>
-static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
-{
- return xeon_lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 08:00:35 +0000