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-rw-r--r--src/mainboard/google/myst/mainboard.c40
1 files changed, 39 insertions, 1 deletions
diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c
index e433c98035..3a25e8c834 100644
--- a/src/mainboard/google/myst/mainboard.c
+++ b/src/mainboard/google/myst/mainboard.c
@@ -5,10 +5,48 @@
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/device.h>
+#include <soc/acpi.h>
#include <variant/ec.h>
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ * 0: timer < soc/amd/common/acpi/lpc.asl
+ * 1: i8042 - Keyboard
+ * 2: cascade
+ * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ * 9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+
static const struct fch_irq_routing fch_irq_map[] = {
- { 0, 0x00, 0x00 },
+ { PIRQ_A, 12, PIRQ_NC },
+ { PIRQ_B, 14, PIRQ_NC },
+ { PIRQ_C, 15, PIRQ_NC },
+ { PIRQ_D, 12, PIRQ_NC },
+ { PIRQ_E, 14, PIRQ_NC },
+ { PIRQ_F, 15, PIRQ_NC },
+ { PIRQ_G, 12, PIRQ_NC },
+ { PIRQ_H, 14, PIRQ_NC },
+
+ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
+ { PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
+ { PIRQ_GPIO, 11, 11 },
+ { PIRQ_I2C0, 10, 10 },
+ { PIRQ_I2C1, 7, 7 },
+ { PIRQ_I2C2, 6, 6 },
+ { PIRQ_I2C3, 5, 5 },
+ { PIRQ_UART0, 4, 4 },
+ { PIRQ_UART1, 3, 3 },
+
+ /* The MISC registers are not interrupt numbers */
+ { PIRQ_MISC, 0xfa, 0x00 },
+ { PIRQ_MISC0, 0x91, 0x00 },
+ { PIRQ_HPET_L, 0x00, 0x00 },
+ { PIRQ_HPET_H, 0x00, 0x00 },
};
const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)