summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/pujjo/overridetree.cb20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
index 647bcbfc30..5c4709f2d9 100644
--- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/alderlake
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC Camera
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
# Configure external V1P05/Vnn/VnnSx Rails
@@ -228,6 +229,18 @@ chip soc/intel/alderlake
device i2c 0x2c on end
end
end
+ device ref pcie_rp4 on
+ # PCIe 4 WLAN
+ register "pch_pcie_rp[PCH_RP(4)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_DW1_03"
+ device pci 00.0 on end
+ end
+ end
device ref pcie_rp7 on
# Enable SD Card PCIe 7 using clk 3
register "pch_pcie_rp[PCH_RP(7)]" = "{
@@ -316,6 +329,13 @@ chip soc/intel/alderlake
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port8 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""CNVi Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi