diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cache.h | 4 | ||||
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/cache.h | 4 | ||||
| -rw-r--r-- | src/device/dram/ddr3.c | 4 | ||||
| -rw-r--r-- | src/lib/device_tree.c | 8 | ||||
| -rw-r--r-- | src/mainboard/amd/inagua/buildOpts.c | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/parmer/buildOpts.c | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t400/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7721/buildOpts.c | 4 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/smi.c | 2 |
10 files changed, 20 insertions, 20 deletions
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index dd271c5bce..9a8021761e 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -48,8 +48,8 @@ #define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ #define SCTLR_Z (1 << 11) /* Branch prediction enable */ #define SCTLR_I (1 << 12) /* Instruction cache enable */ -#define SCTLR_V (1 << 13) /* Low/high exception vectors */ -#define SCTLR_RR (1 << 14) /* Round Robin select */ +#define SCTLR_V (1 << 13) /* Low/high exception vectors */ +#define SCTLR_RR (1 << 14) /* Round Robin select */ /* Bits 16:15 are reserved */ #define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ /* Bit 18 is reserved */ diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index b31c3b0153..8e133efcff 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -48,8 +48,8 @@ #define SCTLR_EL1_UMA (1 << 9) /* User mask access */ #define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */ #define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */ -#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */ -#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */ +#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */ +#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */ #define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */ #define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */ diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 535b48a707..a084ca06e0 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -115,7 +115,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len) * array, and passed to this function. * * @param dimm pointer to @ref dimm_attr structure where the decoded data is to - * be stored + * be stored * @param spd array of raw data previously read from the SPD. * * @return @ref spd_status enumerator @@ -123,7 +123,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len) * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD * SPD_STATUS_CRC_ERROR -- CRC did not verify * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was - * detected. + * detected. */ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) { diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 21916598c5..3d44f39375 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -497,12 +497,12 @@ void dt_read_cell_props(struct device_tree_node *node, u32 *addrcp, u32 *sizecp) * * @param parent The node from which to start the relative path lookup. * @param path An array of path component strings that will be looked - * up in order to find the node. Must be terminated with - * a NULL pointer. Example: {'firmware', 'coreboot', NULL} + * up in order to find the node. Must be terminated with + * a NULL pointer. Example: {'firmware', 'coreboot', NULL} * @param addrcp Pointer that will be updated with any #address-cells - * value found in the path. May be NULL to ignore. + * value found in the path. May be NULL to ignore. * @param sizecp Pointer that will be updated with any #size-cells - * value found in the path. May be NULL to ignore. + * value found in the path. May be NULL to ignore. * @param create 1: Create node(s) if not found. 0: Return NULL instead. * @return The found/created node, or NULL. */ diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index ff947a056b..1727e15cf9 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -36,7 +36,7 @@ /* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE #define INSTALL_S1G4_SOCKET_SUPPORT FALSE #define INSTALL_ASB2_SOCKET_SUPPORT FALSE @@ -53,7 +53,7 @@ */ #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index af2046d81c..c55cf2cb3b 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -155,8 +155,8 @@ #if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 0c72c86ed5..59458690a9 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -237,7 +237,7 @@ chip northbridge/intel/gm45 device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index adcb41797e..f160745fcd 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -170,8 +170,8 @@ #if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 093cad6e01..7ea89b8747 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -74,8 +74,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 9f6badb224..10e2fa627b 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -325,7 +325,7 @@ void southbridge_clear_smi_status(void) reset_pm1_status(); /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); + smi_set_eos(); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |