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-rw-r--r--src/soc/intel/pantherlake/Kconfig1
-rw-r--r--src/soc/intel/pantherlake/cpu.c13
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 96324b7c09..4098757490 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -368,6 +368,7 @@ config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET
config DROP_CPU_FEATURE_PROGRAM_IN_FSP
bool
+ default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS
default n
help
This is to avoid FSP running basic CPU feature programming on BSP
diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c
index 659ba0cf12..28fa1d890f 100644
--- a/src/soc/intel/pantherlake/cpu.c
+++ b/src/soc/intel/pantherlake/cpu.c
@@ -138,7 +138,18 @@ void soc_core_init(struct device *cpu)
if (CONFIG(INTEL_TME) && is_tme_supported())
set_tme_core_activate();
- /* TODO: Add support for DROP_CPU_FEATURE_PROGRAM_IN_FSP */
+ if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) {
+ /* Disable 3-strike error */
+ disable_signaling_three_strike_event();
+
+ set_aesni_lock();
+
+ /* Enable VMX */
+ set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx);
+
+ /* Feature control lock configure */
+ set_feature_ctrl_lock();
+ }
}
static void per_cpu_smm_trigger(void)