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-rw-r--r--src/mainboard/asrock/b85m_pro4/romstage.c4
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c4
-rw-r--r--src/mainboard/google/beltino/romstage.c4
-rw-r--r--src/mainboard/google/slippy/variants/falco/romstage.c4
-rw-r--r--src/mainboard/google/slippy/variants/leon/romstage.c4
-rw-r--r--src/mainboard/google/slippy/variants/peppy/romstage.c4
-rw-r--r--src/mainboard/google/slippy/variants/wolf/romstage.c4
-rw-r--r--src/mainboard/hp/folio_9480m/romstage.c4
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c4
-rw-r--r--src/mainboard/lenovo/t440p/romstage.c4
-rw-r--r--src/mainboard/msi/h81m-p33/romstage.c4
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c4
-rw-r--r--src/northbridge/intel/haswell/pei_data.h26
-rw-r--r--src/northbridge/intel/haswell/raminit.c41
-rw-r--r--src/northbridge/intel/haswell/raminit.h37
15 files changed, 109 insertions, 43 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 793a7d7b30..75efb9e69c 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -25,7 +25,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[3] = 0x53;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -43,7 +43,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index faac6809e3..cc9a04fad6 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -23,7 +23,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -41,7 +41,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 },
{ 1, 0 },
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 9904d5a9b9..a818d87f1c 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -46,7 +46,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */
USB_PORT_MINI_PCIE },
@@ -66,7 +66,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; CN22 */
{ 1, 1 }, /* P2; CN23 */
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index e808182274..9ab76292fb 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -25,7 +25,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
}
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: Port A, CN8 */
USB_PORT_BACK_PANEL },
@@ -45,7 +45,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_INTERNAL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN8 */
{ 1, 0 }, /* P2; Port B, CN9 */
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index c22e25b897..6911c257b0 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -19,7 +19,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
return !(spd_index & 0x4);
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
USB_PORT_BACK_PANEL },
@@ -39,7 +39,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN11 */
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index dd998f00f3..efbbc7f8c7 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -32,7 +32,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
}
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
USB_PORT_MINI_PCIE },
@@ -52,7 +52,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN6 */
{ 0, USB_OC_PIN_SKIP }, /* P2; */
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 95a14a08aa..4c67afefcf 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -25,7 +25,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
}
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
USB_PORT_BACK_PANEL },
@@ -45,7 +45,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN11 */
diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c
index 865fcc6617..f1df3ef1c0 100644
--- a/src/mainboard/hp/folio_9480m/romstage.c
+++ b/src/mainboard/hp/folio_9480m/romstage.c
@@ -23,7 +23,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
@@ -35,7 +35,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, USB_OC_PIN_SKIP }, /* dock */
{ 1, USB_OC_PIN_SKIP }, /* left */
{ 1, USB_OC_PIN_SKIP }, /* right */
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 0f2719a106..07a0083ae3 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -49,7 +49,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[3] = 0x53;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
USB_PORT_BACK_PANEL },
@@ -81,7 +81,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_FRONT_PANEL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; */
{ 1, 0 }, /* P2; */
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index a85935b678..27908c1d98 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -46,7 +46,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x51;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
@@ -64,7 +64,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, USB_OC_PIN_SKIP },
diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c
index 97c888d9e7..5a8f479431 100644
--- a/src/mainboard/msi/h81m-p33/romstage.c
+++ b/src/mainboard/msi/h81m-p33/romstage.c
@@ -23,7 +23,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -41,7 +41,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index ff77854428..f7711c05ca 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -25,7 +25,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[3] = 0x53;
}
-const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_INTERNAL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -43,7 +43,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
-const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 1 },
{ 1, 1 },
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index 14d8b719a9..c455e17d45 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -10,30 +10,30 @@ typedef void (*tx_byte_func)(unsigned char byte);
#define SPD_LEN 256
-#define USB_OC_PIN_SKIP 8
+#define PEI_USB_OC_PIN_SKIP 8
-enum usb2_port_location {
- USB_PORT_BACK_PANEL = 0,
- USB_PORT_FRONT_PANEL,
- USB_PORT_DOCK,
- USB_PORT_MINI_PCIE,
- USB_PORT_FLEX,
- USB_PORT_INTERNAL,
- USB_PORT_SKIP
+enum pei_usb2_port_location {
+ PEI_USB_PORT_BACK_PANEL = 0,
+ PEI_USB_PORT_FRONT_PANEL,
+ PEI_USB_PORT_DOCK,
+ PEI_USB_PORT_MINI_PCIE,
+ PEI_USB_PORT_FLEX,
+ PEI_USB_PORT_INTERNAL,
+ PEI_USB_PORT_SKIP
};
/* Usb Port Length:
* [16:4] = length in inches in octal format
* [3:0] = decimal point
*/
-struct usb2_port_setting {
+struct pei_usb2_port_setting {
uint16_t length;
uint8_t enable;
uint8_t over_current_pin;
uint8_t location;
} __packed;
-struct usb3_port_setting {
+struct pei_usb3_port_setting {
uint8_t enable;
uint8_t over_current_pin;
} __packed;
@@ -80,8 +80,8 @@ struct pei_data
uint32_t max_ddr3_freq;
/* Route all USB ports to XHCI controller in resume path */
int usb_xhci_on_resume;
- struct usb2_port_setting usb2_ports[16];
- struct usb3_port_setting usb3_ports[16];
+ struct pei_usb2_port_setting usb2_ports[16];
+ struct pei_usb3_port_setting usb3_ports[16];
uint8_t spd_data[4][SPD_LEN];
tx_byte_func tx_byte;
} __packed;
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 1f84ffa5cb..5da11299ba 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -309,6 +309,25 @@ static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
}
+static enum pei_usb2_port_location map_to_pei_usb2_location(const enum usb2_port_location loc)
+{
+ static const enum pei_usb2_port_location map[] = {
+ [USB_PORT_SKIP] = PEI_USB_PORT_SKIP,
+ [USB_PORT_BACK_PANEL] = PEI_USB_PORT_BACK_PANEL,
+ [USB_PORT_FRONT_PANEL] = PEI_USB_PORT_FRONT_PANEL,
+ [USB_PORT_DOCK] = PEI_USB_PORT_DOCK,
+ [USB_PORT_MINI_PCIE] = PEI_USB_PORT_MINI_PCIE,
+ [USB_PORT_FLEX] = PEI_USB_PORT_FLEX,
+ [USB_PORT_INTERNAL] = PEI_USB_PORT_INTERNAL,
+ };
+ return loc >= ARRAY_SIZE(map) ? PEI_USB_PORT_SKIP : map[loc];
+}
+
+static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
+{
+ return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
+}
+
void perform_raminit(const int s3resume)
{
const struct device *gbe = pcidev_on_root(0x19, 0);
@@ -337,8 +356,26 @@ void perform_raminit(const int s3resume)
.usb_xhci_on_resume = cfg->usb_xhci_on_resume,
};
- memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports));
- memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports));
+ for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb2_ports); i++) {
+ /* If a port is not enabled, skip it */
+ if (!mainboard_usb2_ports[i].enable) {
+ pei_data.usb2_ports[i].over_current_pin = PEI_USB_OC_PIN_SKIP;
+ pei_data.usb2_ports[i].location = PEI_USB_PORT_SKIP;
+ continue;
+ }
+ const enum usb2_port_location loc = mainboard_usb2_ports[i].location;
+ const uint8_t oc_pin = mainboard_usb2_ports[i].oc_pin;
+ pei_data.usb2_ports[i].length = mainboard_usb2_ports[i].length;
+ pei_data.usb2_ports[i].enable = mainboard_usb2_ports[i].enable;
+ pei_data.usb2_ports[i].over_current_pin = map_to_pei_oc_pin(oc_pin);
+ pei_data.usb2_ports[i].location = map_to_pei_usb2_location(loc);
+ }
+
+ for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb3_ports); i++) {
+ const uint8_t oc_pin = mainboard_usb3_ports[i].oc_pin;
+ pei_data.usb3_ports[i].enable = mainboard_usb3_ports[i].enable;
+ pei_data.usb3_ports[i].over_current_pin = map_to_pei_oc_pin(oc_pin);
+ }
/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
pei_data.boot_mode = s3resume ? 2 : 0;
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 400ac2d4ce..c0f6c639d3 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -3,8 +3,7 @@
#ifndef RAMINIT_H
#define RAMINIT_H
-#include <stdint.h>
-#include "pei_data.h"
+#include <types.h>
#define SPD_MEMORY_DOWN 0xff
@@ -21,9 +20,39 @@ struct spd_info {
#define MAX_USB3_PORTS 6
#endif
+/* There are 8 OC pins */
+#define USB_OC_PIN_SKIP 8
+
+enum usb2_port_location {
+ USB_PORT_SKIP = 0,
+ USB_PORT_BACK_PANEL,
+ USB_PORT_FRONT_PANEL,
+ USB_PORT_DOCK,
+ USB_PORT_MINI_PCIE,
+ USB_PORT_FLEX,
+ USB_PORT_INTERNAL,
+};
+
+/*
+ * USB port length is in MRC format: binary-coded decimal length in tenths of an inch.
+ * 4.2 inches -> 0x0042
+ * 12.7 inches -> 0x0127
+ */
+struct usb2_port_config {
+ uint16_t length;
+ bool enable;
+ unsigned short oc_pin;
+ enum usb2_port_location location;
+};
+
+struct usb3_port_config {
+ bool enable;
+ unsigned int oc_pin;
+};
+
/* Mainboard-specific USB configuration */
-extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
-extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
+extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
+extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
/* Mainboard callback to fill in the SPD addresses */
void mb_get_spd_map(struct spd_info *spdi);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 10:09:06 +0000