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-rw-r--r--src/soc/mediatek/mt8183/dramc_init_setting.c31
-rw-r--r--src/soc/mediatek/mt8183/dramc_pi_basic_api.c18
-rw-r--r--src/soc/mediatek/mt8183/dramc_pi_calibration_api.c45
3 files changed, 59 insertions, 35 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c
index 6f7ae37743..9ae0aae07f 100644
--- a/src/soc/mediatek/mt8183/dramc_init_setting.c
+++ b/src/soc/mediatek/mt8183/dramc_init_setting.c
@@ -56,9 +56,9 @@ static void dvfs_settings(u8 freq_group)
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5);
setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29);
- clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle);
+ clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle);
- setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19);
+ setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19);
setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24);
setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7);
}
@@ -889,12 +889,12 @@ static void dramc_setting_DDR1600(void)
clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8),
(0x0 << 2) | (0x3 << 8));
- clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20);
-
- clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
- (0x2 << 4) | (0x0 << 7) | (0x0 << 13));
- clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20);
- clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13));
+ clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20);
+ clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
+ (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
+ (0x2 << 4) | (0x0 << 7) | (0x0 << 13));
+ clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20);
+ clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) {
int value = ((r == 0) ? 0x1a : 0x26);
@@ -948,11 +948,12 @@ static void dramc_setting_DDR2400(void)
clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
(0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8));
- clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20);
- clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
+ clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20);
+ clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
+ (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
(0x1 << 4) | (0x1 << 7) | (0x1 << 13));
- clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20);
- clrsetbits32(&ch[0].phy.b[1].dq[7],
+ clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20);
+ clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7],
(0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) {
@@ -1056,7 +1057,7 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16),
(0x0 << 6) | (0x0 << 14) | (0x0 << 16));
- clrbits32(&ch[0].phy.pll3, 0x1 < 0);
+ clrbits32(&ch[0].phy.pll3, 0x1 << 0);
setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3);
setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3);
@@ -1087,7 +1088,11 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
for (size_t b = 0; b < 2; b++)
setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10));
+
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0);
+ setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
for (size_t b = 0; b < 2; b++)
clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0],
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index aa156f74f6..4a884b1976 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -47,10 +47,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
broadcast_bak = dramc_get_broadcast();
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
- clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
- write32(&ch[0].phy.misc_spm_ctrl2, 0x0);
- write32(&ch[0].phy.misc_spm_ctrl0, 0x0);
- clrbits32(&ch[0].ao.impcal, 0x1 << 31);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0);
+ write32(&ch[chn].phy.misc_spm_ctrl2, 0x0);
+ write32(&ch[chn].phy.misc_spm_ctrl0, 0x0);
+ clrbits32(&ch[chn].ao.impcal, 0x1 << 31);
+ }
impcal_bak = read32(&ch[0].ao.impcal);
dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP);
@@ -91,7 +93,7 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
if (term == ODT_ON)
setbits32(&ch[0].ao.impcal, 0x1 << 21);
clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11,
- DRVP_result << 4 | 0x1f << 11);
+ DRVP_result << 4);
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) {
@@ -150,9 +152,6 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2];
sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3];
- clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3);
- dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP);
-
/* DQ */
clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0),
(sw_impedance[dq_term][0] << 5) |
@@ -202,7 +201,10 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0],
SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
+ clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
}
static void transfer_pll_to_spm_control(void)
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index aac6d17ed6..ee9b9b6b70 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -365,12 +365,30 @@ void dramc_hw_gating_onoff(u8 chn, bool on)
clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22);
}
-static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn)
+static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group)
{
+ u8 dvs_delay;
+
struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0];
- clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20);
- clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20);
+ switch (freq_group) {
+ case LP4X_DDR1600:
+ dvs_delay = 5;
+ break;
+ case LP4X_DDR2400:
+ dvs_delay = 4;
+ break;
+ case LP4X_DDR3200:
+ case LP4X_DDR3600:
+ dvs_delay = 3;
+ break;
+ default:
+ die("Invalid DDR frequency group %u\n", freq_group);
+ return;
+ }
+
+ clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, dvs_delay << 20);
+ clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, dvs_delay << 20);
clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13));
clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13));
}
@@ -408,7 +426,13 @@ void dramc_apply_config_before_calibration(u8 freq_group)
dramc_hw_gating_onoff(chn, false);
clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28);
- setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11));
+ for (size_t r = 0; r < 2; r++) {
+ for (size_t b = 0; b < 2; b++)
+ clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2],
+ (0x1 << 28) | (0x1 << 23) | (0x3 << 30));
+ clrbits32(&ch[chn].phy.r0_ca_rxdvs[2], 0x3 << 30);
+ }
+ setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7);
clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18);
clrbits32(&ch[chn].ao.mrs, 0x3 << 24);
setbits32(&ch[chn].ao.mpc_option, 0x1 << 17);
@@ -416,21 +440,14 @@ void dramc_apply_config_before_calibration(u8 freq_group)
clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0);
clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
- dramc_rx_input_delay_tracking_init_by_freq(chn);
+ dramc_rx_input_delay_tracking_init_by_freq(chn, freq_group);
setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25);
setbits32(&ch[chn].ao.drsctrl, 0x1 << 0);
if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600)
- clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
+ clrbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31);
else
- setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
- }
-
- for (size_t r = 0; r < 2; r++) {
- for (size_t b = 0; b < 2; b++)
- clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
- (0x1 << 28) | (0x1 << 23) | (0x3 << 30));
- clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30);
+ setbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 07:38:19 +0000