diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_106cx/Kconfig | 9 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 3 |
5 files changed, 13 insertions, 8 deletions
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index fe44024c3c..2ef7392ab9 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -3,3 +3,12 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_LAPIC + +if CPU_INTEL_MODEL_106CX + +config CPU_ADDR_BITS + int + default 32 + +endif + diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index e74e24c0bd..74d0a99dbe 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 32 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 7d402e4d4e..33246ff5bb 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -32,8 +32,7 @@ #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) #define CACHE_MRC_MASK (~CACHE_MRC_BYTES) -#define CPU_MAXPHYSADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define NoEvictMod_MSR 0x2e0 diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 92337c8158..6f13cd916d 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 61feb1d8b5..d8d25a0cb7 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |