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-rw-r--r--src/cpu/intel/haswell/acpi.c90
-rw-r--r--src/cpu/intel/haswell/chip.h8
-rw-r--r--src/mainboard/asrock/b85m_pro4/devicetree.cb7
-rw-r--r--src/mainboard/asrock/h81m-hds/devicetree.cb7
-rw-r--r--src/mainboard/google/beltino/devicetree.cb8
-rw-r--r--src/mainboard/google/slippy/devicetree.cb8
-rw-r--r--src/mainboard/hp/folio_9480m/devicetree.cb8
-rw-r--r--src/mainboard/intel/baskingridge/devicetree.cb8
-rw-r--r--src/mainboard/lenovo/t440p/devicetree.cb6
-rw-r--r--src/mainboard/supermicro/x10slm-f/devicetree.cb7
10 files changed, 27 insertions, 130 deletions
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index b757dc6101..d257d8682a 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -14,6 +14,18 @@
#include <southbridge/intel/lynxpoint/pch.h>
+static int cstate_set_lp[3] = {
+ 2,
+ 3,
+ 9,
+};
+
+static int cstate_set_trad[3] = {
+ 1,
+ 3,
+ 5,
+};
+
static int get_cores_per_package(void)
{
struct cpuinfo_x86 c;
@@ -30,41 +42,6 @@ static int get_cores_per_package(void)
return cores;
}
-static void generate_cstate_entries(acpi_cstate_t *cstates,
- int c1, int c2, int c3)
-{
- int cstate_count = 0;
-
- /* Count number of active C-states */
- if (c1 > 0)
- ++cstate_count;
- if (c2 > 0)
- ++cstate_count;
- if (c3 > 0)
- ++cstate_count;
- if (!cstate_count)
- return;
-
- acpigen_write_package(cstate_count + 1);
- acpigen_write_byte(cstate_count);
-
- /* Add an entry if the level is enabled */
- if (c1 > 0) {
- cstates[c1].ctype = 1;
- acpigen_write_CST_package_entry(&cstates[c1]);
- }
- if (c2 > 0) {
- cstates[c2].ctype = 2;
- acpigen_write_CST_package_entry(&cstates[c2]);
- }
- if (c3 > 0) {
- cstates[c3].ctype = 3;
- acpigen_write_CST_package_entry(&cstates[c3]);
- }
-
- acpigen_pop_len();
-}
-
static acpi_tstate_t tss_table_fine[] = {
{ 100, 1000, 0, 0x00, 0 },
{ 94, 940, 0, 0x1f, 0 },
@@ -119,18 +96,12 @@ static void generate_T_state_entries(int core, int cores_per_package)
static void generate_C_state_entries(void)
{
+ acpi_cstate_t map[3];
+ int *set;
+ int i;
+
struct cpu_info *info;
struct cpu_driver *cpu;
- struct device *lapic;
- struct cpu_intel_haswell_config *conf = NULL;
-
- /* Find the SpeedStep CPU in the device tree using magic APIC ID */
- lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
- if (!lapic)
- return;
- conf = lapic->chip_info;
- if (!conf)
- return;
/* Find CPU map of supported C-states */
info = cpu_info();
@@ -140,25 +111,18 @@ static void generate_C_state_entries(void)
if (!cpu || !cpu->cstates)
return;
- acpigen_emit_byte(0x14); /* MethodOp */
- acpigen_write_len_f(); /* PkgLength */
- acpigen_emit_namestring("_CST");
- acpigen_emit_byte(0x00); /* No Arguments */
-
- /* If running on AC power */
- acpigen_emit_byte(0xa0); /* IfOp */
- acpigen_write_len_f(); /* PkgLength */
- acpigen_emit_namestring("PWRS");
- acpigen_emit_byte(0xa4); /* ReturnOp */
- generate_cstate_entries(cpu->cstates, conf->c1_acpower,
- conf->c2_acpower, conf->c3_acpower);
- acpigen_pop_len();
+ if (haswell_is_ult())
+ set = cstate_set_lp;
+ else
+ set = cstate_set_trad;
- /* Else on battery power */
- acpigen_emit_byte(0xa4); /* ReturnOp */
- generate_cstate_entries(cpu->cstates, conf->c1_battery,
- conf->c2_battery, conf->c3_battery);
- acpigen_pop_len();
+ for (i = 0; i < ARRAY_SIZE(map); i++) {
+ map[i] = cpu->cstates[set[i]];
+ map[i].ctype = i + 1;
+ }
+
+ /* Generate C-state tables */
+ acpigen_write_CST_package(map, ARRAY_SIZE(map));
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index 7c2df103a0..16f1079c32 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -31,14 +31,6 @@ struct cpu_vr_config {
};
struct cpu_intel_haswell_config {
- int c1_battery; /* ACPI C1 on Battery Power */
- int c2_battery; /* ACPI C2 on Battery Power */
- int c3_battery; /* ACPI C3 on Battery Power */
-
- int c1_acpower; /* ACPI C1 on AC Power */
- int c2_acpower; /* ACPI C2 on AC Power */
- int c3_acpower; /* ACPI C3 on AC Power */
-
int tcc_offset; /* TCC Activation Offset */
struct cpu_vr_config vr_config;
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index 024d1f0e1f..43a65f8197 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -5,13 +5,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
- register "c1_acpower" = "1"
- register "c1_battery" = "1"
- register "c2_acpower" = "3"
- register "c2_battery" = "3"
- register "c3_acpower" = "5"
- register "c3_battery" = "5"
-
device lapic 0 on end
device lapic 0xacac off end
end
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
index 45119f9476..7b08af96d8 100644
--- a/src/mainboard/asrock/h81m-hds/devicetree.cb
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -5,13 +5,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
- register "c1_acpower" = "1"
- register "c1_battery" = "1"
- register "c2_acpower" = "3"
- register "c2_battery" = "3"
- register "c3_acpower" = "5"
- register "c3_battery" = "5"
-
device lapic 0 on end
device lapic 0xacac off end
end
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 176fced5ed..8c54f6a6d0 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -18,14 +18,6 @@ chip northbridge/intel/haswell
device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
-
- register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
- register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
-
- register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
- register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
end
end
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 99cae7a406..d98954535f 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -20,14 +20,6 @@ chip northbridge/intel/haswell
device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
-
- register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
- register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
-
- register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
- register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
end
end
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb
index 712d75e2c4..a56a48b1ee 100644
--- a/src/mainboard/hp/folio_9480m/devicetree.cb
+++ b/src/mainboard/hp/folio_9480m/devicetree.cb
@@ -15,14 +15,6 @@ chip northbridge/intel/haswell
register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on
chip cpu/intel/haswell
- register "c1_battery" = "2"
- register "c2_battery" = "3"
- register "c3_battery" = "9"
-
- register "c1_acpower" = "2"
- register "c2_acpower" = "3"
- register "c3_acpower" = "9"
-
device lapic 0 on end
device lapic 0xacac off end
end
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index 797230c8f1..37cff88f30 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -16,14 +16,6 @@ chip northbridge/intel/haswell
device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
-
- register "c1_battery" = "1"
- register "c2_battery" = "3"
- register "c3_battery" = "5"
-
- register "c1_acpower" = "1"
- register "c2_acpower" = "3"
- register "c3_acpower" = "5"
end
end
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
index fb0442d567..8db28cbfae 100644
--- a/src/mainboard/lenovo/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -15,12 +15,6 @@ chip northbridge/intel/haswell
register "ec_present" = "true"
device cpu_cluster 0x0 on
chip cpu/intel/haswell
- register "c1_acpower" = "1"
- register "c1_battery" = "1"
- register "c2_acpower" = "3"
- register "c2_battery" = "3"
- register "c3_acpower" = "5"
- register "c3_battery" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
index 6d64a90221..6cd3ab7933 100644
--- a/src/mainboard/supermicro/x10slm-f/devicetree.cb
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -4,13 +4,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
- register "c1_acpower" = "1"
- register "c1_battery" = "1"
- register "c2_acpower" = "3"
- register "c2_battery" = "3"
- register "c3_acpower" = "5"
- register "c3_battery" = "5"
-
device lapic 0 on end
device lapic 0xacac off end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 16:11:17 +0000