diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/mips/include/arch/memlayout.h | 2 | ||||
| -rw-r--r-- | src/mainboard/google/urara/mainboard.c | 14 | ||||
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 |
3 files changed, 16 insertions, 2 deletions
diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index 4cbbe1d02b..0b30338fbf 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -26,6 +26,6 @@ /* TODO: Double-check that that's the correct alignment for our ABI. */ #define STACK(addr, size) REGION(stack, addr, size, 8) -/* TODO: Need to add DMA_COHERENT region like on ARM? */ +#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c index 1909fc861f..0a0cb020cc 100644 --- a/src/mainboard/google/urara/mainboard.c +++ b/src/mainboard/google/urara/mainboard.c @@ -18,9 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * MA 02110-1301 USA */ - +#include <arch/io.h> +#include <symbols.h> #include <console/console.h> #include <device/device.h> +#include <boot/coreboot_tables.h> static void mainboard_enable(device_t dev) { @@ -31,3 +33,13 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; +} diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 1c7ea9a74c..c3c6c07ebf 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -36,4 +36,6 @@ SECTIONS /* Let's use SRAM for CBFS cache. */ CBFS_CACHE(0x9b000000, 64K) + /* DMA coherent area: end of available DRAM, uncached */ + DMA_COHERENT(0xAFF00000, 1M) } |