diff options
Diffstat (limited to 'src')
40 files changed, 42 insertions, 135 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index e9a987651c..4cd3b3c3ed 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell # This mainboard has VGA register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 25b157d8a3..1c85a299bc 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -16,14 +15,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index 5fbc99f615..5b20f3cca7 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/haswell + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c b/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c index 44932e7229..d2a8680998 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c +++ b/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c @@ -1,21 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) { } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index d84c471bae..b4fe3439b3 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3573d690be..31c5d7111e 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -16,12 +15,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/asrock/z87e-itx/devicetree.cb b/src/mainboard/asrock/z87e-itx/devicetree.cb index 32883e4144..dcc7d5290f 100644 --- a/src/mainboard/asrock/z87e-itx/devicetree.cb +++ b/src/mainboard/asrock/z87e-itx/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/haswell + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/asrock/z87e-itx/romstage.c b/src/mainboard/asrock/z87e-itx/romstage.c index b50390e67c..d2a8680998 100644 --- a/src/mainboard/asrock/z87e-itx/romstage.c +++ b/src/mainboard/asrock/z87e-itx/romstage.c @@ -1,19 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) { } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb index cbde4cbb79..3b56340c9d 100644 --- a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb +++ b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/haswell register "gpu_dp_c_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on diff --git a/src/mainboard/asrock/z87m_oc_formula/romstage.c b/src/mainboard/asrock/z87m_oc_formula/romstage.c index 44932e7229..d2a8680998 100644 --- a/src/mainboard/asrock/z87m_oc_formula/romstage.c +++ b/src/mainboard/asrock/z87m_oc_formula/romstage.c @@ -1,21 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) { } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb index 2258a1bfd1..dcb8123790 100644 --- a/src/mainboard/asrock/z97_extreme6/devicetree.cb +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -8,6 +8,7 @@ chip northbridge/intel/haswell # This mainboard has a DP output register "gpu_dp_c_hotplug" = "7" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c index a344dee1a5..35aece908f 100644 --- a/src/mainboard/asrock/z97_extreme6/romstage.c +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -1,21 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) { } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ diff --git a/src/mainboard/asrock/z97e-itx_ac/devicetree.cb b/src/mainboard/asrock/z97e-itx_ac/devicetree.cb index 2f118db48d..43602d4c3f 100644 --- a/src/mainboard/asrock/z97e-itx_ac/devicetree.cb +++ b/src/mainboard/asrock/z97e-itx_ac/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on diff --git a/src/mainboard/asrock/z97e-itx_ac/romstage.c b/src/mainboard/asrock/z97e-itx_ac/romstage.c index 4abce7b625..3919e990f4 100644 --- a/src/mainboard/asrock/z97e-itx_ac/romstage.c +++ b/src/mainboard/asrock/z97e-itx_ac/romstage.c @@ -1,19 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) { } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb index c408383c70..ee5f1ab545 100644 --- a/src/mainboard/dell/e7240/devicetree.cb +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/haswell register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/e7240/romstage.c index 6b2cb7a80c..c439bfcf15 100644 --- a/src/mainboard/dell/e7240/romstage.c +++ b/src/mainboard/dell/e7240/romstage.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -17,12 +16,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* dock left */ diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb index 841285bb9c..223831cd87 100644 --- a/src/mainboard/dell/optiplex_9020/devicetree.cb +++ b/src/mainboard/dell/optiplex_9020/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell # This mainboard has VGA register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c index 8198eb0503..b9aae99d4c 100644 --- a/src/mainboard/dell/optiplex_9020/romstage.c +++ b/src/mainboard/dell/optiplex_9020/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -15,14 +14,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 9dacd6d71e..95b04ed14a 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -13,6 +13,7 @@ chip northbridge/intel/haswell register "usb_xhci_on_resume" = "true" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index ecf54905e6..8604423d01 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -39,12 +38,6 @@ void mainboard_config_rcba(void) RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 6a8e919ef3..e47e682623 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -13,6 +13,7 @@ chip northbridge/intel/haswell .backlight_pwm_hz = 200, }" register "usb_xhci_on_resume" = "true" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c index fa7cba114d..3b636290d2 100644 --- a/src/mainboard/hp/folio_9480m/romstage.c +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -16,12 +15,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 3226170008..cd2c84ee06 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -11,6 +11,7 @@ chip northbridge/intel/haswell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 936703bce7..0963eb801e 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -40,14 +39,6 @@ void mainboard_config_rcba(void) RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ diff --git a/src/mainboard/lenovo/haswell/romstage.c b/src/mainboard/lenovo/haswell/romstage.c index 9b9a15fa21..518bd4b61c 100644 --- a/src/mainboard/lenovo/haswell/romstage.c +++ b/src/mainboard/lenovo/haswell/romstage.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <option.h> #include <ec/lenovo/pmh7/pmh7.h> diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index f8467c7edc..10e23b3407 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -13,6 +13,7 @@ chip northbridge/intel/haswell .backlight_pwm_hz = 220, }" register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/lenovo/haswell/variants/t440p/romstage.c b/src/mainboard/lenovo/haswell/variants/t440p/romstage.c index f158716ef2..84ddb5b80c 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/t440p/romstage.c @@ -1,16 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x51; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb index 0d705fb9bd..815d3fac97 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb @@ -13,6 +13,7 @@ chip northbridge/intel/haswell .backlight_pwm_hz = 220, }" register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/lenovo/haswell/variants/w541/romstage.c b/src/mainboard/lenovo/haswell/variants/w541/romstage.c index a410f56201..69854dbce4 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/w541/romstage.c @@ -2,19 +2,10 @@ #include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h> -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x52; - spdi->addresses[2] = 0x51; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb index f72ed9ff1b..6051ca66fa 100644 --- a/src/mainboard/msi/h81m-p33/devicetree.cb +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index f4db2644be..1c85a299bc 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -16,12 +15,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 8625daabfa..479de3f815 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/haswell + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 01dab69989..d4609c839a 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> void mainboard_config_rcba(void) @@ -16,14 +15,6 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_INTERNAL }, diff --git a/src/northbridge/intel/haswell/Makefile.mk b/src/northbridge/intel/haswell/Makefile.mk index 8da72dcb1d..bc8cf42046 100644 --- a/src/northbridge/intel/haswell/Makefile.mk +++ b/src/northbridge/intel/haswell/Makefile.mk @@ -16,6 +16,7 @@ romstage-y += memmap.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c +romstage-y += raminit_shared.c postcar-y += memmap.c diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index 0bb6f28a6a..1ed4248594 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -374,9 +374,8 @@ void perform_raminit(const int s3resume) /* Broadwell MRC uses ACPI values for boot_mode */ pei_data.boot_mode = s3resume ? ACPI_S3 : ACPI_S0; - /* Obtain the SPD addresses from mainboard code */ struct spd_info spdi = {0}; - mb_get_spd_map(&spdi); + get_spd_info(&spdi, cfg); /* * Read the SPDs over SMBus in coreboot code so that the data can be used to diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 274e549e2d..dc71340bd6 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -39,6 +39,8 @@ struct northbridge_intel_haswell_config { bool usb_xhci_on_resume; struct i915_gpu_controller_info gfx; + + u8 spd_addresses[4]; }; #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 52bb3b1d65..9a7b7fe2d4 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -391,9 +391,8 @@ void perform_raminit(const int s3resume) /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ pei_data.boot_mode = s3resume ? 2 : 0; - /* Obtain the SPD addresses from mainboard code */ struct spd_info spdi = {0}; - mb_get_spd_map(&spdi); + get_spd_info(&spdi, cfg); /* MRC expects left-aligned SMBus addresses, and 0xff for memory-down */ for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) { diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c index eff993800b..c53ea12320 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/dram/ddr3.h> #include <device/smbus_host.h> +#include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <string.h> @@ -70,8 +71,9 @@ static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t static void get_spd_data(struct sysinfo *ctrl) { + const struct northbridge_intel_haswell_config *cfg = config_of_soc(); struct spd_info spdi = {0}; - mb_get_spd_map(&spdi); + get_spd_info(&spdi, cfg); const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi); for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index e151b46d8b..6c76739e77 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -4,6 +4,7 @@ #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H #include <types.h> +#include "chip.h" #define SPD_MEMORY_DOWN 0xff @@ -15,6 +16,7 @@ struct spd_info { /* Mainboard callback to fill in the SPD addresses */ void mb_get_spd_map(struct spd_info *spdi); +void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg); void perform_raminit(const int s3resume); #endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c new file mode 100644 index 0000000000..90fe1145cc --- /dev/null +++ b/src/northbridge/intel/haswell/raminit_shared.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include "chip.h" +#include "raminit.h" + +void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg) +{ + if (CONFIG(HAVE_SPD_IN_CBFS)) { + /* With memory down: from mainboard code */ + mb_get_spd_map(spdi); + } else { + /* Without memory down: from devicetree */ + memcpy(spdi->addresses, cfg->spd_addresses, ARRAY_SIZE(spdi->addresses)); + } +} |