diff options
Diffstat (limited to 'src')
10 files changed, 74 insertions, 9 deletions
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 39ef2a0795..b2d669c443 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -112,10 +112,15 @@ static void mainboard_configure_gpios(void) override_num_gpios); } +void __weak variant_devtree_update(void) +{ +} + static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); mainboard_ec_init(); + variant_devtree_update(); } static void mainboard_write_blken(void) diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 381cbaaab8..8a9543da2b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -341,8 +341,8 @@ chip soc/amd/cezanne chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" - device i2c 50 on end + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_85)" + device i2c 50 alias cr50 on end end end diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 7062f42dd5..94ed74cff5 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -17,8 +17,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* WAKE_L */ PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_3), /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), /* SD_AUX_RESET_L */ @@ -95,8 +95,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* GPIO_77 - GPIO_83: Not available */ /* EC_SOC_INT_ODL */ PAD_GPI(GPIO_84, PULL_NONE), - /* Unused */ - PAD_NC(GPIO_85), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* RAM_ID_1 / DEV_BEEP_DATA */ @@ -200,14 +200,16 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_GPO(GPIO_24, LOW), /* Enable ESPI, GSC Interrupt & I2C Communication */ - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_3), /* I2C3_SCL */ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 84e3d39644..0fe0b3bae0 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -60,4 +60,5 @@ enum dxio_port_id { uint8_t variant_sd_aux_reset_gpio(void); +void variant_devtree_update(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c b/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c index 4550728afb..aa8eaa0e6a 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c @@ -1,9 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <boardid.h> #include <security/tpm/tis.h> #include <soc/gpio.h> int tis_plat_irq_status(void) { - return gpio_interrupt_status(GPIO_3); + gpio_t irq_gpio = GPIO_85; + uint32_t board_ver = board_id(); + + if (CONFIG(BOARD_GOOGLE_GUYBRUSH) || (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_ver == 1)) + irq_gpio = GPIO_3; + + return gpio_interrupt_status(irq_gpio); } diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 886c1cc9b7..109ca0e018 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -19,6 +19,10 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { PAD_GPI(GPIO_74, PULL_NONE), /* EN_PP5000_PEN */ PAD_GPO(GPIO_5, HIGH), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_85), }; /* This table is used by guybrush variant with board version >= 2. */ @@ -27,6 +31,10 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { PAD_GPO(GPIO_5, HIGH), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, HIGH), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_85), }; static const struct soc_amd_gpio override_early_gpio_table[] = { @@ -35,6 +43,10 @@ static const struct soc_amd_gpio override_early_gpio_table[] = { PAD_GPO(GPIO_69, LOW), /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_85), }; /* This table is used by guybrush variant with board version < 2. */ diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index aefdd3d605..92b19802d8 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -154,6 +154,15 @@ chip soc/amd/cezanne end end # I2C2 + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end # I2C3 + device ref uart_1 on chip drivers/uart/acpi register "name" = ""CRFP"" diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index d147aa9a49..d6cd2623a2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -9,4 +9,6 @@ bootblock-y += variant.c romstage-y += variant.c ramstage-y += variant.c +ramstage-y += ramstage.c + subdirs-y += ./memory diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 2699f2a1cf..9a098dbb66 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -18,6 +18,10 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = { PAD_GPO(GPIO_5, HIGH), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, HIGH), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_85), }; /* This table is used by nipperkin variant with board version >= 2. */ @@ -33,6 +37,8 @@ static const struct soc_amd_gpio bid2_override_gpio_table[] = { }; static const struct soc_amd_gpio override_early_gpio_table[] = { + /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, LOW), diff --git a/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c new file mode 100644 index 0000000000..10428050f0 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> +#include <drivers/i2c/tpm/chip.h> +#include <soc/gpio.h> + +void variant_devtree_update(void) +{ + uint32_t board_ver = board_id(); + const struct device *cr50_dev = DEV_PTR(cr50); + struct drivers_i2c_tpm_config *cfg; + struct acpi_gpio cr50_irq_gpio = ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3); + + if (board_ver > 1) + return; + + cfg = config_of(cr50_dev); + cfg->irq_gpio = cr50_irq_gpio; +} |