diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/i82801gx/chip.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/sata.c | 9 |
2 files changed, 9 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index b775d39ee8..cc17539d7d 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,6 +68,7 @@ struct southbridge_intel_i82801gx_config { uint32_t ide_enable_primary; uint32_t ide_enable_secondary; uint32_t sata_ahci; + uint32_t sata_ports_implemented; int c4onc3_enable:1; }; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index c3908489eb..0e7a1a740c 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -30,6 +30,8 @@ static void sata_init(struct device *dev) { u32 reg32; u16 reg16; + u32 *ahci_bar; + /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -106,9 +108,14 @@ static void sata_init(struct device *dev) /* Set Sata Controller Mode. */ pci_write_config8(dev, 0x90, 0x40); // 40=AHCI - /* Port 0 & 1 enable */ + /* In ACHI mode, bit[3:0] must always be set + * (Port status is controlled through AHCI BAR) + */ pci_write_config8(dev, 0x92, 0x0f); + ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); + ahci_bar[3] = config->sata_ports_implemented; + /* SATA Initialization register */ pci_write_config32(dev, 0x94, 0x1a000180); } else { |