diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/orisa/overridetree.cb | 1 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index 9e6378f6e7..f048dbba13 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -15,7 +15,8 @@ chip soc/intel/alderlake register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8 - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9 + # USB 2.0 Port #10 must be used for integrated BT with Intel CNVi + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10 register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11 register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12 diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 14324d313d..80e5cf3aba 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -91,7 +91,6 @@ chip soc/intel/alderlake register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 |