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-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 628a8cba01..1573cdffbb 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -79,6 +79,14 @@ chip soc/intel/meteorlake
device ref tcss_xhci on end
device ref tcss_dma0 on end
device ref tcss_dma1 on end
+ device ref pcie_rp7 on
+ # Enable PCH PCIE RP 7 using CLK 1
+ register "pcie_rp[PCIE_RP(7)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+ }"
+ end # WWAN
device ref pcie_rp10 on
# Enable SSD Gen4 PCIE 10 using CLK 8
register "pcie_rp[PCIE_RP(10)]" = "{