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-rw-r--r--src/soc/mediatek/mt8183/dramc_init_setting.c18
-rw-r--r--src/soc/mediatek/mt8183/dramc_pi_calibration_api.c27
-rw-r--r--src/soc/mediatek/mt8183/emi.c34
-rw-r--r--src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h6
-rw-r--r--src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h12
-rw-r--r--src/soc/mediatek/mt8183/include/soc/emi.h10
6 files changed, 58 insertions, 49 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c
index 7c95c21da4..2a36b48d5d 100644
--- a/src/soc/mediatek/mt8183/dramc_init_setting.c
+++ b/src/soc/mediatek/mt8183/dramc_init_setting.c
@@ -739,24 +739,24 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank)
return 0;
}
-u8 MR01Value[FSP_MAX] = {0x26, 0x56};
-u8 MR13Value = (1 << 4) | (1 << 3);
-static void dramc_mode_reg_init(u8 freq_group)
+static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr)
{
+ u8 *MR01Value = mr->MR01Value;
u8 MR02Value[FSP_MAX] = {0x12, 0x12};
u8 MR03Value = 0x30;
u8 MR11Value[FSP_MAX] = {0x0, 0x23};
u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = {
{{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} },
};
+ u8 MR13Value;
u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = {
{{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} },
};
u8 MR22Value[FSP_MAX] = {0x38, 0x34};
- MR01Value[FSP_0] &= 0x8f;
- MR01Value[FSP_1] &= 0x8f;
+ MR01Value[FSP_0] = 0x6;
+ MR01Value[FSP_1] = 0x6;
if (freq_group == LP4X_DDR1600) {
MR02Value[0] = 0x12;
@@ -838,6 +838,8 @@ static void dramc_mode_reg_init(u8 freq_group)
(2 << 0) | (MR02Value[operate_fsp] << 16));
}
+ mr->MR13Value = MR13Value;
+
clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24);
clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24);
dramc_set_broadcast(broadcast_bak);
@@ -1730,13 +1732,13 @@ static void ddr_update_ac_timing(u8 freq_group)
}
void dramc_init(const struct sdram_params *params, u8 freq_group,
- const struct dram_impedance *impedance)
+ struct dram_shared_data *shared)
{
- dramc_setting(params, freq_group, impedance);
+ dramc_setting(params, freq_group, &shared->impedance);
dramc_duty_calibration(params, freq_group);
dvfs_settings(freq_group);
- dramc_mode_reg_init(freq_group);
+ dramc_mode_reg_init(freq_group, &shared->mr);
ddr_update_ac_timing(freq_group);
}
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index ab92a7c943..16f28785d3 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -84,9 +84,6 @@ struct per_byte_dly {
u16 final_dly;
};
-extern u8 MR01Value[FSP_MAX];
-extern u8 MR13Value;
-
static void dramc_auto_refresh_switch(u8 chn, bool option)
{
SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, option ? 0 : 1);
@@ -433,24 +430,24 @@ void dramc_apply_config_before_calibration(u8 freq_group)
}
}
-static void dramc_set_mr13_vrcg_to_Normal(u8 chn)
+static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr)
{
- MR13Value &= ~(0x1 << 3);
for (u8 rank = 0; rank < RANK_MAX; rank++)
- dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value);
+ dramc_mode_reg_write_by_rank(chn, rank, 13,
+ mr->MR13Value & ~(0x1 << 3));
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
}
-void dramc_apply_config_after_calibration(void)
+void dramc_apply_config_after_calibration(const struct mr_value *mr)
{
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000);
clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7);
clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2);
clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6);
- dramc_set_mr13_vrcg_to_Normal(chn);
+ dramc_set_mr13_vrcg_to_Normal(chn, mr);
clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3);
clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3);
@@ -936,7 +933,8 @@ static void dramc_rx_dqs_gating_cal_partial(u8 chn, u8 rank,
}
static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
- const struct sdram_params *params, const bool fast_calib)
+ const struct sdram_params *params, const bool fast_calib,
+ const struct mr_value *mr)
{
u8 dqs, fsp, freqDiv = 4;
u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0},
@@ -966,8 +964,7 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
fsp = get_freq_fsq(freq_group);
dramc_rx_dqs_isi_pulse_cg_switch(chn, false);
- MR01Value[fsp] |= 0x80;
- dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]);
+ dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr->MR01Value[fsp] | 0x80);
dramc_rx_dqs_gating_cal_pre(chn, rank);
u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd);
@@ -1048,8 +1045,7 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
write32(regs_bak[i].addr, regs_bak[i].value);
- MR01Value[fsp] &= 0x7f;
- dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]);
+ dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr->MR01Value[fsp]);
dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t,
best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1);
@@ -2099,7 +2095,8 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
(0xff << 8) | (0x9 << 2) | ROEN);
}
-int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group)
+int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group,
+ const struct mr_value *mr)
{
bool fast_calib;
switch (pams->source) {
@@ -2126,7 +2123,7 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group)
dramc_auto_refresh_switch(chn, true);
dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams,
- fast_calib);
+ fast_calib, mr);
dramc_window_perbit_cal(chn, rk, freq_group,
RX_WIN_RD_DQC, pams, fast_calib);
dramc_window_perbit_cal(chn, rk, freq_group,
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index 0e068cd9a6..93e92aceef 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -351,14 +351,14 @@ static void spm_pinmux_setting(void)
static void dfs_init_for_calibration(const struct sdram_params *params,
u8 freq_group,
- struct dram_impedance *impedance)
+ struct dram_shared_data *shared)
{
- dramc_init(params, freq_group, impedance);
+ dramc_init(params, freq_group, shared);
dramc_apply_config_before_calibration(freq_group);
}
static void init_dram(const struct sdram_params *params, u8 freq_group,
- struct dram_impedance *impedance)
+ struct dram_shared_data *shared)
{
global_option_init(params);
emi_init(params);
@@ -367,10 +367,10 @@ static void init_dram(const struct sdram_params *params, u8 freq_group,
dramc_init_pre_settings();
spm_pinmux_setting();
- dramc_sw_impedance_cal(params, ODT_OFF, impedance);
- dramc_sw_impedance_cal(params, ODT_ON, impedance);
+ dramc_sw_impedance_cal(params, ODT_OFF, &shared->impedance);
+ dramc_sw_impedance_cal(params, ODT_ON, &shared->impedance);
- dramc_init(params, freq_group, impedance);
+ dramc_init(params, freq_group, shared);
dramc_apply_config_before_calibration(freq_group);
emi_init2(params);
}
@@ -485,7 +485,7 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
}
static int run_calib(const struct dramc_param *dparam,
- struct dram_impedance *impedance,
+ struct dram_shared_data *shared,
const int shuffle, bool *first_run)
{
const u8 *freq_tbl;
@@ -504,13 +504,13 @@ static int run_calib(const struct dramc_param *dparam,
frequency_table[freq_group], *first_run);
if (*first_run)
- init_dram(params, freq_group, impedance);
+ init_dram(params, freq_group, shared);
else
- dfs_init_for_calibration(params, freq_group, impedance);
+ dfs_init_for_calibration(params, freq_group, shared);
*first_run = false;
dramc_dbg("Start K (current clock: %u\n", params->frequency);
- if (dramc_calibrate_all_channels(params, freq_group) != 0)
+ if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0)
return -1;
dramc_ac_timing_optimize(freq_group);
dramc_dbg("K finished (current clock: %u\n", params->frequency);
@@ -519,30 +519,30 @@ static int run_calib(const struct dramc_param *dparam,
return 0;
}
-static void after_calib(void)
+static void after_calib(const struct mr_value *mr)
{
- dramc_apply_config_after_calibration();
+ dramc_apply_config_after_calibration(mr);
dramc_runtime_config();
}
int mt_set_emi(const struct dramc_param *dparam)
{
- struct dram_impedance impedance;
+ struct dram_shared_data shared;
bool first_run = true;
set_vdram1_vddq_voltage();
if (CONFIG(MT8183_DRAM_DVFS)) {
- if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_3,
+ if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_3,
&first_run) != 0)
return -1;
- if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_2,
+ if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_2,
&first_run) != 0)
return -1;
}
- if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_1, &first_run) != 0)
+ if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_1, &first_run) != 0)
return -1;
- after_calib();
+ after_calib(&shared.mr);
return 0;
}
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
index 5ea9a52423..4da948ec4a 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
@@ -59,4 +59,10 @@ enum {
CBT_BYTE_MODE1
};
+enum {
+ FSP_0 = 0,
+ FSP_1,
+ FSP_MAX
+};
+
#endif /* _DRAMC_COMMON_MT8183_H_ */
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
index 40a516da1d..54f009e9f0 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
@@ -45,12 +45,6 @@ enum dram_te_op {
};
enum {
- FSP_0 = 0,
- FSP_1,
- FSP_MAX
-};
-
-enum {
PASS_RANGE_NA = 0x7fff
};
@@ -107,15 +101,15 @@ void dramc_set_broadcast(u32 onoff);
u32 dramc_get_broadcast(void);
u8 get_freq_fsq(u8 freq_group);
void dramc_init(const struct sdram_params *params, u8 freq_group,
- const struct dram_impedance *impedance);
+ struct dram_shared_data *shared);
void dramc_sw_impedance_save_reg(u8 freq_group,
const struct dram_impedance *impedance);
void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option,
struct dram_impedance *impedance);
void dramc_apply_config_before_calibration(u8 freq_group);
-void dramc_apply_config_after_calibration(void);
+void dramc_apply_config_after_calibration(const struct mr_value *mr);
int dramc_calibrate_all_channels(const struct sdram_params *pams,
- u8 freq_group);
+ u8 freq_group, const struct mr_value *mr);
void dramc_hw_gating_onoff(u8 chn, bool onoff);
void dramc_enable_phy_dcm(bool bEn);
void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);
diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h
index 1b894803bd..255a323d1a 100644
--- a/src/soc/mediatek/mt8183/include/soc/emi.h
+++ b/src/soc/mediatek/mt8183/include/soc/emi.h
@@ -86,6 +86,16 @@ struct dram_impedance {
u32 data[ODT_MAX][4];
};
+struct mr_value {
+ u8 MR01Value[FSP_MAX];
+ u8 MR13Value;
+};
+
+struct dram_shared_data {
+ struct dram_impedance impedance;
+ struct mr_value mr;
+};
+
extern const u8 phy_mapping[CHANNEL_MAX][16];
int complex_mem_test(u8 *start, unsigned int len);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 21:40:45 +0000