diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm64/cpu_ramstage.c | 19 | ||||
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/lib_helpers.h | 22 |
2 files changed, 41 insertions, 0 deletions
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c index 466ca0124f..369bae3c11 100644 --- a/src/arch/arm64/cpu_ramstage.c +++ b/src/arch/arm64/cpu_ramstage.c @@ -117,6 +117,25 @@ static void init_this_cpu(void *arg) printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); dev->ops->init(dev); } + + /* + * Disable coprocessor traps to EL3: + * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR + * and EL2/EL1 access to CPACR_EL1. + * TTA [20] = 0, disable traps for trace register access from any EL. + * TFP [10] = 0, disable traps for floating-point instructions from any + * EL. + */ + raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | + CPTR_EL3_TFP_DISABLE); + + /* + * Allow FPU accesses: + * FPEN [21:20] = 3, disable traps for floating-point instructions from + * EL0/EL1. + * TTA [28] = 0, disable traps for trace register access from EL0/EL1. + */ + raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE); } /* Fill in cpu_info structures according to device tree. */ diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index ba41f45440..1e04d48cfa 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -126,6 +126,28 @@ #define SCTLR_LITTLE_END (0 << SCTLR_ENDIAN_SHIFT) #define SCTLR_BIG_END (1 << SCTLR_ENDIAN_SHIFT) +#define CPTR_EL3_TCPAC_SHIFT (31) +#define CPTR_EL3_TTA_SHIFT (20) +#define CPTR_EL3_TFP_SHIFT (10) +#define CPTR_EL3_TCPAC_DISABLE (0 << CPTR_EL3_TCPAC_SHIFT) +#define CPTR_EL3_TCPAC_ENABLE (1 << CPTR_EL3_TCPAC_SHIFT) +#define CPTR_EL3_TTA_DISABLE (0 << CPTR_EL3_TTA_SHIFT) +#define CPTR_EL3_TTA_ENABLE (1 << CPTR_EL3_TTA_SHIFT) +#define CPTR_EL3_TFP_DISABLE (0 << CPTR_EL3_TFP_SHIFT) +#define CPTR_EL3_TFP_ENABLE (1 << CPTR_EL3_TFP_SHIFT) + +#define CPACR_TTA_SHIFT (28) +#define CPACR_TTA_ENABLE (1 << CPACR_TTA_SHIFT) +#define CPACR_TTA_DISABLE (0 << CPACR_TTA_SHIFT) +#define CPACR_FPEN_SHIFT (20) +/* + * ARMv8-A spec: Values 0b00 and 0b10 both seem to enable traps from el0 and el1 + * for fp reg access. + */ +#define CPACR_TRAP_FP_EL0_EL1 (0 << CPACR_FPEN_SHIFT) +#define CPACR_TRAP_FP_EL0 (1 << CPACR_FPEN_SHIFT) +#define CPACR_TRAP_FP_DISABLE (3 << CPACR_FPEN_SHIFT) + #ifdef __ASSEMBLY__ /* Macro to switch to label based on current el */ |