2 files changed, 4 insertions, 24 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 07013325d6..deadbc567f 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -145,8 +145,9 @@ void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 
 /* CPU identification */
-int haswell_family_model(void);
-int haswell_stepping(void);
-int haswell_is_ult(void);
+static inline int haswell_is_ult(void)
+{
+	return CONFIG(INTEL_LYNXPOINT_LP);
+}
 
 #endif
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 4b73c6a28c..15dcff54dd 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -186,27 +186,6 @@ static const u8 power_limit_time_msr_to_sec[] = {
 	[0x11] = 128,
 };
 
-int haswell_family_model(void)
-{
-	return cpuid_eax(1) & 0x0fff0ff0;
-}
-
-int haswell_stepping(void)
-{
-	return cpuid_eax(1) & 0xf;
-}
-
-/* Dynamically determine if the part is ULT. */
-int haswell_is_ult(void)
-{
-	static int ult = -1;
-
-	if (ult < 0)
-		ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT);
-
-	return ult;
-}
-
 /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate
  * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly
  * when a core is woken up. */