3 files changed, 35 insertions, 2 deletions
diff --git a/src/mainboard/up/squared/bootblock.c b/src/mainboard/up/squared/bootblock.c
index 58064a1b2f..34154e82d9 100644
--- a/src/mainboard/up/squared/bootblock.c
+++ b/src/mainboard/up/squared/bootblock.c
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
-#include <intelblocks/gpio.h>
+#include <soc/gpio.h>
 
 #include "gpio_early.h"
 
-void bootblock_mainboard_init(void)
+void bootblock_mainboard_early_init(void)
 {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }
diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h
index 037fa35609..1aecc189c1 100644
--- a/src/mainboard/up/squared/gpio.h
+++ b/src/mainboard/up/squared/gpio.h
@@ -756,6 +756,25 @@ static const struct pad_config gpio_table[] = {
 
 	/* LPC_FRAMEB - LPC_FRAMEB */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+
+	/*  ------- GPIO Group North ------- */
+
+	/*
+	 * LPSS UART
+	 * Note: It's unconfirmed if this redundancy to the bootblock table is necessary.
+	 */
+
+	/* GPIO_38 - LPSS_UART0_RXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+
+	/* GPIO_39 - LPSS_UART0_TXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
+
+	/* GPIO_42 - LPSS_UART1_RXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+
+	/* GPIO_43 - LPSS_UART1_TXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD),
 };
 
 #endif /* CFG_GPIO_H */
diff --git a/src/mainboard/up/squared/gpio_early.h b/src/mainboard/up/squared/gpio_early.h
index fc7e7e8576..00aefc2d94 100644
--- a/src/mainboard/up/squared/gpio_early.h
+++ b/src/mainboard/up/squared/gpio_early.h
@@ -34,6 +34,20 @@ static const struct pad_config early_gpio_table[] = {
 
 	/* LPC_FRAMEB - LPC_FRAMEB */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+
+	/*  ------- GPIO Group North ------- */
+
+	/* GPIO_38 - LPSS_UART0_RXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+
+	/* GPIO_39 - LPSS_UART0_TXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
+
+	/* GPIO_42 - LPSS_UART1_RXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
+
+	/* GPIO_43 - LPSS_UART1_TXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD),
 };
 
 #endif /* CFG_GPIO_EARLY_H */