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-rw-r--r--src/mainboard/jetway/Kconfig3
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/Kconfig18
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/board_info.txt5
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/devicetree.cb66
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h3
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/romstage.c8
6 files changed, 69 insertions, 34 deletions
diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
index 7e6e29d786..5b55daabb7 100644
--- a/src/mainboard/jetway/Kconfig
+++ b/src/mainboard/jetway/Kconfig
@@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D
bool "J7F4K1G5D"
config BOARD_JETWAY_PA78VM5
bool "PA78VM5 (Fam10)"
+config BOARD_JETWAY_NF81_T56N_LF
+ bool "NF81_T56N_LF"
endchoice
@@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig"
source "src/mainboard/jetway/j7f4k1g2e/Kconfig"
source "src/mainboard/jetway/j7f4k1g5d/Kconfig"
source "src/mainboard/jetway/pa78vm5/Kconfig"
+source "src/mainboard/jetway/nf81-t56n-lf/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index febd8dd1ef..d602ffa119 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -17,7 +18,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-if BOARD_AMD_PERSIMMON
+if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
- select SUPERIO_FINTEK_F81865F
+ select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select HAVE_ACPI_RESUME
+# FIXME: Disable S3 for now. Enable by default once stabilised.
+# select HAVE_ACPI_RESUME
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_4096
+ select BOARD_ROMSIZE_KB_2048
select GFXUMA
config MAINBOARD_DIR
string
- default amd/persimmon
+ default jetway/nf81-t56n-lf
config APIC_ID_OFFSET
hex
@@ -48,7 +50,7 @@ config APIC_ID_OFFSET
config MAINBOARD_PART_NUMBER
string
- default "Persimmon"
+ default "NF81-T56N-LF"
config HW_MEM_HOLE_SIZEK
hex
@@ -101,7 +103,7 @@ config VGA_BIOS
config VGA_BIOS_ID
string
- default "1002,9802"
+ default "1002,9806" # FUSION_G_T56N
config SB800_AHCI_ROM
bool
@@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD
bool
default n
-endif # BOARD_AMD_PERSIMMON
+endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
index 85cb19a9d9..674875153f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
+++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
@@ -1,5 +1,6 @@
-Board name: DBFT1-00-EVAL-KT (Persimmon)
-Category: eval
+Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF
+Category: Mini-ITX
+ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 8b1acd5bb3..347d4a6d47 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
- device pci 4.0 on end # PCIE P2P bridge on-board NIC
+# device pci 1.1 on end # Internal Audio P2P bridge 0x1314
+ device pci 4.0 off end
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
@@ -50,47 +52,64 @@ chip northbridge/amd/agesa/family14/root_complex
device i2c 51 on end
end
end # SM
- device pci 14.1 on end # IDE 0x439c
+ device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/fintek/f81865f
- device pnp 4e.0 off # Floppy
+ chip superio/fintek/f71869ad
+# XXX: 4e is the default index port and .xy is the
+# LDN indexing the pnp_info array found in the superio.c
+# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
+# see page 18 from Fintek F71869 V1.1 datasheet.
+ device pnp 2e.00 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 4e.3 off end # Parallel Port
- device pnp 4e.4 off end # Hardware Monitor
- device pnp 4e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 4e.6 off end # GPIO
- device pnp 4e.a off end # PME
- device pnp 4e.10 on # COM1
+ device pnp 2e.01 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 4e.11 on # COM2
+# COM2 not physically wired on board.
+ device pnp 2e.02 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- end # f81865f
+ device pnp 2e.03 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.04 on # Hardware Monitor
+ io 0x60 = 0x295
+ irq 0x70 = 0
+ end
+ device pnp 2e.05 on # KBC
+ io 0x60 = 0x060
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+ end
+ device pnp 2e.06 off end # GPIO
+# TODO: Verify BSEL register content with vendor BIOS using
+# $ sudo isadump 0x4e 0x4f 0x7
+# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
+ device pnp 2e.07 on end # BSEL
+ device pnp 2e.0a off end # PME
+ end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
- device pci 14.5 off end # OHCI FS/LS USB
+ device pci 14.5 on end # OHCI FS/LS USB (0x4399)
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
- device pci 15.0 off end # PCIe PortA
+ device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
- device pci 16.0 off end # OHCI USB 10-13
- device pci 16.2 off end # EHCI USB 10-13
+ device pci 16.0 on end # OHCI USB 10-13 (0x4397)
+ device pci 16.2 on end # EHCI USB 10-13 (0x4396)
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- #set up SB800 Fan control registers and IMC fan controls
+ # Set up SB800 Fan control registers and IMC fan controls
+ # TODO: verify SB handles the HW monitor and not the super io (PME)
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
register "fan0_enabled" = "1"
register "fan1_enabled" = "1"
@@ -150,6 +169,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end
device pci 18.7 on end
+#
+# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
+# with i2cdump tool.
+# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
+#
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
index f084b2f170..ce08bee1e7 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -211,6 +212,7 @@
*/
#define GEC_CONFIG 0
+/* FIXME: Verify this for sound to work! */
static const CODECENTRY persimmon_codec_alc269[] =
{
/* NID, PinConfig */
@@ -228,6 +230,7 @@ static const CODECENTRY persimmon_codec_alc269[] =
{0xff, 0xffffffff} /* end of table */
};
+/* FIXME: Verify this for sound to work! */
static const CODECTBLLIST codec_tablelist[] =
{
{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 98c64eda44..12149210b6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@
#include <cpu/x86/mtrr.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/fintek/f71869ad/f71869ad.h"
#include "cpu/x86/lapic.h"
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
@@ -45,7 +46,8 @@
void disable_cache_as_ram(void); /* cache_as_ram.inc */
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
+#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -70,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init();
post_code(0x31);
- f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:49:47 +0000