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-rw-r--r--src/soc/intel/cannonlake/Makefile.inc1
-rw-r--r--src/soc/intel/cannonlake/finalize.c146
-rw-r--r--src/soc/intel/cannonlake/include/soc/pmc.h3
-rw-r--r--src/soc/intel/cannonlake/lockdown.c113
4 files changed, 263 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 6fcee31adb..1076e10efe 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -30,6 +30,7 @@ romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += acpi.c
ramstage-y += chip.c
ramstage-y += cpu.c
+ramstage-y += finalize.c
ramstage-y += gpio.c
ramstage-y += gspi.c
ramstage-y += gpio.c
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
new file mode 100644
index 0000000000..8aa7c04302
--- /dev/null
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootstate.h>
+#include <chip.h>
+#include <console/console.h>
+#include <console/post_codes.h>
+#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <reg_script.h>
+#include <spi-generic.h>
+#include <soc/p2sb.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+#include <soc/systemagent.h>
+#include <stdlib.h>
+
+#define PSF_BASE_ADDRESS 0x300
+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
+
+static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
+{
+ uint32_t reg32;
+
+ reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));
+ pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);
+}
+
+static void disable_sideband_access(void)
+{
+ device_t dev;
+ u8 reg8;
+ uint32_t mask;
+
+ dev = PCH_DEV_P2SB;
+
+ /* Remove the host accessing right to PSF register range. */
+ /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */
+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
+ pch_configure_endpoints(dev, 5, mask);
+
+ /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */
+ reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);
+ pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));
+}
+
+static void pch_disable_heci(void)
+{
+ device_t dev = PCH_DEV_P2SB;
+
+ /*
+ * if p2sb device 1f.1 is not present or hidden in devicetree
+ * p2sb device becomes NULL
+ */
+ if (!dev)
+ return;
+
+ /* unhide p2sb device */
+ pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
+
+ /* disable heci#1 */
+ pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
+ PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
+
+ disable_sideband_access();
+
+ /* hide p2sb device */
+ pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);
+}
+
+static void pch_finalize(void)
+{
+ device_t dev;
+ uint32_t reg32;
+ uint16_t tcobase, tcocnt;
+ uint8_t *pmcbase;
+ config_t *config;
+ uint8_t reg8;
+
+ /* TCO Lock down */
+ tcobase = smbus_tco_regs();
+ tcocnt = inw(tcobase + TCO1_CNT);
+ tcocnt |= TCO_LOCK;
+ outw(tcocnt, tcobase + TCO1_CNT);
+
+ /*
+ * Disable ACPI PM timer based on dt policy
+ *
+ * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
+ * Disabling ACPI PM timer also switches off TCO
+ */
+ dev = PCH_DEV_PMC;
+ config = dev->chip_info;
+ pmcbase = pmc_mmio_regs();
+ if (config->PmTimerDisabled) {
+ reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
+ reg8 |= (1 << 1);
+ write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
+ }
+
+ /* Disable XTAL shutdown qualification for low power idle. */
+ if (config->s0ix_enable) {
+ reg32 = read32(pmcbase + CPPMVRIC);
+ reg32 |= XTALSDQDIS;
+ write32(pmcbase + CPPMVRIC, reg32);
+ }
+
+ /* we should disable Heci1 based on the devicetree policy */
+ if (config->HeciEnabled == 0)
+ pch_disable_heci();
+}
+
+static void soc_finalize(void *unused)
+{
+ printk(BIOS_DEBUG, "Finalizing chipset.\n");
+
+ pch_finalize();
+
+ printk(BIOS_DEBUG, "Finalizing SMM.\n");
+ outb(APM_CNT_FINALIZE, APM_CNT);
+
+ /* Indicate finalize step with post code */
+ post_code(POST_OS_BOOT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index a98b4bad7f..fd28859fa3 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -120,6 +120,9 @@
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
#define GBLRST_CAUSE1 0x1928
+#define CPPMVRIC 0x1B1C
+#define XTALSDQDIS (1 << 22)
+
#define IRQ_REG ACTL
#define SCI_IRQ_ADJUST 0
#define ACTL 0x1BD8
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
new file mode 100644
index 0000000000..dba59014db
--- /dev/null
+++ b/src/soc/intel/cannonlake/lockdown.c
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootstate.h>
+#include <chip.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <string.h>
+
+#define PCR_DMI_GCS 0x274C
+#define PCR_DMI_GCS_BILD (1 << 0)
+
+static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
+{
+ uint8_t *pmcbase;
+ uint32_t reg32, pmsyncreg;
+
+ /* PMSYNC */
+ pmcbase = pmc_mmio_regs();
+ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
+ pmsyncreg |= PMSYNC_LOCK;
+ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+
+ /* Lock down ABASE and sleep stretching policy */
+ reg32 = read32(pmcbase + GEN_PMCON_B);
+ reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+ write32(pmcbase + GEN_PMCON_B, reg32);
+
+ if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ pmcbase = pmc_mmio_regs();
+ reg8 = read8(pmcbase + GEN_PMCON_B);
+ reg8 |= SMI_LOCK;
+ write8(pmcbase + GEN_PMCON_B, reg8);
+ }
+}
+
+static void dmi_lockdown_cfg(void)
+{
+ /*
+ * GCS reg of DMI
+ *
+ * When set, prevents GCS.BBS from being changed
+ * GCS.BBS: (Boot BIOS Strap) This field determines the destination
+ * of accesses to the BIOS memory range.
+ * Bits Description
+ * “0b”: SPI
+ * “1b”: LPC/eSPI
+ */
+ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
+}
+
+static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
+{
+ /* Set FAST_SPI opcode menu */
+ fast_spi_set_opcode_menu();
+
+ /* Discrete Lock Flash PR registers */
+ fast_spi_pr_dlock();
+
+ /* Lock FAST_SPIBAR */
+ fast_spi_lock_bar();
+
+ /* Set Bios Interface Lock, Bios Lock */
+ if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ /* Bios Interface Lock */
+ fast_spi_set_bios_interface_lock_down();
+
+ /* Bios Lock */
+ fast_spi_set_lock_enable();
+ }
+}
+
+static void platform_lockdown_config(void *unused)
+{
+ struct soc_intel_cannonlake_config *config;
+ struct device *dev;
+
+ dev = PCH_DEV_SPI;
+ /* Check if device is valid, else return */
+ if (dev == NULL || dev->chip_info == NULL)
+ return;
+
+ config = dev->chip_info;
+
+ /* SPI lock down configuration */
+ spi_lockdown_cfg(config);
+
+ /* DMI lock down configuration */
+ dmi_lockdown_cfg();
+
+ /* PMC lock down configuration */
+ pmc_lockdown_cfg(config);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
+ NULL);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 16:48:34 +0000